^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i.MX8 OCOTP fusebox driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Peng Fan <peng.fan@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/firmware/imx/sci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX_SIP_OTP_WRITE 0xc200000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum ocotp_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) IMX8QXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) IMX8QM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ECC_REGION BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HOLE_REGION BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct ocotp_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct ocotp_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 num_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ocotp_region region[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct ocotp_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const struct ocotp_devtype_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct imx_sc_ipc *nvmem_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct imx_sc_msg_misc_fuse_read {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static DEFINE_MUTEX(scu_ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct ocotp_devtype_data imx8qxp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .devtype = IMX8QXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .nregs = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .num_region = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .region = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {0x10, 0x10f, ECC_REGION},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {0x110, 0x21F, HOLE_REGION},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {0x220, 0x31F, ECC_REGION},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct ocotp_devtype_data imx8qm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .devtype = IMX8QM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .nregs = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .num_region = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .region = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {0x10, 0x10f, ECC_REGION},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {0x1a0, 0x1ff, ECC_REGION},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static bool in_hole(void *context, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct ocotp_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct ocotp_devtype_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) for (i = 0; i < data->num_region; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (data->region[i].flag & HOLE_REGION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if ((index >= data->region[i].start) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (index <= data->region[i].end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static bool in_ecc(void *context, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ocotp_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const struct ocotp_devtype_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (i = 0; i < data->num_region; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (data->region[i].flag & ECC_REGION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if ((index >= data->region[i].start) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (index <= data->region[i].end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int imx_sc_misc_otp_fuse_read(struct imx_sc_ipc *ipc, u32 word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct imx_sc_msg_misc_fuse_read msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct imx_sc_rpc_msg *hdr = &msg.hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) hdr->ver = IMX_SC_RPC_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) hdr->svc = IMX_SC_RPC_SVC_MISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) hdr->func = IMX_SC_MISC_FUNC_OTP_FUSE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) hdr->size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) msg.word = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = imx_scu_call_rpc(ipc, &msg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *val = msg.word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int imx_scu_ocotp_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct ocotp_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 count, index, num_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) index = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) num_bytes = round_up(bytes, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) count = num_bytes >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (count > (priv->data->nregs - index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) count = priv->data->nregs - index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) p = kzalloc(num_bytes, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mutex_lock(&scu_ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) buf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = index; i < (index + count); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (in_hole(context, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *buf++ = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = imx_sc_misc_otp_fuse_read(priv->nvmem_ipc, i, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mutex_unlock(&scu_ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) memcpy(val, (u8 *)p, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mutex_unlock(&scu_ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int imx_scu_ocotp_write(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct ocotp_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* allow only writing one complete OTP word at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (bytes != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) index = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (in_hole(context, index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (in_ecc(context, index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_warn("ECC region, only program once\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mutex_lock(&scu_ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = imx_sc_misc_otp_fuse_read(priv->nvmem_ipc, index, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mutex_unlock(&scu_ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pr_warn("ECC region, already has value: %x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mutex_lock(&scu_ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) arm_smccc_smc(IMX_SIP_OTP_WRITE, index, *buf, 0, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mutex_unlock(&scu_ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct nvmem_config imx_scu_ocotp_nvmem_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = "imx-scu-ocotp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .read_only = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .word_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .reg_read = imx_scu_ocotp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .reg_write = imx_scu_ocotp_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct of_device_id imx_scu_ocotp_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .compatible = "fsl,imx8qxp-scu-ocotp", (void *)&imx8qxp_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { .compatible = "fsl,imx8qm-scu-ocotp", (void *)&imx8qm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_DEVICE_TABLE(of, imx_scu_ocotp_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int imx_scu_ocotp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct ocotp_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = imx_scu_get_handle(&priv->nvmem_ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) priv->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) imx_scu_ocotp_nvmem_config.size = 4 * priv->data->nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) imx_scu_ocotp_nvmem_config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) imx_scu_ocotp_nvmem_config.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) nvmem = devm_nvmem_register(dev, &imx_scu_ocotp_nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return PTR_ERR_OR_ZERO(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct platform_driver imx_scu_ocotp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .probe = imx_scu_ocotp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .name = "imx_scu_ocotp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .of_match_table = imx_scu_ocotp_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) module_platform_driver(imx_scu_ocotp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_DESCRIPTION("i.MX8 SCU OCOTP fuse box driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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