^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i.MX IIM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Pengutronix, Michael Grzeschik <m.grzeschik@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the barebox iim driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Orex Computed Radiography
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IIM_BANK_BASE(n) (0x800 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct imx_iim_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct iim_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int imx_iim_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void *buf, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct iim_priv *iim = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 *buf8 = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret = clk_prepare_enable(iim->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) for (i = offset; i < offset + bytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int bank = i >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int reg = i & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *buf8++ = readl(iim->base + IIM_BANK_BASE(bank) + reg * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clk_disable_unprepare(iim->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct imx_iim_drvdata imx27_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .nregs = 2 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct imx_iim_drvdata imx25_imx31_imx35_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .nregs = 3 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct imx_iim_drvdata imx51_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .nregs = 4 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct imx_iim_drvdata imx53_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .nregs = 4 * 32 + 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct of_device_id imx_iim_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .compatible = "fsl,imx25-iim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .data = &imx25_imx31_imx35_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .compatible = "fsl,imx27-iim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .data = &imx27_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .compatible = "fsl,imx31-iim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .data = &imx25_imx31_imx35_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .compatible = "fsl,imx35-iim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .data = &imx25_imx31_imx35_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .compatible = "fsl,imx51-iim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .data = &imx51_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .compatible = "fsl,imx53-iim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .data = &imx53_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MODULE_DEVICE_TABLE(of, imx_iim_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int imx_iim_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct iim_priv *iim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct nvmem_config cfg = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const struct imx_iim_drvdata *drvdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) iim = devm_kzalloc(dev, sizeof(*iim), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!iim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) iim->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (IS_ERR(iim->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return PTR_ERR(iim->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) of_id = of_match_device(imx_iim_dt_ids, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) drvdata = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) iim->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (IS_ERR(iim->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return PTR_ERR(iim->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cfg.name = "imx-iim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cfg.read_only = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) cfg.word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cfg.stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cfg.reg_read = imx_iim_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) cfg.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cfg.size = drvdata->nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cfg.priv = iim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) nvmem = devm_nvmem_register(dev, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return PTR_ERR_OR_ZERO(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct platform_driver imx_iim_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .probe = imx_iim_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "imx-iim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .of_match_table = imx_iim_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) module_platform_driver(imx_iim_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MODULE_AUTHOR("Michael Grzeschik <m.grzeschik@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MODULE_DESCRIPTION("i.MX IIM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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