^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2016 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * # of tries for OTP Status. The time to execute a command varies. The slowest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * commands are writes which also vary based on the # of bits turned on. Writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 0xffffffff takes ~3800 us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OTPC_RETRIES 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Sequence to enable OTP program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OTPC_PROG_EN_SEQ { 0xf, 0x4, 0x8, 0xd }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* OTPC Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OTPC_CMD_READ 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OTPC_CMD_OTP_PROG_ENABLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OTPC_CMD_OTP_PROG_DISABLE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OTPC_CMD_PROGRAM 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* OTPC Status Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OTPC_STAT_CMD_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OTPC_STAT_PROG_OK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* OTPC register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OTPC_MODE_REG_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OTPC_MODE_REG_OTPC_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OTPC_COMMAND_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OTPC_COMMAND_COMMAND_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OTPC_CMD_START_OFFSET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OTPC_CMD_START_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OTPC_CPU_STATUS_OFFSET 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OTPC_CPUADDR_REG_OFFSET 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OTPC_CPU_WRITE_REG_OFFSET 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OTPC_CMD_MASK (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct otpc_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* in words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 otpc_row_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* 128 bit row / 4 words support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 data_r_offset[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 128 bit row / 4 words support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 data_w_offset[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct otpc_map otp_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .otpc_row_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .data_r_offset = {0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .data_w_offset = {0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct otpc_map otp_map_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .otpc_row_size = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .data_r_offset = {0x10, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .data_w_offset = {0x2c, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct otpc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) const struct otpc_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct nvmem_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline void set_command(void __iomem *base, u32 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void set_cpu_address(void __iomem *base, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline void set_start_bit(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void reset_start_bit(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(0, base + OTPC_CMD_START_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void write_cpu_data(void __iomem *base, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int poll_cpu_status(void __iomem *base, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) for (retries = 0; retries < OTPC_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) status = readl(base + OTPC_CPU_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (status & value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (retries == OTPC_RETRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int enable_ocotp_program(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const u32 vals[] = OTPC_PROG_EN_SEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Write the magic sequence to enable programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) set_command(base, OTPC_CMD_OTP_PROG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) for (i = 0; i < ARRAY_SIZE(vals); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) write_cpu_data(base, vals[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) set_start_bit(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reset_start_bit(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return poll_cpu_status(base, OTPC_STAT_PROG_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int disable_ocotp_program(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) set_command(base, OTPC_CMD_OTP_PROG_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) set_start_bit(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = poll_cpu_status(base, OTPC_STAT_PROG_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) reset_start_bit(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int bcm_otpc_read(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct otpc_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 bytes_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 address = offset / priv->config->word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (bytes_read = 0; bytes_read < bytes;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) set_command(priv->base, OTPC_CMD_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) set_cpu_address(priv->base, address++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) set_start_bit(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(priv->dev, "otp read error: 0x%x", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = 0; i < priv->map->otpc_row_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *buf++ = readl(priv->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv->map->data_r_offset[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bytes_read += sizeof(*buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) reset_start_bit(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int bcm_otpc_write(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct otpc_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 bytes_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 address = offset / priv->config->word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (offset % priv->config->word_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = enable_ocotp_program(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for (bytes_written = 0; bytes_written < bytes;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) set_command(priv->base, OTPC_CMD_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) set_cpu_address(priv->base, address++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = 0; i < priv->map->otpc_row_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) writel(*buf, priv->base + priv->map->data_w_offset[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bytes_written += sizeof(*buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) set_start_bit(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) reset_start_bit(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(priv->dev, "otp write error: 0x%x", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) disable_ocotp_program(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct nvmem_config bcm_otpc_nvmem_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "bcm-ocotp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .read_only = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .word_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .reg_read = bcm_otpc_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .reg_write = bcm_otpc_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct of_device_id bcm_otpc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .compatible = "brcm,ocotp", .data = &otp_map },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .compatible = "brcm,ocotp-v2", .data = &otp_map_v2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct acpi_device_id bcm_otpc_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int bcm_otpc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct otpc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 num_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) priv->map = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!priv->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Get OTP base address register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) priv->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (IS_ERR(priv->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(dev, "unable to map I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Enable CPU access to OTPC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writel(readl(priv->base + OTPC_MODE_REG_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) BIT(OTPC_MODE_REG_OTPC_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) priv->base + OTPC_MODE_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) reset_start_bit(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Read size of memory in words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) err = device_property_read_u32(dev, "brcm,ocotp-size", &num_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(dev, "size parameter not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } else if (num_words == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(dev, "size must be > 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bcm_otpc_nvmem_config.size = 4 * num_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bcm_otpc_nvmem_config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bcm_otpc_nvmem_config.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (priv->map == &otp_map_v2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) bcm_otpc_nvmem_config.word_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bcm_otpc_nvmem_config.stride = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) priv->config = &bcm_otpc_nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) nvmem = devm_nvmem_register(dev, &bcm_otpc_nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (IS_ERR(nvmem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(dev, "error registering nvmem config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return PTR_ERR(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct platform_driver bcm_otpc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .probe = bcm_otpc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = "brcm-otpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .of_match_table = bcm_otpc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .acpi_match_table = ACPI_PTR(bcm_otpc_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) module_platform_driver(bcm_otpc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MODULE_DESCRIPTION("Broadcom OTPC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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