^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015-2016 HGST, a Western Digital Company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _NVMET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _NVMET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kref.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/percpu-refcount.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/uuid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/nvme.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/configfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/rcupdate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/radix-tree.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/t10-pi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NVMET_DEFAULT_VS NVME_VS(1, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NVMET_ASYNC_EVENTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NVMET_ERROR_LOG_SLOTS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NVMET_NO_ERROR_LOC ((u16)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NVMET_DEFAULT_CTRL_MODEL "Linux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Supported optional AENs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NVMET_AEN_CFG_OPTIONAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_ANA_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NVMET_DISC_AEN_CFG_OPTIONAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (NVME_AEN_CFG_DISC_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Plus mandatory SMART AENs (we'll never send them, but allow enabling them):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NVMET_AEN_CFG_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) (NVME_SMART_CRIT_SPARE | NVME_SMART_CRIT_TEMPERATURE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) NVME_SMART_CRIT_RELIABILITY | NVME_SMART_CRIT_MEDIA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) NVME_SMART_CRIT_VOLATILE_MEMORY | NVMET_AEN_CFG_OPTIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Helper Macros when NVMe error is NVME_SC_CONNECT_INVALID_PARAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * The 16 bit shift is to set IATTR bit to 1, which means offending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * offset starts in the data section of connect()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IPO_IATTR_CONNECT_DATA(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (cpu_to_le32((1 << 16) | (offsetof(struct nvmf_connect_data, x))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IPO_IATTR_CONNECT_SQE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (cpu_to_le32(offsetof(struct nvmf_connect_command, x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct nvmet_ns {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct percpu_ref ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct block_device *bdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct file *file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bool readonly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 nsid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 blksize_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) loff_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 nguid[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) uuid_t uuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 anagrpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool buffered_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct nvmet_subsys *subsys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const char *device_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct config_group device_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct config_group group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct completion disable_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mempool_t *bvec_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct kmem_cache *bvec_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int use_p2pmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct pci_dev *p2p_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int pi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int metadata_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline struct nvmet_ns *to_nvmet_ns(struct config_item *item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return container_of(to_config_group(item), struct nvmet_ns, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline struct device *nvmet_ns_dev(struct nvmet_ns *ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ns->bdev ? disk_to_dev(ns->bdev->bd_disk) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct nvmet_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct nvmet_sq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct nvmet_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct percpu_ref ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 sqhd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool sqhd_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct completion free_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct completion confirm_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct nvmet_ana_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct config_group group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct nvmet_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 grpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline struct nvmet_ana_group *to_ana_group(struct config_item *item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return container_of(to_config_group(item), struct nvmet_ana_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * struct nvmet_port - Common structure to keep port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * information for the target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @entry: Entry into referrals or transport list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @disc_addr: Address information is stored in a format defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * for a discovery log page entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @group: ConfigFS group for this element's folder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @priv: Private data for the transport.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct nvmet_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct nvmf_disc_rsp_page_entry disc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct config_group group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct config_group subsys_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct list_head subsystems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct config_group referrals_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct list_head referrals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct list_head global_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct config_group ana_groups_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct nvmet_ana_group ana_default_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum nvme_ana_state *ana_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int inline_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const struct nvmet_fabrics_ops *tr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool pi_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline struct nvmet_port *to_nvmet_port(struct config_item *item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return container_of(to_config_group(item), struct nvmet_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline struct nvmet_port *ana_groups_to_port(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct config_item *item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return container_of(to_config_group(item), struct nvmet_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ana_groups_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct nvmet_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct nvmet_subsys *subsys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct nvmet_sq **sqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool reset_tbkas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 csts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) uuid_t hostid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 cntlid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 kato;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct nvmet_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 aen_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long aen_masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct nvmet_req *async_event_cmds[NVMET_ASYNC_EVENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int nr_async_event_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct list_head async_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct work_struct async_event_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct list_head subsys_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct kref ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct delayed_work ka_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct work_struct fatal_err_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) const struct nvmet_fabrics_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __le32 *changed_ns_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 nr_changed_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) char subsysnqn[NVMF_NQN_FIELD_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) char hostnqn[NVMF_NQN_FIELD_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct device *p2p_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct radix_tree_root p2p_ns_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spinlock_t error_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u64 err_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct nvme_error_slot slots[NVMET_ERROR_LOG_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool pi_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct nvmet_subsys_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct rcu_head rcuhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) char number[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct nvmet_subsys {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) enum nvme_subsys_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct kref ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct xarray namespaces;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int nr_namespaces;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int max_nsid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 cntlid_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u16 cntlid_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct list_head ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct list_head hosts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bool allow_any_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 max_qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u64 ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u64 serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) char *subsysnqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bool pi_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct config_group group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct config_group namespaces_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct config_group allowed_hosts_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct nvmet_subsys_model __rcu *model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #ifdef CONFIG_NVME_TARGET_PASSTHRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct nvme_ctrl *passthru_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) char *passthru_ctrl_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct config_group passthru_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif /* CONFIG_NVME_TARGET_PASSTHRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static inline struct nvmet_subsys *to_subsys(struct config_item *item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return container_of(to_config_group(item), struct nvmet_subsys, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static inline struct nvmet_subsys *namespaces_to_subsys(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct config_item *item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return container_of(to_config_group(item), struct nvmet_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) namespaces_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct nvmet_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct config_group group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline struct nvmet_host *to_host(struct config_item *item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return container_of(to_config_group(item), struct nvmet_host, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static inline char *nvmet_host_name(struct nvmet_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return config_item_name(&host->group.cg_item);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct nvmet_host_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct nvmet_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct nvmet_subsys_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct nvmet_subsys *subsys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct nvmet_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct nvmet_fabrics_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int msdbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define NVMF_KEYED_SGLS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define NVMF_METADATA_SUPPORTED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void (*queue_response)(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int (*add_port)(struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void (*remove_port)(struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) void (*delete_ctrl)(struct nvmet_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) void (*disc_traddr)(struct nvmet_req *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct nvmet_port *port, char *traddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 (*install_queue)(struct nvmet_sq *nvme_sq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void (*discovery_chg)(struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 (*get_mdts)(const struct nvmet_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define NVMET_MAX_INLINE_BIOVEC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define NVMET_MAX_INLINE_DATA_LEN NVMET_MAX_INLINE_BIOVEC * PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct nvmet_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct nvme_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct nvme_completion *cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct nvmet_sq *sq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct nvmet_cq *cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct nvmet_ns *ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct scatterlist *metadata_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct bio_vec inline_bvec[NVMET_MAX_INLINE_BIOVEC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct bio inline_bio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) bool mpool_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct kiocb iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct bio_vec *bvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct request *rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bool use_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int sg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int metadata_sg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* data length as parsed from the SGL descriptor: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) size_t transfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) size_t metadata_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct nvmet_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) void (*execute)(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) const struct nvmet_fabrics_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct pci_dev *p2p_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct device *p2p_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u16 error_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u64 error_slba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) extern struct workqueue_struct *buffered_io_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static inline void nvmet_set_result(struct nvmet_req *req, u32 result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) req->cqe->result.u32 = cpu_to_le32(result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * NVMe command writes actually are DMA reads for us on the target side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline enum dma_data_direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) nvmet_data_dir(struct nvmet_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return nvme_is_write(req->cmd) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct nvmet_async_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 event_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 event_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 log_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline void nvmet_clear_aen_bit(struct nvmet_req *req, u32 bn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int rae = le32_to_cpu(req->cmd->common.cdw10) & 1 << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!rae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) clear_bit(bn, &req->sq->ctrl->aen_masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static inline bool nvmet_aen_bit_disabled(struct nvmet_ctrl *ctrl, u32 bn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!(READ_ONCE(ctrl->aen_enabled) & (1 << bn)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return test_and_set_bit(bn, &ctrl->aen_masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void nvmet_get_feat_kato(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) void nvmet_get_feat_async_event(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u16 nvmet_set_feat_kato(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u16 nvmet_set_feat_async_event(struct nvmet_req *req, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) void nvmet_execute_async_event(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void nvmet_start_keep_alive_timer(struct nvmet_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) void nvmet_stop_keep_alive_timer(struct nvmet_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u16 nvmet_parse_connect_cmd(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void nvmet_bdev_set_limits(struct block_device *bdev, struct nvme_id_ns *id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u16 nvmet_bdev_parse_io_cmd(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u16 nvmet_file_parse_io_cmd(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u16 nvmet_parse_admin_cmd(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u16 nvmet_parse_discovery_cmd(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u16 nvmet_parse_fabrics_cmd(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) bool nvmet_req_init(struct nvmet_req *req, struct nvmet_cq *cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct nvmet_sq *sq, const struct nvmet_fabrics_ops *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void nvmet_req_uninit(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bool nvmet_check_transfer_len(struct nvmet_req *req, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) bool nvmet_check_data_len_lte(struct nvmet_req *req, size_t data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void nvmet_req_complete(struct nvmet_req *req, u16 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int nvmet_req_alloc_sgls(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void nvmet_req_free_sgls(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void nvmet_execute_set_features(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void nvmet_execute_get_features(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) void nvmet_execute_keep_alive(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) void nvmet_cq_setup(struct nvmet_ctrl *ctrl, struct nvmet_cq *cq, u16 qid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u16 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) void nvmet_sq_setup(struct nvmet_ctrl *ctrl, struct nvmet_sq *sq, u16 qid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void nvmet_sq_destroy(struct nvmet_sq *sq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int nvmet_sq_init(struct nvmet_sq *sq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void nvmet_ctrl_fatal_error(struct nvmet_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void nvmet_update_cc(struct nvmet_ctrl *ctrl, u32 new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u16 nvmet_alloc_ctrl(const char *subsysnqn, const char *hostnqn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct nvmet_req *req, u32 kato, struct nvmet_ctrl **ctrlp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u16 nvmet_ctrl_find_get(const char *subsysnqn, const char *hostnqn, u16 cntlid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct nvmet_req *req, struct nvmet_ctrl **ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void nvmet_ctrl_put(struct nvmet_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u16 nvmet_check_ctrl_status(struct nvmet_req *req, struct nvme_command *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct nvmet_subsys *nvmet_subsys_alloc(const char *subsysnqn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) enum nvme_subsys_type type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void nvmet_subsys_put(struct nvmet_subsys *subsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) void nvmet_subsys_del_ctrls(struct nvmet_subsys *subsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct nvmet_ns *nvmet_find_namespace(struct nvmet_ctrl *ctrl, __le32 nsid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) void nvmet_put_namespace(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int nvmet_ns_enable(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) void nvmet_ns_disable(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct nvmet_ns *nvmet_ns_alloc(struct nvmet_subsys *subsys, u32 nsid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) void nvmet_ns_free(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) void nvmet_send_ana_event(struct nvmet_subsys *subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) void nvmet_port_send_ana_event(struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int nvmet_register_transport(const struct nvmet_fabrics_ops *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void nvmet_unregister_transport(const struct nvmet_fabrics_ops *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void nvmet_port_del_ctrls(struct nvmet_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct nvmet_subsys *subsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int nvmet_enable_port(struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) void nvmet_disable_port(struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void nvmet_referral_enable(struct nvmet_port *parent, struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void nvmet_referral_disable(struct nvmet_port *parent, struct nvmet_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u16 nvmet_copy_to_sgl(struct nvmet_req *req, off_t off, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u16 nvmet_copy_from_sgl(struct nvmet_req *req, off_t off, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u16 nvmet_zero_sgl(struct nvmet_req *req, off_t off, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 nvmet_get_log_page_len(struct nvme_command *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u64 nvmet_get_log_page_offset(struct nvme_command *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) extern struct list_head *nvmet_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) void nvmet_port_disc_changed(struct nvmet_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct nvmet_subsys *subsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void nvmet_subsys_disc_changed(struct nvmet_subsys *subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct nvmet_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) void nvmet_add_async_event(struct nvmet_ctrl *ctrl, u8 event_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 event_info, u8 log_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define NVMET_QUEUE_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define NVMET_NR_QUEUES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define NVMET_MAX_CMD NVMET_QUEUE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Nice round number that makes a list of nsids fit into a page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Should become tunable at some point in the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define NVMET_MAX_NAMESPACES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * 0 is not a valid ANA group ID, so we start numbering at 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * ANA Group 1 exists without manual intervention, has namespaces assigned to it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * by default, and is available in an optimized state through all ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define NVMET_MAX_ANAGRPS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define NVMET_DEFAULT_ANA_GRPID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define NVMET_KAS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define NVMET_DISC_KATO_MS 120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int __init nvmet_init_configfs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void __exit nvmet_exit_configfs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int __init nvmet_init_discovery(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) void nvmet_exit_discovery(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) extern struct nvmet_subsys *nvmet_disc_subsys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) extern struct rw_semaphore nvmet_config_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) extern u32 nvmet_ana_group_enabled[NVMET_MAX_ANAGRPS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) extern u64 nvmet_ana_chgcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) extern struct rw_semaphore nvmet_ana_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) bool nvmet_host_allowed(struct nvmet_subsys *subsys, const char *hostnqn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int nvmet_bdev_ns_enable(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int nvmet_file_ns_enable(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) void nvmet_bdev_ns_disable(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) void nvmet_file_ns_disable(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u16 nvmet_bdev_flush(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u16 nvmet_file_flush(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) void nvmet_ns_changed(struct nvmet_subsys *subsys, u32 nsid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) void nvmet_bdev_ns_revalidate(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int nvmet_file_ns_revalidate(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) void nvmet_ns_revalidate(struct nvmet_ns *ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static inline u32 nvmet_rw_data_len(struct nvmet_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ((u32)le16_to_cpu(req->cmd->rw.length) + 1) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) req->ns->blksize_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static inline u32 nvmet_rw_metadata_len(struct nvmet_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ((u32)le16_to_cpu(req->cmd->rw.length) + 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) req->ns->metadata_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static inline u32 nvmet_dsm_len(struct nvmet_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return (le32_to_cpu(req->cmd->dsm.nr) + 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) sizeof(struct nvme_dsm_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #ifdef CONFIG_NVME_TARGET_PASSTHRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) void nvmet_passthru_subsys_free(struct nvmet_subsys *subsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int nvmet_passthru_ctrl_enable(struct nvmet_subsys *subsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) void nvmet_passthru_ctrl_disable(struct nvmet_subsys *subsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u16 nvmet_parse_passthru_admin_cmd(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u16 nvmet_parse_passthru_io_cmd(struct nvmet_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static inline struct nvme_ctrl *nvmet_passthru_ctrl(struct nvmet_subsys *subsys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return subsys->passthru_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #else /* CONFIG_NVME_TARGET_PASSTHRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static inline void nvmet_passthru_subsys_free(struct nvmet_subsys *subsys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static inline void nvmet_passthru_ctrl_disable(struct nvmet_subsys *subsys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static inline u16 nvmet_parse_passthru_admin_cmd(struct nvmet_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static inline u16 nvmet_parse_passthru_io_cmd(struct nvmet_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static inline struct nvme_ctrl *nvmet_passthru_ctrl(struct nvmet_subsys *subsys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #endif /* CONFIG_NVME_TARGET_PASSTHRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static inline struct nvme_ctrl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) nvmet_req_passthru_ctrl(struct nvmet_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return nvmet_passthru_ctrl(req->sq->ctrl->subsys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u16 errno_to_nvme_status(struct nvmet_req *req, int errno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Convert a 32-bit number to a 16-bit 0's based number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static inline __le16 to0based(u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return cpu_to_le16(max(1U, min(1U << 16, a)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static inline bool nvmet_ns_has_pi(struct nvmet_ns *ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ns->pi_type && ns->metadata_size == sizeof(struct t10_pi_tuple);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static inline __le64 nvmet_sect_to_lba(struct nvmet_ns *ns, sector_t sect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return cpu_to_le64(sect >> (ns->blksize_shift - SECTOR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static inline sector_t nvmet_lba_to_sect(struct nvmet_ns *ns, __le64 lba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return le64_to_cpu(lba) << (ns->blksize_shift - SECTOR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static inline bool nvmet_use_inline_bvec(struct nvmet_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return req->transfer_len <= NVMET_MAX_INLINE_DATA_LEN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) req->sg_cnt <= NVMET_MAX_INLINE_BIOVEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #endif /* _NVMET_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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