Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * NVM Express hardware monitoring support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2019, Guenter Roeck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/units.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "nvme.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) struct nvme_hwmon_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	struct nvme_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	struct nvme_smart_log log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	struct mutex read_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int nvme_get_temp_thresh(struct nvme_ctrl *ctrl, int sensor, bool under,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 				long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	unsigned int threshold = sensor << NVME_TEMP_THRESH_SELECT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	if (under)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		threshold |= NVME_TEMP_THRESH_TYPE_UNDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	ret = nvme_get_features(ctrl, NVME_FEAT_TEMP_THRESH, threshold, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	*temp = kelvin_to_millicelsius(status & NVME_TEMP_THRESH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int nvme_set_temp_thresh(struct nvme_ctrl *ctrl, int sensor, bool under,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 				long temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	unsigned int threshold = sensor << NVME_TEMP_THRESH_SELECT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	temp = millicelsius_to_kelvin(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	threshold |= clamp_val(temp, 0, NVME_TEMP_THRESH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	if (under)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		threshold |= NVME_TEMP_THRESH_TYPE_UNDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	ret = nvme_set_features(ctrl, NVME_FEAT_TEMP_THRESH, threshold, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 				NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int nvme_hwmon_get_smart_log(struct nvme_hwmon_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return nvme_get_log(data->ctrl, NVME_NSID_ALL, NVME_LOG_SMART, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			   NVME_CSI_NVM, &data->log, sizeof(data->log), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int nvme_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			   u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct nvme_hwmon_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct nvme_smart_log *log = &data->log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * First handle attributes which don't require us to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * the smart log.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return nvme_get_temp_thresh(data->ctrl, channel, false, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return nvme_get_temp_thresh(data->ctrl, channel, true, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		*val = kelvin_to_millicelsius(data->ctrl->cctemp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mutex_lock(&data->read_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	err = nvme_hwmon_get_smart_log(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		if (!channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			temp = get_unaligned_le16(log->temperature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			temp = le16_to_cpu(log->temp_sensor[channel - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		*val = kelvin_to_millicelsius(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case hwmon_temp_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		*val = !!(log->critical_warning & NVME_SMART_CRIT_TEMPERATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	mutex_unlock(&data->read_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int nvme_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			    u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct nvme_hwmon_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return nvme_set_temp_thresh(data->ctrl, channel, false, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return nvme_set_temp_thresh(data->ctrl, channel, true, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const char * const nvme_hwmon_sensor_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	"Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	"Sensor 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	"Sensor 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	"Sensor 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	"Sensor 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	"Sensor 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	"Sensor 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	"Sensor 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	"Sensor 8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int nvme_hwmon_read_string(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				  enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				  int channel, const char **str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	*str = nvme_hwmon_sensor_names[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static umode_t nvme_hwmon_is_visible(const void *_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				     enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				     u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	const struct nvme_hwmon_data *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if (!channel && data->ctrl->cctemp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if ((!channel && data->ctrl->wctemp) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		    (channel && data->log.temp_sensor[channel - 1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			if (data->ctrl->quirks &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			    NVME_QUIRK_NO_TEMP_THRESH_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case hwmon_temp_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (!channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case hwmon_temp_label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if (!channel || data->log.temp_sensor[channel - 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct hwmon_channel_info *nvme_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				HWMON_T_CRIT | HWMON_T_LABEL | HWMON_T_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				HWMON_T_LABEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct hwmon_ops nvme_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.is_visible	= nvme_hwmon_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.read		= nvme_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.read_string	= nvme_hwmon_read_string,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.write		= nvme_hwmon_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct hwmon_chip_info nvme_hwmon_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.ops	= &nvme_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.info	= nvme_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int nvme_hwmon_init(struct nvme_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct device *dev = ctrl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct nvme_hwmon_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct device *hwmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	data->ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	mutex_init(&data->read_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	err = nvme_hwmon_get_smart_log(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_warn(ctrl->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			"Failed to read smart log (error %d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		devm_kfree(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	hwmon = devm_hwmon_device_register_with_info(dev, "nvme", data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 						     &nvme_hwmon_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 						     NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (IS_ERR(hwmon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		dev_warn(dev, "Failed to instantiate hwmon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		devm_kfree(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }