^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI TRF7970a RFID/NFC Transceiver Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Erick Macias <emacias@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Felipe Balbi <balbi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Mark A. Greer <mgreer@animalcreek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/nfc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <net/nfc/nfc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <net/nfc/digital.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* There are 3 ways the host can communicate with the trf7970a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * parallel mode, SPI with Slave Select (SS) mode, and SPI without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * SS mode. The driver only supports the two SPI modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * The trf7970a is very timing sensitive and the VIN, EN2, and EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * pins must asserted in that order and with specific delays in between.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * The delays used in the driver were provided by TI and have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * confirmed to work with this driver. There is a bug with the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * version of the trf7970a that requires that EN2 remain low no matter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * what. If it goes high, it will generate an RF field even when in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * passive target mode. TI has indicated that the chip will work okay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * when EN2 is left low. The 'en2-rf-quirk' device tree property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * indicates that trf7970a currently being used has the erratum and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * that EN2 must be kept low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Timeouts are implemented using the delayed workqueue kernel facility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Timeouts are required so things don't hang when there is no response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * from the trf7970a (or tag). Using this mechanism creates a race with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * interrupts, however. That is, an interrupt and a timeout could occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * closely enough together that one is blocked by the mutex while the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * executes. When the timeout handler executes first and blocks the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * interrupt handler, it will eventually set the state to IDLE so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * interrupt handler will check the state and exit with no harm done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * When the interrupt handler executes first and blocks the timeout handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * the cancel_delayed_work() call will know that it didn't cancel the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * work item (i.e., timeout) and will return zero. That return code is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * used by the timer handler to indicate that it should ignore the timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * once its unblocked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Aborting an active command isn't as simple as it seems because the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * way to abort a command that's already been sent to the tag is so turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * off power to the tag. If we do that, though, we'd have to go through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * the entire anticollision procedure again but the digital layer doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * support that. So, if an abort is received before trf7970a_send_cmd()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * has sent the command to the tag, it simply returns -ECANCELED. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * command has already been sent to the tag, then the driver continues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * normally and recieves the response data (or error) but just before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * sending the data upstream, it frees the rx_skb and sends -ECANCELED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * upstream instead. If the command failed, that error will be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * upstream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * When recieving data from a tag and the interrupt status register has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * only the SRX bit set, it means that all of the data has been received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * (once what's in the fifo has been read). However, depending on timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * an interrupt status with only the SRX bit set may not be recived. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * those cases, the timeout mechanism is used to wait 20 ms in case more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * data arrives. After 20 ms, it is assumed that all of the data has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * received and the accumulated rx data is sent upstream. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * 'TRF7970A_ST_WAIT_FOR_RX_DATA_CONT' state is used for this purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * (i.e., it indicates that some data has been received but we're not sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * if there is more coming so a timeout in this state means all data has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * been received and there isn't an error). The delay is 20 ms since delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * of ~16 ms have been observed during testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * When transmitting a frame larger than the FIFO size (127 bytes), the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * driver will wait 20 ms for the FIFO to drain past the low-watermark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * and generate an interrupt. The low-watermark set to 32 bytes so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * interrupt should fire after 127 - 32 = 95 bytes have been sent. At
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * the lowest possible bit rate (6.62 kbps for 15693), it will take up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * to ~14.35 ms so 20 ms is used for the timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Type 2 write and sector select commands respond with a 4-bit ACK or NACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Having only 4 bits in the FIFO won't normally generate an interrupt so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * driver enables the '4_bit_RX' bit of the Special Functions register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * to cause an interrupt in that case. Leaving that bit for a read command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * messes up the data returned so it is only enabled when the framing is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 'NFC_DIGITAL_FRAMING_NFCA_T2T' and the command is not a read command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Unfortunately, that means that the driver has to peek into tx frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * when the framing is 'NFC_DIGITAL_FRAMING_NFCA_T2T'. This is done by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * the trf7970a_per_cmd_config() routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * ISO/IEC 15693 frames specify whether to use single or double sub-carrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * frequencies and whether to use low or high data rates in the flags byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * of the frame. This means that the driver has to peek at all 15693 frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * to determine what speed to set the communication to. In addition, write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * and lock commands use the OPTION flag to indicate that an EOF must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * sent to the tag before it will send its response. So the driver has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * examine all frames for that reason too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * It is unclear how long to wait before sending the EOF. According to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Note under Table 1-1 in section 1.6 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * http://www.ti.com/lit/ug/scbu011/scbu011.pdf, that wait should be at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * 10 ms for TI Tag-it HF-I tags; however testing has shown that is not long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * enough so 20 ms is used. So the timer is set to 40 ms - 20 ms to drain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * up to 127 bytes in the FIFO at the lowest bit rate plus another 20 ms to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * ensure the wait is long enough before sending the EOF. This seems to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * reliably.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TRF7970A_SUPPORTED_PROTOCOLS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (NFC_PROTO_MIFARE_MASK | NFC_PROTO_ISO14443_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) NFC_PROTO_ISO14443_B_MASK | NFC_PROTO_FELICA_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) NFC_PROTO_ISO15693_MASK | NFC_PROTO_NFC_DEP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TRF7970A_AUTOSUSPEND_DELAY 30000 /* 30 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TRF7970A_13MHZ_CLOCK_FREQUENCY 13560000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TRF7970A_27MHZ_CLOCK_FREQUENCY 27120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TRF7970A_RX_SKB_ALLOC_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TRF7970A_FIFO_SIZE 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* TX length is 3 nibbles long ==> 4KB - 1 bytes max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TRF7970A_TX_MAX (4096 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TRF7970A_WAIT_FOR_TX_IRQ 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TRF7970A_WAIT_FOR_RX_DATA_TIMEOUT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TRF7970A_WAIT_FOR_FIFO_DRAIN_TIMEOUT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TRF7970A_WAIT_TO_ISSUE_ISO15693_EOF 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Guard times for various RF technologies (in us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TRF7970A_GUARD_TIME_NFCA 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TRF7970A_GUARD_TIME_NFCB 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TRF7970A_GUARD_TIME_NFCF 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TRF7970A_GUARD_TIME_15693 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Erratum: When reading IRQ Status register on trf7970a, we must issue a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * read continuous command for IRQ Status and Collision Position registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TRF7970A_QUIRK_IRQ_STATUS_READ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TRF7970A_QUIRK_EN2_MUST_STAY_LOW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Direct commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TRF7970A_CMD_IDLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TRF7970A_CMD_SOFT_INIT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TRF7970A_CMD_RF_COLLISION 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TRF7970A_CMD_RF_COLLISION_RESPONSE_N 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TRF7970A_CMD_RF_COLLISION_RESPONSE_0 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TRF7970A_CMD_FIFO_RESET 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TRF7970A_CMD_TRANSMIT_NO_CRC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TRF7970A_CMD_TRANSMIT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TRF7970A_CMD_DELAY_TRANSMIT_NO_CRC 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TRF7970A_CMD_DELAY_TRANSMIT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TRF7970A_CMD_EOF 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TRF7970A_CMD_CLOSE_SLOT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TRF7970A_CMD_BLOCK_RX 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TRF7970A_CMD_ENABLE_RX 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TRF7970A_CMD_TEST_INT_RF 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TRF7970A_CMD_TEST_EXT_RF 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TRF7970A_CMD_RX_GAIN_ADJUST 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Bits determining whether its a direct command or register R/W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * whether to use a continuous SPI transaction or not, and the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * direct cmd opcode or regster address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TRF7970A_CMD_BIT_CTRL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TRF7970A_CMD_BIT_RW BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TRF7970A_CMD_BIT_CONTINUOUS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TRF7970A_CMD_BIT_OPCODE(opcode) ((opcode) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Registers addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TRF7970A_CHIP_STATUS_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TRF7970A_ISO_CTRL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TRF7970A_ISO14443B_TX_OPTIONS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TRF7970A_ISO14443A_HIGH_BITRATE_OPTIONS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TRF7970A_TX_TIMER_SETTING_H_BYTE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TRF7970A_TX_TIMER_SETTING_L_BYTE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TRF7970A_TX_PULSE_LENGTH_CTRL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TRF7970A_RX_NO_RESPONSE_WAIT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TRF7970A_RX_WAIT_TIME 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TRF7970A_MODULATOR_SYS_CLK_CTRL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TRF7970A_RX_SPECIAL_SETTINGS 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TRF7970A_REG_IO_CTRL 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TRF7970A_IRQ_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TRF7970A_COLLISION_IRQ_MASK 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TRF7970A_COLLISION_POSITION 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TRF7970A_RSSI_OSC_STATUS 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TRF7970A_SPECIAL_FCN_REG1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TRF7970A_SPECIAL_FCN_REG2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TRF7970A_RAM1 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TRF7970A_RAM2 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TRF7970A_NFC_LOW_FIELD_LEVEL 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TRF7970A_NFCID1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TRF7970A_NFC_TARGET_LEVEL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TRF79070A_NFC_TARGET_PROTOCOL 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TRF7970A_TEST_REGISTER1 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TRF7970A_TEST_REGISTER2 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TRF7970A_FIFO_STATUS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TRF7970A_TX_LENGTH_BYTE1 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TRF7970A_TX_LENGTH_BYTE2 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TRF7970A_FIFO_IO_REGISTER 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Chip Status Control Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TRF7970A_CHIP_STATUS_VRS5_3 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TRF7970A_CHIP_STATUS_REC_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TRF7970A_CHIP_STATUS_AGC_ON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TRF7970A_CHIP_STATUS_PM_ON BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TRF7970A_CHIP_STATUS_RF_PWR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TRF7970A_CHIP_STATUS_RF_ON BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TRF7970A_CHIP_STATUS_DIRECT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TRF7970A_CHIP_STATUS_STBY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* ISO Control Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TRF7970A_ISO_CTRL_15693_SGL_1OF4_662 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TRF7970A_ISO_CTRL_15693_SGL_1OF256_662 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TRF7970A_ISO_CTRL_15693_SGL_1OF4_2648 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TRF7970A_ISO_CTRL_15693_SGL_1OF256_2648 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TRF7970A_ISO_CTRL_15693_DBL_1OF4_667a 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TRF7970A_ISO_CTRL_15693_DBL_1OF256_667 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TRF7970A_ISO_CTRL_15693_DBL_1OF4_2669 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TRF7970A_ISO_CTRL_15693_DBL_1OF256_2669 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TRF7970A_ISO_CTRL_14443A_106 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TRF7970A_ISO_CTRL_14443A_212 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TRF7970A_ISO_CTRL_14443A_424 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TRF7970A_ISO_CTRL_14443A_848 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TRF7970A_ISO_CTRL_14443B_106 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TRF7970A_ISO_CTRL_14443B_212 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TRF7970A_ISO_CTRL_14443B_424 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TRF7970A_ISO_CTRL_14443B_848 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TRF7970A_ISO_CTRL_FELICA_212 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TRF7970A_ISO_CTRL_FELICA_424 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TRF7970A_ISO_CTRL_NFC_NFCA_106 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TRF7970A_ISO_CTRL_NFC_NFCF_212 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TRF7970A_ISO_CTRL_NFC_NFCF_424 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TRF7970A_ISO_CTRL_NFC_CE_14443A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TRF7970A_ISO_CTRL_NFC_CE_14443B 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TRF7970A_ISO_CTRL_NFC_CE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TRF7970A_ISO_CTRL_NFC_ACTIVE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TRF7970A_ISO_CTRL_NFC_INITIATOR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TRF7970A_ISO_CTRL_NFC_NFC_CE_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TRF7970A_ISO_CTRL_RFID BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TRF7970A_ISO_CTRL_DIR_MODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TRF7970A_ISO_CTRL_RX_CRC_N BIT(7) /* true == No CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TRF7970A_ISO_CTRL_RFID_SPEED_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Modulator and SYS_CLK Control Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TRF7970A_MODULATOR_DEPTH(n) ((n) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TRF7970A_MODULATOR_DEPTH_ASK10 (TRF7970A_MODULATOR_DEPTH(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TRF7970A_MODULATOR_DEPTH_OOK (TRF7970A_MODULATOR_DEPTH(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TRF7970A_MODULATOR_DEPTH_ASK7 (TRF7970A_MODULATOR_DEPTH(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TRF7970A_MODULATOR_DEPTH_ASK8_5 (TRF7970A_MODULATOR_DEPTH(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TRF7970A_MODULATOR_DEPTH_ASK13 (TRF7970A_MODULATOR_DEPTH(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TRF7970A_MODULATOR_DEPTH_ASK16 (TRF7970A_MODULATOR_DEPTH(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TRF7970A_MODULATOR_DEPTH_ASK22 (TRF7970A_MODULATOR_DEPTH(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TRF7970A_MODULATOR_DEPTH_ASK30 (TRF7970A_MODULATOR_DEPTH(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TRF7970A_MODULATOR_EN_ANA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TRF7970A_MODULATOR_CLK(n) (((n) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TRF7970A_MODULATOR_CLK_DISABLED (TRF7970A_MODULATOR_CLK(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TRF7970A_MODULATOR_CLK_3_6 (TRF7970A_MODULATOR_CLK(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TRF7970A_MODULATOR_CLK_6_13 (TRF7970A_MODULATOR_CLK(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TRF7970A_MODULATOR_CLK_13_27 (TRF7970A_MODULATOR_CLK(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TRF7970A_MODULATOR_EN_OOK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TRF7970A_MODULATOR_27MHZ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TRF7970A_RX_SPECIAL_SETTINGS_NO_LIM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TRF7970A_RX_SPECIAL_SETTINGS_AGCR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TRF7970A_RX_SPECIAL_SETTINGS_GD_0DB (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TRF7970A_RX_SPECIAL_SETTINGS_GD_5DB (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TRF7970A_RX_SPECIAL_SETTINGS_GD_10DB (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TRF7970A_RX_SPECIAL_SETTINGS_GD_15DB (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TRF7970A_RX_SPECIAL_SETTINGS_HBT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TRF7970A_RX_SPECIAL_SETTINGS_M848 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TRF7970A_RX_SPECIAL_SETTINGS_C424 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TRF7970A_RX_SPECIAL_SETTINGS_C212 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TRF7970A_REG_IO_CTRL_VRS(v) ((v) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TRF7970A_REG_IO_CTRL_IO_LOW BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TRF7970A_REG_IO_CTRL_EN_EXT_PA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TRF7970A_REG_IO_CTRL_AUTO_REG BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* IRQ Status Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TRF7970A_IRQ_STATUS_NORESP BIT(0) /* ISO15693 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TRF7970A_IRQ_STATUS_NFC_COL_ERROR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TRF7970A_IRQ_STATUS_COL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TRF7970A_IRQ_STATUS_FRAMING_EOF_ERROR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TRF7970A_IRQ_STATUS_NFC_RF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TRF7970A_IRQ_STATUS_PARITY_ERROR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TRF7970A_IRQ_STATUS_NFC_SDD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TRF7970A_IRQ_STATUS_CRC_ERROR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TRF7970A_IRQ_STATUS_NFC_PROTO_ERROR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TRF7970A_IRQ_STATUS_FIFO BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TRF7970A_IRQ_STATUS_SRX BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TRF7970A_IRQ_STATUS_TX BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TRF7970A_IRQ_STATUS_ERROR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (TRF7970A_IRQ_STATUS_COL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) TRF7970A_IRQ_STATUS_FRAMING_EOF_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) TRF7970A_IRQ_STATUS_PARITY_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) TRF7970A_IRQ_STATUS_CRC_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TRF7970A_RSSI_OSC_STATUS_RSSI_MASK (BIT(2) | BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TRF7970A_RSSI_OSC_STATUS_RSSI_X_MASK (BIT(5) | BIT(4) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TRF7970A_RSSI_OSC_STATUS_RSSI_OSC_OK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TRF7970A_SPECIAL_FCN_REG1_COL_7_6 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TRF7970A_SPECIAL_FCN_REG1_14_ANTICOLL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TRF7970A_SPECIAL_FCN_REG1_4_BIT_RX BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TRF7970A_SPECIAL_FCN_REG1_SP_DIR_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TRF7970A_SPECIAL_FCN_REG1_NEXT_SLOT_37US BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TRF7970A_SPECIAL_FCN_REG1_PAR43 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_124 (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_120 (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_112 (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_96 (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_4 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_8 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_16 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_32 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TRF7970A_NFC_LOW_FIELD_LEVEL_RFDET(v) ((v) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TRF7970A_NFC_LOW_FIELD_LEVEL_CLEX_DIS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TRF7970A_NFC_TARGET_LEVEL_RFDET(v) ((v) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TRF7970A_NFC_TARGET_LEVEL_HI_RF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TRF7970A_NFC_TARGET_LEVEL_SDD_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define TRF7970A_NFC_TARGET_LEVEL_LD_S_4BYTES (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TRF7970A_NFC_TARGET_LEVEL_LD_S_7BYTES (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TRF7970A_NFC_TARGET_LEVEL_LD_S_10BYTES (0x2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_106 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_212 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_424 (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TRF79070A_NFC_TARGET_PROTOCOL_PAS_14443B BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define TRF79070A_NFC_TARGET_PROTOCOL_PAS_106 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TRF79070A_NFC_TARGET_PROTOCOL_FELICA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TRF79070A_NFC_TARGET_PROTOCOL_RF_L BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TRF79070A_NFC_TARGET_PROTOCOL_RF_H BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TRF79070A_NFC_TARGET_PROTOCOL_106A \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (TRF79070A_NFC_TARGET_PROTOCOL_RF_H | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) TRF79070A_NFC_TARGET_PROTOCOL_RF_L | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) TRF79070A_NFC_TARGET_PROTOCOL_PAS_106 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TRF79070A_NFC_TARGET_PROTOCOL_106B \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (TRF79070A_NFC_TARGET_PROTOCOL_RF_H | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) TRF79070A_NFC_TARGET_PROTOCOL_RF_L | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) TRF79070A_NFC_TARGET_PROTOCOL_PAS_14443B | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TRF79070A_NFC_TARGET_PROTOCOL_212F \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (TRF79070A_NFC_TARGET_PROTOCOL_RF_H | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) TRF79070A_NFC_TARGET_PROTOCOL_RF_L | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) TRF79070A_NFC_TARGET_PROTOCOL_FELICA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TRF79070A_NFC_TARGET_PROTOCOL_424F \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (TRF79070A_NFC_TARGET_PROTOCOL_RF_H | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) TRF79070A_NFC_TARGET_PROTOCOL_RF_L | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) TRF79070A_NFC_TARGET_PROTOCOL_FELICA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define TRF7970A_FIFO_STATUS_OVERFLOW BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* NFC (ISO/IEC 14443A) Type 2 Tag commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define NFC_T2T_CMD_READ 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* ISO 15693 commands codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ISO15693_CMD_INVENTORY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define ISO15693_CMD_READ_SINGLE_BLOCK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define ISO15693_CMD_WRITE_SINGLE_BLOCK 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define ISO15693_CMD_LOCK_BLOCK 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define ISO15693_CMD_READ_MULTIPLE_BLOCK 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define ISO15693_CMD_WRITE_MULTIPLE_BLOCK 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define ISO15693_CMD_SELECT 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define ISO15693_CMD_RESET_TO_READY 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define ISO15693_CMD_WRITE_AFI 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ISO15693_CMD_LOCK_AFI 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define ISO15693_CMD_WRITE_DSFID 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define ISO15693_CMD_LOCK_DSFID 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define ISO15693_CMD_GET_SYSTEM_INFO 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define ISO15693_CMD_GET_MULTIPLE_BLOCK_SECURITY_STATUS 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* ISO 15693 request and response flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define ISO15693_REQ_FLAG_SUB_CARRIER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define ISO15693_REQ_FLAG_DATA_RATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define ISO15693_REQ_FLAG_INVENTORY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define ISO15693_REQ_FLAG_PROTOCOL_EXT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define ISO15693_REQ_FLAG_SELECT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define ISO15693_REQ_FLAG_AFI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define ISO15693_REQ_FLAG_ADDRESS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define ISO15693_REQ_FLAG_NB_SLOTS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define ISO15693_REQ_FLAG_OPTION BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define ISO15693_REQ_FLAG_SPEED_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (ISO15693_REQ_FLAG_SUB_CARRIER | ISO15693_REQ_FLAG_DATA_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) enum trf7970a_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) TRF7970A_ST_PWR_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) TRF7970A_ST_RF_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) TRF7970A_ST_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) TRF7970A_ST_IDLE_RX_BLOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) TRF7970A_ST_WAIT_FOR_TX_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) TRF7970A_ST_WAIT_FOR_RX_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) TRF7970A_ST_WAIT_FOR_RX_DATA_CONT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) TRF7970A_ST_WAIT_TO_ISSUE_EOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) TRF7970A_ST_LISTENING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) TRF7970A_ST_LISTENING_MD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) TRF7970A_ST_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct trf7970a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) enum trf7970a_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct nfc_digital_dev *ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) bool is_initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) bool aborting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct sk_buff *rx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) nfc_digital_cmd_complete_t cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void *cb_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u8 chip_status_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 iso_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u8 iso_ctrl_tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u8 modulator_sys_clk_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 special_fcn_reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int guard_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int technology;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int framing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 md_rf_tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 tx_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) bool issue_eof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct gpio_desc *en_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct gpio_desc *en2_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) bool ignore_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct delayed_work timeout_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int trf7970a_cmd(struct trf7970a *trf, u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 cmd = TRF7970A_CMD_BIT_CTRL | TRF7970A_CMD_BIT_OPCODE(opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_dbg(trf->dev, "cmd: 0x%x\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = spi_write(trf->spi, &cmd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(trf->dev, "%s - cmd: 0x%x, ret: %d\n", __func__, cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int trf7970a_read(struct trf7970a *trf, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u8 addr = TRF7970A_CMD_BIT_RW | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = spi_write_then_read(trf->spi, &addr, 1, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(trf->dev, "%s - addr: 0x%x, ret: %d\n", __func__, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(trf->dev, "read(0x%x): 0x%x\n", addr, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int trf7970a_read_cont(struct trf7970a *trf, u8 reg, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 addr = reg | TRF7970A_CMD_BIT_RW | TRF7970A_CMD_BIT_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct spi_transfer t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_dbg(trf->dev, "read_cont(0x%x, %zd)\n", addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) memset(&t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) t[0].tx_buf = &addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) t[0].len = sizeof(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) t[1].rx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) t[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = spi_sync(trf->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(trf->dev, "%s - addr: 0x%x, ret: %d\n", __func__, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int trf7970a_write(struct trf7970a *trf, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 buf[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_dbg(trf->dev, "write(0x%x): 0x%x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = spi_write(trf->spi, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(trf->dev, "%s - write: 0x%x 0x%x, ret: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) buf[0], buf[1], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int trf7970a_read_irqstatus(struct trf7970a *trf, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) addr = TRF7970A_IRQ_STATUS | TRF7970A_CMD_BIT_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (trf->quirks & TRF7970A_QUIRK_IRQ_STATUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) addr |= TRF7970A_CMD_BIT_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = spi_write_then_read(trf->spi, &addr, 1, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = spi_write_then_read(trf->spi, &addr, 1, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(trf->dev, "%s - irqstatus: Status read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *status = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int trf7970a_read_target_proto(struct trf7970a *trf, u8 *target_proto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) addr = TRF79070A_NFC_TARGET_PROTOCOL | TRF7970A_CMD_BIT_RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) TRF7970A_CMD_BIT_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = spi_write_then_read(trf->spi, &addr, 1, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_err(trf->dev, "%s - target_proto: Read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) *target_proto = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int trf7970a_mode_detect(struct trf7970a *trf, u8 *rf_tech)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u8 target_proto, tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = trf7970a_read_target_proto(trf, &target_proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) switch (target_proto) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case TRF79070A_NFC_TARGET_PROTOCOL_106A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tech = NFC_DIGITAL_RF_TECH_106A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case TRF79070A_NFC_TARGET_PROTOCOL_106B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) tech = NFC_DIGITAL_RF_TECH_106B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case TRF79070A_NFC_TARGET_PROTOCOL_212F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) tech = NFC_DIGITAL_RF_TECH_212F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case TRF79070A_NFC_TARGET_PROTOCOL_424F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) tech = NFC_DIGITAL_RF_TECH_424F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_dbg(trf->dev, "%s - mode_detect: target_proto: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) __func__, target_proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) *rf_tech = tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void trf7970a_send_upstream(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_kfree_skb_any(trf->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) trf->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (trf->rx_skb && !IS_ERR(trf->rx_skb) && !trf->aborting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) print_hex_dump_debug("trf7970a rx data: ", DUMP_PREFIX_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 16, 1, trf->rx_skb->data, trf->rx_skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) trf->state = TRF7970A_ST_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (trf->aborting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_dbg(trf->dev, "Abort process complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!IS_ERR(trf->rx_skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) kfree_skb(trf->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) trf->rx_skb = ERR_PTR(-ECANCELED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) trf->aborting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) trf->cb(trf->ddev, trf->cb_arg, trf->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) trf->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void trf7970a_send_err_upstream(struct trf7970a *trf, int errno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_dbg(trf->dev, "Error - state: %d, errno: %d\n", trf->state, errno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) cancel_delayed_work(&trf->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) kfree_skb(trf->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) trf->rx_skb = ERR_PTR(errno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) trf7970a_send_upstream(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int trf7970a_transmit(struct trf7970a *trf, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned int len, u8 *prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned int prefix_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct spi_transfer t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) print_hex_dump_debug("trf7970a tx data: ", DUMP_PREFIX_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 16, 1, skb->data, len, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) memset(&t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) t[0].tx_buf = prefix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) t[0].len = prefix_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) t[1].tx_buf = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) t[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = spi_sync(trf->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(trf->dev, "%s - Can't send tx data: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) skb_pull(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (skb->len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) trf->state = TRF7970A_ST_WAIT_FOR_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) timeout = TRF7970A_WAIT_FOR_FIFO_DRAIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (trf->issue_eof) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) trf->state = TRF7970A_ST_WAIT_TO_ISSUE_EOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) timeout = TRF7970A_WAIT_TO_ISSUE_ISO15693_EOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) trf->state = TRF7970A_ST_WAIT_FOR_RX_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (!trf->timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) timeout = TRF7970A_WAIT_FOR_TX_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) timeout = trf->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_dbg(trf->dev, "Setting timeout for %d ms, state: %d\n", timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) schedule_delayed_work(&trf->timeout_work, msecs_to_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static void trf7970a_fill_fifo(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct sk_buff *skb = trf->tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u8 fifo_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u8 prefix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = trf7970a_read(trf, TRF7970A_FIFO_STATUS, &fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev_dbg(trf->dev, "Filling FIFO - fifo_bytes: 0x%x\n", fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) fifo_bytes &= ~TRF7970A_FIFO_STATUS_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Calculate how much more data can be written to the fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) len = TRF7970A_FIFO_SIZE - fifo_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) schedule_delayed_work(&trf->timeout_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) msecs_to_jiffies(TRF7970A_WAIT_FOR_FIFO_DRAIN_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) len = min(skb->len, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) prefix = TRF7970A_CMD_BIT_CONTINUOUS | TRF7970A_FIFO_IO_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = trf7970a_transmit(trf, skb, len, &prefix, sizeof(prefix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static void trf7970a_drain_fifo(struct trf7970a *trf, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct sk_buff *skb = trf->rx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u8 fifo_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (status & TRF7970A_IRQ_STATUS_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) trf7970a_send_err_upstream(trf, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = trf7970a_read(trf, TRF7970A_FIFO_STATUS, &fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_dbg(trf->dev, "Draining FIFO - fifo_bytes: 0x%x\n", fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) fifo_bytes &= ~TRF7970A_FIFO_STATUS_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!fifo_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) goto no_rx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (fifo_bytes > skb_tailroom(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) skb = skb_copy_expand(skb, skb_headroom(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) max_t(int, fifo_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) TRF7970A_RX_SKB_ALLOC_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) trf7970a_send_err_upstream(trf, -ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) kfree_skb(trf->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) trf->rx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = trf7970a_read_cont(trf, TRF7970A_FIFO_IO_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) skb_put(skb, fifo_bytes), fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* If received Type 2 ACK/NACK, shift right 4 bits and pass up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if ((trf->framing == NFC_DIGITAL_FRAMING_NFCA_T2T) && (skb->len == 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) (trf->special_fcn_reg1 == TRF7970A_SPECIAL_FCN_REG1_4_BIT_RX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) skb->data[0] >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) status = TRF7970A_IRQ_STATUS_SRX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) trf->state = TRF7970A_ST_WAIT_FOR_RX_DATA_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = trf7970a_read(trf, TRF7970A_FIFO_STATUS, &fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fifo_bytes &= ~TRF7970A_FIFO_STATUS_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* If there are bytes in the FIFO, set status to '0' so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * the if stmt below doesn't fire and the driver will wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * for the trf7970a to generate another RX interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (fifo_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) no_rx_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (status == TRF7970A_IRQ_STATUS_SRX) { /* Receive complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) trf7970a_send_upstream(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_dbg(trf->dev, "Setting timeout for %d ms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) TRF7970A_WAIT_FOR_RX_DATA_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) schedule_delayed_work(&trf->timeout_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) msecs_to_jiffies(TRF7970A_WAIT_FOR_RX_DATA_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static irqreturn_t trf7970a_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct trf7970a *trf = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u8 status, fifo_bytes, iso_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (trf->state == TRF7970A_ST_RF_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = trf7970a_read_irqstatus(trf, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_dbg(trf->dev, "IRQ - state: %d, status: 0x%x\n", trf->state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) switch (trf->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case TRF7970A_ST_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case TRF7970A_ST_IDLE_RX_BLOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* If initiator and getting interrupts caused by RF noise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * turn off the receiver to avoid unnecessary interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * It will be turned back on in trf7970a_send_cmd() when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * the next command is issued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (trf->is_initiator && (status & TRF7970A_IRQ_STATUS_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) trf7970a_cmd(trf, TRF7970A_CMD_BLOCK_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) trf->state = TRF7970A_ST_IDLE_RX_BLOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) trf7970a_cmd(trf, TRF7970A_CMD_FIFO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case TRF7970A_ST_WAIT_FOR_TX_FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (status & TRF7970A_IRQ_STATUS_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) trf->ignore_timeout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) !cancel_delayed_work(&trf->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) trf7970a_fill_fifo(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) trf7970a_send_err_upstream(trf, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case TRF7970A_ST_WAIT_FOR_RX_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case TRF7970A_ST_WAIT_FOR_RX_DATA_CONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (status & TRF7970A_IRQ_STATUS_SRX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) trf->ignore_timeout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) !cancel_delayed_work(&trf->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) trf7970a_drain_fifo(trf, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } else if (status & TRF7970A_IRQ_STATUS_FIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = trf7970a_read(trf, TRF7970A_FIFO_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) &fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) fifo_bytes &= ~TRF7970A_FIFO_STATUS_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) else if (!fifo_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) trf7970a_cmd(trf, TRF7970A_CMD_FIFO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) } else if ((status == TRF7970A_IRQ_STATUS_TX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) (!trf->is_initiator &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) (status == (TRF7970A_IRQ_STATUS_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) TRF7970A_IRQ_STATUS_NFC_RF)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) trf7970a_cmd(trf, TRF7970A_CMD_FIFO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (!trf->timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) trf->ignore_timeout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) !cancel_delayed_work(&trf->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) trf->rx_skb = ERR_PTR(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) trf7970a_send_upstream(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (trf->is_initiator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) iso_ctrl = trf->iso_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) switch (trf->framing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case NFC_DIGITAL_FRAMING_NFCA_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) trf->tx_cmd = TRF7970A_CMD_TRANSMIT_NO_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) iso_ctrl |= TRF7970A_ISO_CTRL_RX_CRC_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) trf->iso_ctrl = 0xff; /* Force ISO_CTRL write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) case NFC_DIGITAL_FRAMING_NFCA_STANDARD_WITH_CRC_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) trf->tx_cmd = TRF7970A_CMD_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) iso_ctrl &= ~TRF7970A_ISO_CTRL_RX_CRC_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) trf->iso_ctrl = 0xff; /* Force ISO_CTRL write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case NFC_DIGITAL_FRAMING_NFCA_ANTICOL_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ret = trf7970a_write(trf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) TRF7970A_SPECIAL_FCN_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) TRF7970A_SPECIAL_FCN_REG1_14_ANTICOLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) goto err_unlock_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) trf->special_fcn_reg1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) TRF7970A_SPECIAL_FCN_REG1_14_ANTICOLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (iso_ctrl != trf->iso_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = trf7970a_write(trf, TRF7970A_ISO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) iso_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto err_unlock_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) trf->iso_ctrl = iso_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) trf7970a_send_err_upstream(trf, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) case TRF7970A_ST_WAIT_TO_ISSUE_EOF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (status != TRF7970A_IRQ_STATUS_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) trf7970a_send_err_upstream(trf, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) case TRF7970A_ST_LISTENING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (status & TRF7970A_IRQ_STATUS_SRX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) trf->ignore_timeout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) !cancel_delayed_work(&trf->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) trf7970a_drain_fifo(trf, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) } else if (!(status & TRF7970A_IRQ_STATUS_NFC_RF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) trf7970a_send_err_upstream(trf, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case TRF7970A_ST_LISTENING_MD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (status & TRF7970A_IRQ_STATUS_SRX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) trf->ignore_timeout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) !cancel_delayed_work(&trf->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ret = trf7970a_mode_detect(trf, &trf->md_rf_tech);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) trf->state = TRF7970A_ST_LISTENING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) trf7970a_drain_fifo(trf, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } else if (!(status & TRF7970A_IRQ_STATUS_NFC_RF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) trf7970a_send_err_upstream(trf, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_err(trf->dev, "%s - Driver in invalid state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __func__, trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) err_unlock_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static void trf7970a_issue_eof(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_dbg(trf->dev, "Issuing EOF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = trf7970a_cmd(trf, TRF7970A_CMD_FIFO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = trf7970a_cmd(trf, TRF7970A_CMD_EOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) trf7970a_send_err_upstream(trf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) trf->state = TRF7970A_ST_WAIT_FOR_RX_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_dbg(trf->dev, "Setting timeout for %d ms, state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) trf->timeout, trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) schedule_delayed_work(&trf->timeout_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) msecs_to_jiffies(trf->timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static void trf7970a_timeout_work_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct trf7970a *trf = container_of(work, struct trf7970a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) timeout_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_dbg(trf->dev, "Timeout - state: %d, ignore_timeout: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) trf->state, trf->ignore_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (trf->ignore_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) trf->ignore_timeout = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) else if (trf->state == TRF7970A_ST_WAIT_FOR_RX_DATA_CONT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) trf7970a_drain_fifo(trf, TRF7970A_IRQ_STATUS_SRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) else if (trf->state == TRF7970A_ST_WAIT_TO_ISSUE_EOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) trf7970a_issue_eof(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) trf7970a_send_err_upstream(trf, -ETIMEDOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int trf7970a_init(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dev_dbg(trf->dev, "Initializing device - state: %d\n", trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret = trf7970a_cmd(trf, TRF7970A_CMD_SOFT_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = trf7970a_cmd(trf, TRF7970A_CMD_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ret = trf7970a_write(trf, TRF7970A_REG_IO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) trf->io_ctrl | TRF7970A_REG_IO_CTRL_VRS(0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ret = trf7970a_write(trf, TRF7970A_NFC_TARGET_LEVEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) trf->chip_status_ctrl &= ~TRF7970A_CHIP_STATUS_RF_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = trf7970a_write(trf, TRF7970A_MODULATOR_SYS_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) trf->modulator_sys_clk_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = trf7970a_write(trf, TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_96 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ret = trf7970a_write(trf, TRF7970A_SPECIAL_FCN_REG1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) trf->special_fcn_reg1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) trf->iso_ctrl = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_dbg(trf->dev, "Couldn't init device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static void trf7970a_switch_rf_off(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if ((trf->state == TRF7970A_ST_PWR_OFF) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) (trf->state == TRF7970A_ST_RF_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dev_dbg(trf->dev, "Switching rf off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) trf->chip_status_ctrl &= ~TRF7970A_CHIP_STATUS_RF_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) trf7970a_write(trf, TRF7970A_CHIP_STATUS_CTRL, trf->chip_status_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) trf->aborting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) trf->state = TRF7970A_ST_RF_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) pm_runtime_mark_last_busy(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) pm_runtime_put_autosuspend(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int trf7970a_switch_rf_on(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dev_dbg(trf->dev, "Switching rf on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) pm_runtime_get_sync(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (trf->state != TRF7970A_ST_RF_OFF) { /* Power on, RF off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev_err(trf->dev, "%s - Incorrect state: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ret = trf7970a_init(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dev_err(trf->dev, "%s - Can't initialize: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) trf->state = TRF7970A_ST_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static int trf7970a_switch_rf(struct nfc_digital_dev *ddev, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dev_dbg(trf->dev, "Switching RF - state: %d, on: %d\n", trf->state, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) switch (trf->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) case TRF7970A_ST_PWR_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) case TRF7970A_ST_RF_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = trf7970a_switch_rf_on(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case TRF7970A_ST_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) case TRF7970A_ST_IDLE_RX_BLOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dev_err(trf->dev, "%s - Invalid request: %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) __func__, trf->state, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) trf7970a_switch_rf_off(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) switch (trf->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) case TRF7970A_ST_PWR_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) case TRF7970A_ST_RF_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_err(trf->dev, "%s - Invalid request: %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) __func__, trf->state, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) case TRF7970A_ST_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) case TRF7970A_ST_IDLE_RX_BLOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) case TRF7970A_ST_WAIT_FOR_RX_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case TRF7970A_ST_WAIT_FOR_RX_DATA_CONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) trf7970a_switch_rf_off(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static int trf7970a_in_config_rf_tech(struct trf7970a *trf, int tech)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) dev_dbg(trf->dev, "rf technology: %d\n", tech);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) switch (tech) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) case NFC_DIGITAL_RF_TECH_106A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) trf->iso_ctrl_tech = TRF7970A_ISO_CTRL_14443A_106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) trf->modulator_sys_clk_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) (trf->modulator_sys_clk_ctrl & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) TRF7970A_MODULATOR_DEPTH_OOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) trf->guard_time = TRF7970A_GUARD_TIME_NFCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) case NFC_DIGITAL_RF_TECH_106B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) trf->iso_ctrl_tech = TRF7970A_ISO_CTRL_14443B_106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) trf->modulator_sys_clk_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) (trf->modulator_sys_clk_ctrl & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) TRF7970A_MODULATOR_DEPTH_ASK10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) trf->guard_time = TRF7970A_GUARD_TIME_NFCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case NFC_DIGITAL_RF_TECH_212F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) trf->iso_ctrl_tech = TRF7970A_ISO_CTRL_FELICA_212;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) trf->modulator_sys_clk_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) (trf->modulator_sys_clk_ctrl & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) TRF7970A_MODULATOR_DEPTH_ASK10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) trf->guard_time = TRF7970A_GUARD_TIME_NFCF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case NFC_DIGITAL_RF_TECH_424F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) trf->iso_ctrl_tech = TRF7970A_ISO_CTRL_FELICA_424;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) trf->modulator_sys_clk_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) (trf->modulator_sys_clk_ctrl & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) TRF7970A_MODULATOR_DEPTH_ASK10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) trf->guard_time = TRF7970A_GUARD_TIME_NFCF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) case NFC_DIGITAL_RF_TECH_ISO15693:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) trf->iso_ctrl_tech = TRF7970A_ISO_CTRL_15693_SGL_1OF4_2648;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) trf->modulator_sys_clk_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) (trf->modulator_sys_clk_ctrl & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) TRF7970A_MODULATOR_DEPTH_OOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) trf->guard_time = TRF7970A_GUARD_TIME_15693;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_dbg(trf->dev, "Unsupported rf technology: %d\n", tech);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) trf->technology = tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* If in initiator mode and not changing the RF tech due to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * PSL sequence (indicated by 'trf->iso_ctrl == 0xff' from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * trf7970a_init()), clear the NFC Target Detection Level register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * due to erratum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (trf->iso_ctrl == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = trf7970a_write(trf, TRF7970A_NFC_TARGET_LEVEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int trf7970a_is_rf_field(struct trf7970a *trf, bool *is_rf_field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u8 rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = trf7970a_write(trf, TRF7970A_CHIP_STATUS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) trf->chip_status_ctrl |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) TRF7970A_CHIP_STATUS_REC_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ret = trf7970a_cmd(trf, TRF7970A_CMD_TEST_EXT_RF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) usleep_range(50, 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = trf7970a_read(trf, TRF7970A_RSSI_OSC_STATUS, &rssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ret = trf7970a_write(trf, TRF7970A_CHIP_STATUS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) trf->chip_status_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (rssi & TRF7970A_RSSI_OSC_STATUS_RSSI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) *is_rf_field = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) *is_rf_field = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static int trf7970a_in_config_framing(struct trf7970a *trf, int framing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u8 iso_ctrl = trf->iso_ctrl_tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) bool is_rf_field = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_dbg(trf->dev, "framing: %d\n", framing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) switch (framing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) case NFC_DIGITAL_FRAMING_NFCA_SHORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) case NFC_DIGITAL_FRAMING_NFCA_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) trf->tx_cmd = TRF7970A_CMD_TRANSMIT_NO_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) iso_ctrl |= TRF7970A_ISO_CTRL_RX_CRC_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) case NFC_DIGITAL_FRAMING_NFCA_STANDARD_WITH_CRC_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) case NFC_DIGITAL_FRAMING_NFCA_T4T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case NFC_DIGITAL_FRAMING_NFCB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case NFC_DIGITAL_FRAMING_NFCB_T4T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) case NFC_DIGITAL_FRAMING_NFCF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) case NFC_DIGITAL_FRAMING_NFCF_T3T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) case NFC_DIGITAL_FRAMING_ISO15693_INVENTORY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) case NFC_DIGITAL_FRAMING_ISO15693_T5T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case NFC_DIGITAL_FRAMING_NFCA_NFC_DEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case NFC_DIGITAL_FRAMING_NFCF_NFC_DEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) trf->tx_cmd = TRF7970A_CMD_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) iso_ctrl &= ~TRF7970A_ISO_CTRL_RX_CRC_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) case NFC_DIGITAL_FRAMING_NFCA_T2T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) trf->tx_cmd = TRF7970A_CMD_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) iso_ctrl |= TRF7970A_ISO_CTRL_RX_CRC_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dev_dbg(trf->dev, "Unsupported Framing: %d\n", framing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) trf->framing = framing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (!(trf->chip_status_ctrl & TRF7970A_CHIP_STATUS_RF_ON)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = trf7970a_is_rf_field(trf, &is_rf_field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (is_rf_field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (iso_ctrl != trf->iso_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ret = trf7970a_write(trf, TRF7970A_ISO_CTRL, iso_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) trf->iso_ctrl = iso_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ret = trf7970a_write(trf, TRF7970A_MODULATOR_SYS_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) trf->modulator_sys_clk_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (!(trf->chip_status_ctrl & TRF7970A_CHIP_STATUS_RF_ON)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ret = trf7970a_write(trf, TRF7970A_CHIP_STATUS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) trf->chip_status_ctrl |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) TRF7970A_CHIP_STATUS_RF_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) trf->chip_status_ctrl |= TRF7970A_CHIP_STATUS_RF_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) usleep_range(trf->guard_time, trf->guard_time + 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static int trf7970a_in_configure_hw(struct nfc_digital_dev *ddev, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) int param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dev_dbg(trf->dev, "Configure hw - type: %d, param: %d\n", type, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) trf->is_initiator = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if ((trf->state == TRF7970A_ST_PWR_OFF) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) (trf->state == TRF7970A_ST_RF_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ret = trf7970a_switch_rf_on(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) case NFC_DIGITAL_CONFIG_RF_TECH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = trf7970a_in_config_rf_tech(trf, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) case NFC_DIGITAL_CONFIG_FRAMING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ret = trf7970a_in_config_framing(trf, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) dev_dbg(trf->dev, "Unknown type: %d\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static int trf7970a_is_iso15693_write_or_lock(u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) case ISO15693_CMD_WRITE_SINGLE_BLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) case ISO15693_CMD_LOCK_BLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) case ISO15693_CMD_WRITE_MULTIPLE_BLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) case ISO15693_CMD_WRITE_AFI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) case ISO15693_CMD_LOCK_AFI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) case ISO15693_CMD_WRITE_DSFID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) case ISO15693_CMD_LOCK_DSFID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static int trf7970a_per_cmd_config(struct trf7970a *trf, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) u8 *req = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) u8 special_fcn_reg1, iso_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) trf->issue_eof = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* When issuing Type 2 read command, make sure the '4_bit_RX' bit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * special functions register 1 is cleared; otherwise, its a write or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * sector select command and '4_bit_RX' must be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * When issuing an ISO 15693 command, inspect the flags byte to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * what speed to use. Also, remember if the OPTION flag is set on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * a Type 5 write or lock command so the driver will know that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * has to send an EOF in order to get a response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if ((trf->technology == NFC_DIGITAL_RF_TECH_106A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) (trf->framing == NFC_DIGITAL_FRAMING_NFCA_T2T)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (req[0] == NFC_T2T_CMD_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) special_fcn_reg1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) special_fcn_reg1 = TRF7970A_SPECIAL_FCN_REG1_4_BIT_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (special_fcn_reg1 != trf->special_fcn_reg1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ret = trf7970a_write(trf, TRF7970A_SPECIAL_FCN_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) special_fcn_reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) trf->special_fcn_reg1 = special_fcn_reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) } else if (trf->technology == NFC_DIGITAL_RF_TECH_ISO15693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) iso_ctrl = trf->iso_ctrl & ~TRF7970A_ISO_CTRL_RFID_SPEED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) switch (req[0] & ISO15693_REQ_FLAG_SPEED_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) iso_ctrl |= TRF7970A_ISO_CTRL_15693_SGL_1OF4_662;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) case ISO15693_REQ_FLAG_SUB_CARRIER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) iso_ctrl |= TRF7970A_ISO_CTRL_15693_DBL_1OF4_667a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) case ISO15693_REQ_FLAG_DATA_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) iso_ctrl |= TRF7970A_ISO_CTRL_15693_SGL_1OF4_2648;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) case (ISO15693_REQ_FLAG_SUB_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ISO15693_REQ_FLAG_DATA_RATE):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) iso_ctrl |= TRF7970A_ISO_CTRL_15693_DBL_1OF4_2669;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (iso_ctrl != trf->iso_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ret = trf7970a_write(trf, TRF7970A_ISO_CTRL, iso_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) trf->iso_ctrl = iso_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if ((trf->framing == NFC_DIGITAL_FRAMING_ISO15693_T5T) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) trf7970a_is_iso15693_write_or_lock(req[1]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) (req[0] & ISO15693_REQ_FLAG_OPTION))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) trf->issue_eof = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static int trf7970a_send_cmd(struct nfc_digital_dev *ddev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct sk_buff *skb, u16 timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) nfc_digital_cmd_complete_t cb, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) u8 prefix[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_dbg(trf->dev, "New request - state: %d, timeout: %d ms, len: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) trf->state, timeout, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (skb->len > TRF7970A_TX_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if ((trf->state != TRF7970A_ST_IDLE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) (trf->state != TRF7970A_ST_IDLE_RX_BLOCKED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) dev_err(trf->dev, "%s - Bogus state: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (trf->aborting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dev_dbg(trf->dev, "Abort process complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) trf->aborting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ret = -ECANCELED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) trf->rx_skb = nfc_alloc_recv_skb(TRF7970A_RX_SKB_ALLOC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (!trf->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) dev_dbg(trf->dev, "Can't alloc rx_skb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (trf->state == TRF7970A_ST_IDLE_RX_BLOCKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ret = trf7970a_cmd(trf, TRF7970A_CMD_ENABLE_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) trf->state = TRF7970A_ST_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (trf->is_initiator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ret = trf7970a_per_cmd_config(trf, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) trf->ddev = ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) trf->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) trf->cb = cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) trf->cb_arg = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) trf->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) trf->ignore_timeout = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* TX data must be prefixed with a FIFO reset cmd, a cmd that depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * on what the current framing is, the address of the TX length byte 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * register (0x1d), and the 2 byte length of the data to be transmitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * That totals 5 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) prefix[0] = TRF7970A_CMD_BIT_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) TRF7970A_CMD_BIT_OPCODE(TRF7970A_CMD_FIFO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) prefix[1] = TRF7970A_CMD_BIT_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) TRF7970A_CMD_BIT_OPCODE(trf->tx_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) prefix[2] = TRF7970A_CMD_BIT_CONTINUOUS | TRF7970A_TX_LENGTH_BYTE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (trf->framing == NFC_DIGITAL_FRAMING_NFCA_SHORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) prefix[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) prefix[4] = 0x0f; /* 7 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) prefix[3] = (len & 0xf00) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) prefix[3] |= ((len & 0xf0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) prefix[4] = ((len & 0x0f) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) len = min_t(int, skb->len, TRF7970A_FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* Clear possible spurious interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ret = trf7970a_read_irqstatus(trf, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ret = trf7970a_transmit(trf, skb, len, prefix, sizeof(prefix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) kfree_skb(trf->rx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) trf->rx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static int trf7970a_tg_config_rf_tech(struct trf7970a *trf, int tech)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) dev_dbg(trf->dev, "rf technology: %d\n", tech);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) switch (tech) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) case NFC_DIGITAL_RF_TECH_106A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) trf->iso_ctrl_tech = TRF7970A_ISO_CTRL_NFC_NFC_CE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) TRF7970A_ISO_CTRL_NFC_CE | TRF7970A_ISO_CTRL_NFC_CE_14443A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) trf->modulator_sys_clk_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) (trf->modulator_sys_clk_ctrl & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) TRF7970A_MODULATOR_DEPTH_OOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) case NFC_DIGITAL_RF_TECH_212F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) trf->iso_ctrl_tech = TRF7970A_ISO_CTRL_NFC_NFC_CE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) TRF7970A_ISO_CTRL_NFC_NFCF_212;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) trf->modulator_sys_clk_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) (trf->modulator_sys_clk_ctrl & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) TRF7970A_MODULATOR_DEPTH_ASK10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) case NFC_DIGITAL_RF_TECH_424F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) trf->iso_ctrl_tech = TRF7970A_ISO_CTRL_NFC_NFC_CE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) TRF7970A_ISO_CTRL_NFC_NFCF_424;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) trf->modulator_sys_clk_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) (trf->modulator_sys_clk_ctrl & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) TRF7970A_MODULATOR_DEPTH_ASK10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) dev_dbg(trf->dev, "Unsupported rf technology: %d\n", tech);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) trf->technology = tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* Normally we write the ISO_CTRL register in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * trf7970a_tg_config_framing() because the framing can change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * the value written. However, when sending a PSL RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) * digital_tg_send_psl_res_complete() doesn't call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) * trf7970a_tg_config_framing() so we must write the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if ((trf->framing == NFC_DIGITAL_FRAMING_NFC_DEP_ACTIVATED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) (trf->iso_ctrl_tech != trf->iso_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ret = trf7970a_write(trf, TRF7970A_ISO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) trf->iso_ctrl_tech);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) trf->iso_ctrl = trf->iso_ctrl_tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* Since this is a target routine, several of the framing calls are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * made between receiving the request and sending the response so they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * should take effect until after the response is sent. This is accomplished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * by skipping the ISO_CTRL register write here and doing it in the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static int trf7970a_tg_config_framing(struct trf7970a *trf, int framing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) u8 iso_ctrl = trf->iso_ctrl_tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) dev_dbg(trf->dev, "framing: %d\n", framing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) switch (framing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) case NFC_DIGITAL_FRAMING_NFCA_NFC_DEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) trf->tx_cmd = TRF7970A_CMD_TRANSMIT_NO_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) iso_ctrl |= TRF7970A_ISO_CTRL_RX_CRC_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) case NFC_DIGITAL_FRAMING_NFCA_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) case NFC_DIGITAL_FRAMING_NFCA_STANDARD_WITH_CRC_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) case NFC_DIGITAL_FRAMING_NFCA_ANTICOL_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* These ones are applied in the interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) iso_ctrl = trf->iso_ctrl; /* Don't write to ISO_CTRL yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) case NFC_DIGITAL_FRAMING_NFCF_NFC_DEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) trf->tx_cmd = TRF7970A_CMD_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) iso_ctrl &= ~TRF7970A_ISO_CTRL_RX_CRC_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) case NFC_DIGITAL_FRAMING_NFC_DEP_ACTIVATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) trf->tx_cmd = TRF7970A_CMD_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) iso_ctrl &= ~TRF7970A_ISO_CTRL_RX_CRC_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dev_dbg(trf->dev, "Unsupported Framing: %d\n", framing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) trf->framing = framing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (iso_ctrl != trf->iso_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ret = trf7970a_write(trf, TRF7970A_ISO_CTRL, iso_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) trf->iso_ctrl = iso_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ret = trf7970a_write(trf, TRF7970A_MODULATOR_SYS_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) trf->modulator_sys_clk_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (!(trf->chip_status_ctrl & TRF7970A_CHIP_STATUS_RF_ON)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ret = trf7970a_write(trf, TRF7970A_CHIP_STATUS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) trf->chip_status_ctrl |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) TRF7970A_CHIP_STATUS_RF_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) trf->chip_status_ctrl |= TRF7970A_CHIP_STATUS_RF_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static int trf7970a_tg_configure_hw(struct nfc_digital_dev *ddev, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) int param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) dev_dbg(trf->dev, "Configure hw - type: %d, param: %d\n", type, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) trf->is_initiator = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if ((trf->state == TRF7970A_ST_PWR_OFF) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) (trf->state == TRF7970A_ST_RF_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ret = trf7970a_switch_rf_on(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) case NFC_DIGITAL_CONFIG_RF_TECH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ret = trf7970a_tg_config_rf_tech(trf, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) case NFC_DIGITAL_CONFIG_FRAMING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ret = trf7970a_tg_config_framing(trf, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) dev_dbg(trf->dev, "Unknown type: %d\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static int _trf7970a_tg_listen(struct nfc_digital_dev *ddev, u16 timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) nfc_digital_cmd_complete_t cb, void *arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) bool mode_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if ((trf->state != TRF7970A_ST_IDLE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) (trf->state != TRF7970A_ST_IDLE_RX_BLOCKED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dev_err(trf->dev, "%s - Bogus state: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (trf->aborting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) dev_dbg(trf->dev, "Abort process complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) trf->aborting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) ret = -ECANCELED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) trf->rx_skb = nfc_alloc_recv_skb(TRF7970A_RX_SKB_ALLOC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (!trf->rx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) dev_dbg(trf->dev, "Can't alloc rx_skb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ret = trf7970a_write(trf, TRF7970A_RX_SPECIAL_SETTINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) TRF7970A_RX_SPECIAL_SETTINGS_HBT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) TRF7970A_RX_SPECIAL_SETTINGS_M848 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) TRF7970A_RX_SPECIAL_SETTINGS_C424 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) TRF7970A_RX_SPECIAL_SETTINGS_C212);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) ret = trf7970a_write(trf, TRF7970A_REG_IO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) trf->io_ctrl | TRF7970A_REG_IO_CTRL_VRS(0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ret = trf7970a_write(trf, TRF7970A_NFC_LOW_FIELD_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) TRF7970A_NFC_LOW_FIELD_LEVEL_RFDET(0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ret = trf7970a_write(trf, TRF7970A_NFC_TARGET_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) TRF7970A_NFC_TARGET_LEVEL_RFDET(0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) trf->ddev = ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) trf->cb = cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) trf->cb_arg = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) trf->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) trf->ignore_timeout = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ret = trf7970a_cmd(trf, TRF7970A_CMD_ENABLE_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) trf->state = mode_detect ? TRF7970A_ST_LISTENING_MD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) TRF7970A_ST_LISTENING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) schedule_delayed_work(&trf->timeout_work, msecs_to_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static int trf7970a_tg_listen(struct nfc_digital_dev *ddev, u16 timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) nfc_digital_cmd_complete_t cb, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) dev_dbg(trf->dev, "Listen - state: %d, timeout: %d ms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) trf->state, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return _trf7970a_tg_listen(ddev, timeout, cb, arg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static int trf7970a_tg_listen_md(struct nfc_digital_dev *ddev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) u16 timeout, nfc_digital_cmd_complete_t cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) dev_dbg(trf->dev, "Listen MD - state: %d, timeout: %d ms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) trf->state, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ret = trf7970a_tg_configure_hw(ddev, NFC_DIGITAL_CONFIG_RF_TECH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) NFC_DIGITAL_RF_TECH_106A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ret = trf7970a_tg_configure_hw(ddev, NFC_DIGITAL_CONFIG_FRAMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) NFC_DIGITAL_FRAMING_NFCA_NFC_DEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return _trf7970a_tg_listen(ddev, timeout, cb, arg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static int trf7970a_tg_get_rf_tech(struct nfc_digital_dev *ddev, u8 *rf_tech)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) dev_dbg(trf->dev, "Get RF Tech - state: %d, rf_tech: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) trf->state, trf->md_rf_tech);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) *rf_tech = trf->md_rf_tech;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) static void trf7970a_abort_cmd(struct nfc_digital_dev *ddev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct trf7970a *trf = nfc_digital_get_drvdata(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) dev_dbg(trf->dev, "Abort process initiated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) switch (trf->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) case TRF7970A_ST_WAIT_FOR_TX_FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) case TRF7970A_ST_WAIT_FOR_RX_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) case TRF7970A_ST_WAIT_FOR_RX_DATA_CONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) case TRF7970A_ST_WAIT_TO_ISSUE_EOF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) trf->aborting = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) case TRF7970A_ST_LISTENING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) trf->ignore_timeout = !cancel_delayed_work(&trf->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) trf7970a_send_err_upstream(trf, -ECANCELED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) dev_dbg(trf->dev, "Abort process complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static struct nfc_digital_ops trf7970a_nfc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .in_configure_hw = trf7970a_in_configure_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .in_send_cmd = trf7970a_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .tg_configure_hw = trf7970a_tg_configure_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .tg_send_cmd = trf7970a_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .tg_listen = trf7970a_tg_listen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .tg_listen_md = trf7970a_tg_listen_md,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .tg_get_rf_tech = trf7970a_tg_get_rf_tech,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .switch_rf = trf7970a_switch_rf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .abort_cmd = trf7970a_abort_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static int trf7970a_power_up(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) dev_dbg(trf->dev, "Powering up - state: %d\n", trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (trf->state != TRF7970A_ST_PWR_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ret = regulator_enable(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) dev_err(trf->dev, "%s - Can't enable VIN: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (trf->en2_gpiod &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) !(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) gpiod_set_value_cansleep(trf->en2_gpiod, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) gpiod_set_value_cansleep(trf->en_gpiod, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) usleep_range(20000, 21000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) trf->state = TRF7970A_ST_RF_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static int trf7970a_power_down(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) dev_dbg(trf->dev, "Powering down - state: %d\n", trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (trf->state == TRF7970A_ST_PWR_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (trf->state != TRF7970A_ST_RF_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) dev_dbg(trf->dev, "Can't power down - not RF_OFF state (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) trf->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) gpiod_set_value_cansleep(trf->en_gpiod, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (trf->en2_gpiod && !(trf->quirks & TRF7970A_QUIRK_EN2_MUST_STAY_LOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) gpiod_set_value_cansleep(trf->en2_gpiod, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ret = regulator_disable(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) dev_err(trf->dev, "%s - Can't disable VIN: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) trf->state = TRF7970A_ST_PWR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static int trf7970a_startup(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ret = trf7970a_power_up(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) pm_runtime_set_active(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) pm_runtime_enable(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) pm_runtime_mark_last_busy(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static void trf7970a_shutdown(struct trf7970a *trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) switch (trf->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) case TRF7970A_ST_WAIT_FOR_TX_FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) case TRF7970A_ST_WAIT_FOR_RX_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) case TRF7970A_ST_WAIT_FOR_RX_DATA_CONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) case TRF7970A_ST_WAIT_TO_ISSUE_EOF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) case TRF7970A_ST_LISTENING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) trf7970a_send_err_upstream(trf, -ECANCELED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) case TRF7970A_ST_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) case TRF7970A_ST_IDLE_RX_BLOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) trf7970a_switch_rf_off(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) pm_runtime_disable(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) pm_runtime_set_suspended(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) trf7970a_power_down(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static int trf7970a_get_autosuspend_delay(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) int autosuspend_delay, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ret = of_property_read_u32(np, "autosuspend-delay", &autosuspend_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) autosuspend_delay = TRF7970A_AUTOSUSPEND_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return autosuspend_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static int trf7970a_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) struct device_node *np = spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) struct trf7970a *trf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) int uvolts, autosuspend_delay, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) u32 clk_freq = TRF7970A_13MHZ_CLOCK_FREQUENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) dev_err(&spi->dev, "No Device Tree entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) trf = devm_kzalloc(&spi->dev, sizeof(*trf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (!trf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) trf->state = TRF7970A_ST_PWR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) trf->dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) trf->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) spi->mode = SPI_MODE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) dev_err(trf->dev, "Can't set up SPI Communication\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (of_property_read_bool(np, "irq-status-read-quirk"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) trf->quirks |= TRF7970A_QUIRK_IRQ_STATUS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* There are two enable pins - only EN must be present in the DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) trf->en_gpiod = devm_gpiod_get_index(trf->dev, "ti,enable", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (IS_ERR(trf->en_gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) dev_err(trf->dev, "No EN GPIO property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) return PTR_ERR(trf->en_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) trf->en2_gpiod = devm_gpiod_get_index_optional(trf->dev, "ti,enable", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (!trf->en2_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) dev_info(trf->dev, "No EN2 GPIO property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) } else if (IS_ERR(trf->en2_gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) dev_err(trf->dev, "Error getting EN2 GPIO property: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) PTR_ERR(trf->en2_gpiod));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return PTR_ERR(trf->en2_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) } else if (of_property_read_bool(np, "en2-rf-quirk")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) trf->quirks |= TRF7970A_QUIRK_EN2_MUST_STAY_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) of_property_read_u32(np, "clock-frequency", &clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if ((clk_freq != TRF7970A_27MHZ_CLOCK_FREQUENCY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) (clk_freq != TRF7970A_13MHZ_CLOCK_FREQUENCY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) dev_err(trf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) "clock-frequency (%u Hz) unsupported\n", clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (clk_freq == TRF7970A_27MHZ_CLOCK_FREQUENCY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) trf->modulator_sys_clk_ctrl = TRF7970A_MODULATOR_27MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) dev_dbg(trf->dev, "trf7970a configured for 27MHz crystal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) trf->modulator_sys_clk_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ret = devm_request_threaded_irq(trf->dev, spi->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) trf7970a_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) "trf7970a", trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) dev_err(trf->dev, "Can't request IRQ#%d: %d\n", spi->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) mutex_init(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) INIT_DELAYED_WORK(&trf->timeout_work, trf7970a_timeout_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) trf->regulator = devm_regulator_get(&spi->dev, "vin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (IS_ERR(trf->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ret = PTR_ERR(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) dev_err(trf->dev, "Can't get VIN regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) goto err_destroy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ret = regulator_enable(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) dev_err(trf->dev, "Can't enable VIN: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) goto err_destroy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) uvolts = regulator_get_voltage(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (uvolts > 4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) trf->chip_status_ctrl = TRF7970A_CHIP_STATUS_VRS5_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) trf->regulator = devm_regulator_get(&spi->dev, "vdd-io");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (IS_ERR(trf->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ret = PTR_ERR(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) dev_err(trf->dev, "Can't get VDD_IO regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) goto err_destroy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) ret = regulator_enable(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) dev_err(trf->dev, "Can't enable VDD_IO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) goto err_destroy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (regulator_get_voltage(trf->regulator) == 1800000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) trf->io_ctrl = TRF7970A_REG_IO_CTRL_IO_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) dev_dbg(trf->dev, "trf7970a config vdd_io to 1.8V\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) trf->ddev = nfc_digital_allocate_device(&trf7970a_nfc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) TRF7970A_SUPPORTED_PROTOCOLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) NFC_DIGITAL_DRV_CAPS_IN_CRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) NFC_DIGITAL_DRV_CAPS_TG_CRC, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (!trf->ddev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) dev_err(trf->dev, "Can't allocate NFC digital device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) goto err_disable_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) nfc_digital_set_parent_dev(trf->ddev, trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) nfc_digital_set_drvdata(trf->ddev, trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) spi_set_drvdata(spi, trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) autosuspend_delay = trf7970a_get_autosuspend_delay(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) pm_runtime_set_autosuspend_delay(trf->dev, autosuspend_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) pm_runtime_use_autosuspend(trf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ret = trf7970a_startup(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) goto err_free_ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ret = nfc_digital_register_device(trf->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) dev_err(trf->dev, "Can't register NFC digital device: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) goto err_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) err_shutdown:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) trf7970a_shutdown(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) err_free_ddev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) nfc_digital_free_device(trf->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) err_disable_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) regulator_disable(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) err_destroy_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) mutex_destroy(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) static int trf7970a_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) struct trf7970a *trf = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) trf7970a_shutdown(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) nfc_digital_unregister_device(trf->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) nfc_digital_free_device(trf->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) regulator_disable(trf->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) mutex_destroy(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static int trf7970a_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) struct trf7970a *trf = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) dev_dbg(dev, "Suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) trf7970a_shutdown(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) static int trf7970a_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) struct trf7970a *trf = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) dev_dbg(dev, "Resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ret = trf7970a_startup(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static int trf7970a_pm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) struct trf7970a *trf = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) dev_dbg(dev, "Runtime suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) mutex_lock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) ret = trf7970a_power_down(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) mutex_unlock(&trf->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static int trf7970a_pm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) struct trf7970a *trf = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) dev_dbg(dev, "Runtime resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) ret = trf7970a_power_up(trf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static const struct dev_pm_ops trf7970a_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) SET_SYSTEM_SLEEP_PM_OPS(trf7970a_suspend, trf7970a_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) SET_RUNTIME_PM_OPS(trf7970a_pm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) trf7970a_pm_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) static const struct of_device_id trf7970a_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) {.compatible = "ti,trf7970a",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) MODULE_DEVICE_TABLE(of, trf7970a_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static const struct spi_device_id trf7970a_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {"trf7970a", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) MODULE_DEVICE_TABLE(spi, trf7970a_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) static struct spi_driver trf7970a_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .probe = trf7970a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .remove = trf7970a_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .id_table = trf7970a_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .name = "trf7970a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .of_match_table = of_match_ptr(trf7970a_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .pm = &trf7970a_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) module_spi_driver(trf7970a_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) MODULE_AUTHOR("Mark A. Greer <mgreer@animalcreek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) MODULE_DESCRIPTION("TI trf7970a RFID/NFC Transceiver Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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