^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Low Level Transport (NDLC) Driver for STMicroelectronics NFC Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <net/nfc/nci_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "st-nci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NDLC_TIMER_T1 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NDLC_TIMER_T1_WAIT 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NDLC_TIMER_T2 1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCB_TYPE_DATAFRAME 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCB_TYPE_SUPERVISOR 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCB_TYPE_MASK PCB_TYPE_SUPERVISOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCB_SYNC_ACK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCB_SYNC_NACK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCB_SYNC_WAIT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCB_SYNC_NOINFO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCB_SYNC_MASK PCB_SYNC_WAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCB_DATAFRAME_RETRANSMIT_YES 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCB_DATAFRAME_RETRANSMIT_NO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCB_DATAFRAME_RETRANSMIT_MASK PCB_DATAFRAME_RETRANSMIT_NO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCB_SUPERVISOR_RETRANSMIT_YES 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCB_SUPERVISOR_RETRANSMIT_NO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCB_SUPERVISOR_RETRANSMIT_MASK PCB_SUPERVISOR_RETRANSMIT_NO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCB_FRAME_CRC_INFO_PRESENT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCB_FRAME_CRC_INFO_NOTPRESENT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCB_FRAME_CRC_INFO_MASK PCB_FRAME_CRC_INFO_PRESENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NDLC_DUMP_SKB(info, skb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pr_debug("%s:\n", info); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) print_hex_dump(KERN_DEBUG, "ndlc: ", DUMP_PREFIX_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 16, 1, skb->data, skb->len, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int ndlc_open(struct llt_ndlc *ndlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* toggle reset pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ndlc->ops->enable(ndlc->phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ndlc->powered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) EXPORT_SYMBOL(ndlc_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void ndlc_close(struct llt_ndlc *ndlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct nci_mode_set_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) cmd.cmd_type = ST_NCI_SET_NFC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cmd.mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* toggle reset pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ndlc->ops->enable(ndlc->phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) nci_prop_cmd(ndlc->ndev, ST_NCI_CORE_PROP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) sizeof(struct nci_mode_set_cmd), (__u8 *)&cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ndlc->powered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ndlc->ops->disable(ndlc->phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) EXPORT_SYMBOL(ndlc_close);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ndlc_send(struct llt_ndlc *ndlc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* add ndlc header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 pcb = PCB_TYPE_DATAFRAME | PCB_DATAFRAME_RETRANSMIT_NO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PCB_FRAME_CRC_INFO_NOTPRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *(u8 *)skb_push(skb, 1) = pcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) skb_queue_tail(&ndlc->send_q, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) schedule_work(&ndlc->sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) EXPORT_SYMBOL(ndlc_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void llt_ndlc_send_queue(struct llt_ndlc *ndlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long time_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ndlc->send_q.qlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pr_debug("sendQlen=%d unackQlen=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ndlc->send_q.qlen, ndlc->ack_pending_q.qlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) while (ndlc->send_q.qlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) skb = skb_dequeue(&ndlc->send_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) NDLC_DUMP_SKB("ndlc frame written", skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) r = ndlc->ops->write(ndlc->phy_id, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ndlc->hard_fault = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) time_sent = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *(unsigned long *)skb->cb = time_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) skb_queue_tail(&ndlc->ack_pending_q, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* start timer t1 for ndlc aknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ndlc->t1_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mod_timer(&ndlc->t1_timer, time_sent +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) msecs_to_jiffies(NDLC_TIMER_T1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* start timer t2 for chip availability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ndlc->t2_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mod_timer(&ndlc->t2_timer, time_sent +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) msecs_to_jiffies(NDLC_TIMER_T2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void llt_ndlc_requeue_data_pending(struct llt_ndlc *ndlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 pcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) while ((skb = skb_dequeue_tail(&ndlc->ack_pending_q))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pcb = skb->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) switch (pcb & PCB_TYPE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case PCB_TYPE_SUPERVISOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) skb->data[0] = (pcb & ~PCB_SUPERVISOR_RETRANSMIT_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PCB_SUPERVISOR_RETRANSMIT_YES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case PCB_TYPE_DATAFRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) skb->data[0] = (pcb & ~PCB_DATAFRAME_RETRANSMIT_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PCB_DATAFRAME_RETRANSMIT_YES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_err("UNKNOWN Packet Control Byte=%d\n", pcb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) skb_queue_head(&ndlc->send_q, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void llt_ndlc_rcv_queue(struct llt_ndlc *ndlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 pcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long time_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ndlc->rcv_q.qlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pr_debug("rcvQlen=%d\n", ndlc->rcv_q.qlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) while ((skb = skb_dequeue(&ndlc->rcv_q)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pcb = skb->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) skb_pull(skb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if ((pcb & PCB_TYPE_MASK) == PCB_TYPE_SUPERVISOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) switch (pcb & PCB_SYNC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case PCB_SYNC_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) skb = skb_dequeue(&ndlc->ack_pending_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) del_timer_sync(&ndlc->t1_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) del_timer_sync(&ndlc->t2_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ndlc->t2_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ndlc->t1_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case PCB_SYNC_NACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) llt_ndlc_requeue_data_pending(ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) llt_ndlc_send_queue(ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* start timer t1 for ndlc aknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) time_sent = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ndlc->t1_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mod_timer(&ndlc->t1_timer, time_sent +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) msecs_to_jiffies(NDLC_TIMER_T1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case PCB_SYNC_WAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) time_sent = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ndlc->t1_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mod_timer(&ndlc->t1_timer, time_sent +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) msecs_to_jiffies(NDLC_TIMER_T1_WAIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } else if ((pcb & PCB_TYPE_MASK) == PCB_TYPE_DATAFRAME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) nci_recv_frame(ndlc->ndev, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void llt_ndlc_sm_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct llt_ndlc *ndlc = container_of(work, struct llt_ndlc, sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) llt_ndlc_send_queue(ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) llt_ndlc_rcv_queue(ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ndlc->t1_active && timer_pending(&ndlc->t1_timer) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pr_debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ("Handle T1(recv SUPERVISOR) elapsed (T1 now inactive)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ndlc->t1_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) llt_ndlc_requeue_data_pending(ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) llt_ndlc_send_queue(ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ndlc->t2_active && timer_pending(&ndlc->t2_timer) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pr_debug("Handle T2(recv DATA) elapsed (T2 now inactive)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ndlc->t2_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ndlc->t1_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) del_timer_sync(&ndlc->t1_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) del_timer_sync(&ndlc->t2_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ndlc_close(ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ndlc->hard_fault = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void ndlc_recv(struct llt_ndlc *ndlc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pr_err("NULL Frame -> link is dead\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ndlc->hard_fault = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ndlc_close(ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) NDLC_DUMP_SKB("incoming frame", skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) skb_queue_tail(&ndlc->rcv_q, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) schedule_work(&ndlc->sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) EXPORT_SYMBOL(ndlc_recv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void ndlc_t1_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct llt_ndlc *ndlc = from_timer(ndlc, t, t1_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pr_debug("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) schedule_work(&ndlc->sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void ndlc_t2_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct llt_ndlc *ndlc = from_timer(ndlc, t, t2_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pr_debug("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) schedule_work(&ndlc->sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int ndlc_probe(void *phy_id, struct nfc_phy_ops *phy_ops, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int phy_headroom, int phy_tailroom, struct llt_ndlc **ndlc_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct st_nci_se_status *se_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct llt_ndlc *ndlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ndlc = devm_kzalloc(dev, sizeof(struct llt_ndlc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!ndlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ndlc->ops = phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ndlc->phy_id = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ndlc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ndlc->powered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *ndlc_id = ndlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* initialize timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) timer_setup(&ndlc->t1_timer, ndlc_t1_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) timer_setup(&ndlc->t2_timer, ndlc_t2_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) skb_queue_head_init(&ndlc->rcv_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) skb_queue_head_init(&ndlc->send_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) skb_queue_head_init(&ndlc->ack_pending_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) INIT_WORK(&ndlc->sm_work, llt_ndlc_sm_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return st_nci_probe(ndlc, phy_headroom, phy_tailroom, se_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) EXPORT_SYMBOL(ndlc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void ndlc_remove(struct llt_ndlc *ndlc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) st_nci_remove(ndlc->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* cancel timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) del_timer_sync(&ndlc->t1_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) del_timer_sync(&ndlc->t2_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ndlc->t2_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ndlc->t1_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) skb_queue_purge(&ndlc->rcv_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) skb_queue_purge(&ndlc->send_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EXPORT_SYMBOL(ndlc_remove);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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