Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * I2C Link Layer for Samsung S3FWRN5 NCI based Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Samsung Electrnoics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Robert Baldyga <r.baldyga@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <net/nfc/nfc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "s3fwrn5.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define S3FWRN5_I2C_DRIVER_NAME "s3fwrn5_i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define S3FWRN5_I2C_MAX_PAYLOAD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define S3FWRN5_EN_WAIT_TIME 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct s3fwrn5_i2c_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct i2c_client *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct nci_dev *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	int gpio_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int gpio_fw_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	enum s3fwrn5_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned int irq_skip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static void s3fwrn5_i2c_set_wake(void *phy_id, bool wake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct s3fwrn5_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	mutex_lock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	gpio_set_value(phy->gpio_fw_wake, wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	msleep(S3FWRN5_EN_WAIT_TIME/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	mutex_unlock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void s3fwrn5_i2c_set_mode(void *phy_id, enum s3fwrn5_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct s3fwrn5_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	mutex_lock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (phy->mode == mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	phy->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	gpio_set_value(phy->gpio_en, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	gpio_set_value(phy->gpio_fw_wake, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (mode == S3FWRN5_MODE_FW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		gpio_set_value(phy->gpio_fw_wake, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (mode != S3FWRN5_MODE_COLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		msleep(S3FWRN5_EN_WAIT_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		gpio_set_value(phy->gpio_en, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		msleep(S3FWRN5_EN_WAIT_TIME/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	phy->irq_skip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mutex_unlock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static enum s3fwrn5_mode s3fwrn5_i2c_get_mode(void *phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct s3fwrn5_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	enum s3fwrn5_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mutex_lock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	mode = phy->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	mutex_unlock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int s3fwrn5_i2c_write(void *phy_id, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct s3fwrn5_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mutex_lock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	phy->irq_skip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	ret = i2c_master_send(phy->i2c_dev, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (ret == -EREMOTEIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		/* Retry, chip was in standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		usleep_range(110000, 120000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		ret  = i2c_master_send(phy->i2c_dev, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	mutex_unlock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (ret != skb->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct s3fwrn5_phy_ops i2c_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.set_wake = s3fwrn5_i2c_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.set_mode = s3fwrn5_i2c_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.get_mode = s3fwrn5_i2c_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.write = s3fwrn5_i2c_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int s3fwrn5_i2c_read(struct s3fwrn5_i2c_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	size_t hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	size_t data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	char hdr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	hdr_size = (phy->mode == S3FWRN5_MODE_NCI) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		NCI_CTRL_HDR_SIZE : S3FWRN5_FW_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ret = i2c_master_recv(phy->i2c_dev, hdr, hdr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (ret < hdr_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	data_len = (phy->mode == S3FWRN5_MODE_NCI) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		((struct nci_ctrl_hdr *)hdr)->plen :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		((struct s3fwrn5_fw_header *)hdr)->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	skb = alloc_skb(hdr_size + data_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	skb_put_data(skb, hdr, hdr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (data_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ret = i2c_master_recv(phy->i2c_dev, skb_put(skb, data_len), data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (ret != data_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return s3fwrn5_recv_frame(phy->ndev, skb, phy->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static irqreturn_t s3fwrn5_i2c_irq_thread_fn(int irq, void *phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct s3fwrn5_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (!phy || !phy->ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	mutex_lock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (phy->irq_skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	switch (phy->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	case S3FWRN5_MODE_NCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case S3FWRN5_MODE_FW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		s3fwrn5_i2c_read(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	case S3FWRN5_MODE_COLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	mutex_unlock(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int s3fwrn5_i2c_parse_dt(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct s3fwrn5_i2c_phy *phy = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	phy->gpio_en = of_get_named_gpio(np, "en-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (!gpio_is_valid(phy->gpio_en)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		/* Support also deprecated property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		phy->gpio_en = of_get_named_gpio(np, "s3fwrn5,en-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (!gpio_is_valid(phy->gpio_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	phy->gpio_fw_wake = of_get_named_gpio(np, "wake-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (!gpio_is_valid(phy->gpio_fw_wake)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		/* Support also deprecated property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		phy->gpio_fw_wake = of_get_named_gpio(np, "s3fwrn5,fw-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (!gpio_is_valid(phy->gpio_fw_wake))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int s3fwrn5_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				  const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct s3fwrn5_i2c_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	phy = devm_kzalloc(&client->dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	mutex_init(&phy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	phy->mode = S3FWRN5_MODE_COLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	phy->irq_skip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	phy->i2c_dev = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	i2c_set_clientdata(client, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ret = s3fwrn5_i2c_parse_dt(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ret = devm_gpio_request_one(&phy->i2c_dev->dev, phy->gpio_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		GPIOF_OUT_INIT_HIGH, "s3fwrn5_en");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ret = devm_gpio_request_one(&phy->i2c_dev->dev, phy->gpio_fw_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		GPIOF_OUT_INIT_LOW, "s3fwrn5_fw_wake");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = s3fwrn5_probe(&phy->ndev, phy, &phy->i2c_dev->dev, &i2c_phy_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		S3FWRN5_I2C_MAX_PAYLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ret = devm_request_threaded_irq(&client->dev, phy->i2c_dev->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		s3fwrn5_i2c_irq_thread_fn, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		S3FWRN5_I2C_DRIVER_NAME, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		s3fwrn5_remove(phy->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int s3fwrn5_i2c_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct s3fwrn5_i2c_phy *phy = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	s3fwrn5_remove(phy->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct i2c_device_id s3fwrn5_i2c_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	{S3FWRN5_I2C_DRIVER_NAME, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_DEVICE_TABLE(i2c, s3fwrn5_i2c_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct of_device_id of_s3fwrn5_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{ .compatible = "samsung,s3fwrn5-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_DEVICE_TABLE(of, of_s3fwrn5_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct i2c_driver s3fwrn5_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.name = S3FWRN5_I2C_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.of_match_table = of_match_ptr(of_s3fwrn5_i2c_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.probe = s3fwrn5_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.remove = s3fwrn5_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.id_table = s3fwrn5_i2c_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) module_i2c_driver(s3fwrn5_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_DESCRIPTION("I2C driver for Samsung S3FWRN5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_AUTHOR("Robert Baldyga <r.baldyga@samsung.com>");