Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * NCI based driver for Samsung S3FWRN5 NFC chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Samsung Electrnoics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Robert Baldyga <r.baldyga@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <crypto/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <crypto/sha.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "s3fwrn5.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "firmware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) struct s3fwrn5_fw_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	__u8 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	__u8 build1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	__u8 build2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	__u8 target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static int s3fwrn5_fw_send_msg(struct s3fwrn5_fw_info *fw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct sk_buff *msg, struct sk_buff **rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct s3fwrn5_info *info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		container_of(fw_info, struct s3fwrn5_info, fw_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	reinit_completion(&fw_info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	ret = s3fwrn5_write(info, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	ret = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		&fw_info->completion, msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	else if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (!fw_info->rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	*rsp = fw_info->rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	fw_info->rsp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int s3fwrn5_fw_prep_msg(struct s3fwrn5_fw_info *fw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct sk_buff **msg, u8 type, u8 code, const void *data, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct s3fwrn5_fw_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	hdr.type = type | fw_info->parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	fw_info->parity ^= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	hdr.code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	hdr.len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	skb = alloc_skb(S3FWRN5_FW_HDR_SIZE + len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	skb_put_data(skb, &hdr, S3FWRN5_FW_HDR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		skb_put_data(skb, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	*msg = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int s3fwrn5_fw_get_bootinfo(struct s3fwrn5_fw_info *fw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct s3fwrn5_fw_cmd_get_bootinfo_rsp *bootinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct sk_buff *msg, *rsp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct s3fwrn5_fw_header *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* Send GET_BOOTINFO command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ret = s3fwrn5_fw_prep_msg(fw_info, &msg, S3FWRN5_FW_MSG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		S3FWRN5_FW_CMD_GET_BOOTINFO, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ret = s3fwrn5_fw_send_msg(fw_info, msg, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	kfree_skb(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	hdr = (struct s3fwrn5_fw_header *) rsp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (hdr->code != S3FWRN5_FW_RET_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	memcpy(bootinfo, rsp->data + S3FWRN5_FW_HDR_SIZE, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	kfree_skb(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int s3fwrn5_fw_enter_update_mode(struct s3fwrn5_fw_info *fw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	const void *hash_data, u16 hash_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	const void *sig_data, u16 sig_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct s3fwrn5_fw_cmd_enter_updatemode args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct sk_buff *msg, *rsp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct s3fwrn5_fw_header *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/* Send ENTER_UPDATE_MODE command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	args.hashcode_size = hash_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	args.signature_size = sig_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ret = s3fwrn5_fw_prep_msg(fw_info, &msg, S3FWRN5_FW_MSG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		S3FWRN5_FW_CMD_ENTER_UPDATE_MODE, &args, sizeof(args));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	ret = s3fwrn5_fw_send_msg(fw_info, msg, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	kfree_skb(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	hdr = (struct s3fwrn5_fw_header *) rsp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (hdr->code != S3FWRN5_FW_RET_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	kfree_skb(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Send hashcode data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ret = s3fwrn5_fw_prep_msg(fw_info, &msg, S3FWRN5_FW_MSG_DATA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		hash_data, hash_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ret = s3fwrn5_fw_send_msg(fw_info, msg, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	kfree_skb(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	hdr = (struct s3fwrn5_fw_header *) rsp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (hdr->code != S3FWRN5_FW_RET_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	kfree_skb(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* Send signature data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ret = s3fwrn5_fw_prep_msg(fw_info, &msg, S3FWRN5_FW_MSG_DATA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		sig_data, sig_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ret = s3fwrn5_fw_send_msg(fw_info, msg, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	kfree_skb(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	hdr = (struct s3fwrn5_fw_header *) rsp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (hdr->code != S3FWRN5_FW_RET_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	kfree_skb(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int s3fwrn5_fw_update_sector(struct s3fwrn5_fw_info *fw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 base_addr, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct s3fwrn5_fw_cmd_update_sector args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct sk_buff *msg, *rsp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct s3fwrn5_fw_header *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* Send UPDATE_SECTOR command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	args.base_address = base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ret = s3fwrn5_fw_prep_msg(fw_info, &msg, S3FWRN5_FW_MSG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		S3FWRN5_FW_CMD_UPDATE_SECTOR, &args, sizeof(args));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ret = s3fwrn5_fw_send_msg(fw_info, msg, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	kfree_skb(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	hdr = (struct s3fwrn5_fw_header *) rsp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (hdr->code != S3FWRN5_FW_RET_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	kfree_skb(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* Send data split into 256-byte packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	for (i = 0; i < 16; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		ret = s3fwrn5_fw_prep_msg(fw_info, &msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			S3FWRN5_FW_MSG_DATA, 0, data+256*i, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		ret = s3fwrn5_fw_send_msg(fw_info, msg, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		kfree_skb(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		hdr = (struct s3fwrn5_fw_header *) rsp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		if (hdr->code != S3FWRN5_FW_RET_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		kfree_skb(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	kfree_skb(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int s3fwrn5_fw_complete_update_mode(struct s3fwrn5_fw_info *fw_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct sk_buff *msg, *rsp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct s3fwrn5_fw_header *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/* Send COMPLETE_UPDATE_MODE command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret = s3fwrn5_fw_prep_msg(fw_info, &msg, S3FWRN5_FW_MSG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		S3FWRN5_FW_CMD_COMPLETE_UPDATE_MODE, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ret = s3fwrn5_fw_send_msg(fw_info, msg, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	kfree_skb(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	hdr = (struct s3fwrn5_fw_header *) rsp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (hdr->code != S3FWRN5_FW_RET_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	kfree_skb(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * Firmware header stucture:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * 0x00 - 0x0B : Date and time string (w/o NUL termination)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * 0x10 - 0x13 : Firmware version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * 0x14 - 0x17 : Signature address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * 0x18 - 0x1B : Signature size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * 0x1C - 0x1F : Firmware image address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * 0x20 - 0x23 : Firmware sectors count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * 0x24 - 0x27 : Custom signature address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * 0x28 - 0x2B : Custom signature size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define S3FWRN5_FW_IMAGE_HEADER_SIZE 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int s3fwrn5_fw_request_firmware(struct s3fwrn5_fw_info *fw_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct s3fwrn5_fw_image *fw = &fw_info->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	u32 sig_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	u32 image_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	u32 custom_sig_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ret = request_firmware(&fw->fw, fw_info->fw_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		&fw_info->ndev->nfc_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (fw->fw->size < S3FWRN5_FW_IMAGE_HEADER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		release_firmware(fw->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	memcpy(fw->date, fw->fw->data + 0x00, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	fw->date[12] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	memcpy(&fw->version, fw->fw->data + 0x10, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	memcpy(&sig_off, fw->fw->data + 0x14, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	fw->sig = fw->fw->data + sig_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	memcpy(&fw->sig_size, fw->fw->data + 0x18, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	memcpy(&image_off, fw->fw->data + 0x1C, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	fw->image = fw->fw->data + image_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	memcpy(&fw->image_sectors, fw->fw->data + 0x20, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	memcpy(&custom_sig_off, fw->fw->data + 0x24, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	fw->custom_sig = fw->fw->data + custom_sig_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	memcpy(&fw->custom_sig_size, fw->fw->data + 0x28, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void s3fwrn5_fw_release_firmware(struct s3fwrn5_fw_info *fw_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	release_firmware(fw_info->fw.fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int s3fwrn5_fw_get_base_addr(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct s3fwrn5_fw_cmd_get_bootinfo_rsp *bootinfo, u32 *base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		u8 version[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		u32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	} match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		{{0x05, 0x00, 0x00, 0x00}, 0x00005000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		{{0x05, 0x00, 0x00, 0x01}, 0x00003000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		{{0x05, 0x00, 0x00, 0x02}, 0x00003000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		{{0x05, 0x00, 0x00, 0x03}, 0x00003000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		{{0x05, 0x00, 0x00, 0x05}, 0x00003000}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	for (i = 0; i < ARRAY_SIZE(match); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		if (bootinfo->hw_version[0] == match[i].version[0] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			bootinfo->hw_version[1] == match[i].version[1] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			bootinfo->hw_version[3] == match[i].version[3]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			*base_addr = match[i].base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) s3fwrn5_fw_is_custom(const struct s3fwrn5_fw_cmd_get_bootinfo_rsp *bootinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return !!bootinfo->hw_version[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int s3fwrn5_fw_setup(struct s3fwrn5_fw_info *fw_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	struct s3fwrn5_fw_cmd_get_bootinfo_rsp bootinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	/* Get firmware data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	ret = s3fwrn5_fw_request_firmware(fw_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		dev_err(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			"Failed to get fw file, ret=%02x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/* Get bootloader info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	ret = s3fwrn5_fw_get_bootinfo(fw_info, &bootinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		dev_err(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			"Failed to get bootinfo, ret=%02x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	/* Match hardware version to obtain firmware base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ret = s3fwrn5_fw_get_base_addr(&bootinfo, &fw_info->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		dev_err(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			"Unknown hardware version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	fw_info->sector_size = bootinfo.sector_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	fw_info->sig_size = s3fwrn5_fw_is_custom(&bootinfo) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		fw_info->fw.custom_sig_size : fw_info->fw.sig_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	fw_info->sig = s3fwrn5_fw_is_custom(&bootinfo) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		fw_info->fw.custom_sig : fw_info->fw.sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	s3fwrn5_fw_release_firmware(fw_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) bool s3fwrn5_fw_check_version(const struct s3fwrn5_fw_info *fw_info, u32 version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	struct s3fwrn5_fw_version *new = (void *) &fw_info->fw.version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	struct s3fwrn5_fw_version *old = (void *) &version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	if (new->major > old->major)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (new->build1 > old->build1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (new->build2 > old->build2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int s3fwrn5_fw_download(struct s3fwrn5_fw_info *fw_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct s3fwrn5_fw_image *fw = &fw_info->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	u8 hash_data[SHA1_DIGEST_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	struct crypto_shash *tfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	u32 image_size, off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	image_size = fw_info->sector_size * fw->image_sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	/* Compute SHA of firmware data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	tfm = crypto_alloc_shash("sha1", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	if (IS_ERR(tfm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		ret = PTR_ERR(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		dev_err(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 			"Cannot allocate shash (code=%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	ret = crypto_shash_tfm_digest(tfm, fw->image, image_size, hash_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	crypto_free_shash(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		dev_err(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			"Cannot compute hash (code=%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	/* Firmware update process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	dev_info(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		"Firmware update: %s\n", fw_info->fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	ret = s3fwrn5_fw_enter_update_mode(fw_info, hash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		SHA1_DIGEST_SIZE, fw_info->sig, fw_info->sig_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		dev_err(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			"Unable to enter update mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	for (off = 0; off < image_size; off += fw_info->sector_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		ret = s3fwrn5_fw_update_sector(fw_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 			fw_info->base_addr + off, fw->image + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			dev_err(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 				"Firmware update error (code=%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	ret = s3fwrn5_fw_complete_update_mode(fw_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		dev_err(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 			"Unable to complete update mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	dev_info(&fw_info->ndev->nfc_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		"Firmware update: success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) void s3fwrn5_fw_init(struct s3fwrn5_fw_info *fw_info, const char *fw_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	fw_info->parity = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	fw_info->rsp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	fw_info->fw.fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	strcpy(fw_info->fw_name, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	init_completion(&fw_info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) void s3fwrn5_fw_cleanup(struct s3fwrn5_fw_info *fw_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	s3fwrn5_fw_release_firmware(fw_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int s3fwrn5_fw_recv_frame(struct nci_dev *ndev, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	struct s3fwrn5_info *info = nci_get_drvdata(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	struct s3fwrn5_fw_info *fw_info = &info->fw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	if (WARN_ON(fw_info->rsp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	fw_info->rsp = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	complete(&fw_info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }