^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * I2C Link Layer for PN544 HCI based Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/crc-ccitt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/nfc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <net/nfc/hci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <net/nfc/llc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <net/nfc/nfc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pn544.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PN544_I2C_FRAME_HEADROOM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PN544_I2C_FRAME_TAILROOM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* GPIO names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PN544_GPIO_NAME_IRQ "pn544_irq"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PN544_GPIO_NAME_FW "pn544_fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PN544_GPIO_NAME_EN "pn544_en"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* framing in HCI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PN544_HCI_I2C_LLC_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PN544_HCI_I2C_LLC_CRC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PN544_HCI_I2C_LLC_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PN544_HCI_I2C_LLC_MAX_PAYLOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct i2c_device_id pn544_hci_i2c_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {"pn544", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct acpi_device_id pn544_hci_i2c_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {"NXP5440", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Exposed through the 4 most significant bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * from the HCI SW_VERSION first byte, a.k.a.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * SW RomLib.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PN544_HW_VARIANT_C2 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PN544_HW_VARIANT_C3 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PN544_FW_CMD_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PN544_FW_CMD_WRITE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PN544_FW_CMD_CHECK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PN544_FW_CMD_SECURE_WRITE 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct pn544_i2c_fw_frame_write {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u16 be_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 be_dest_addr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u16 be_datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pn544_i2c_fw_frame_check {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 be_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 be_start_addr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u16 be_datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 be_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct pn544_i2c_fw_frame_response {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 be_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct pn544_i2c_fw_blob {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 be_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 be_destaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct pn544_i2c_fw_secure_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 be_datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pn544_i2c_fw_secure_blob {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u64 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PN544_FW_CMD_RESULT_TIMEOUT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PN544_FW_CMD_RESULT_BAD_CRC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PN544_FW_WRITE_BUFFER_MAX_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PN544_FW_SECURE_FRAME_HEADER_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PN544_FW_SECURE_BLOB_HEADER_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FW_WORK_STATE_IDLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FW_WORK_STATE_START 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct pn544_i2c_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct i2c_client *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct nfc_hci_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct gpio_desc *gpiod_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct gpio_desc *gpiod_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int en_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 hw_variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct work_struct fw_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int fw_work_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 fw_blob_dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) size_t fw_blob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const u8 *fw_blob_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) size_t fw_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) size_t fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int fw_cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int powered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int run_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int hard_fault; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * < 0 if hardware error occured (e.g. i2c err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * and prevents normal operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define I2C_DUMP_SKB(info, skb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pr_debug("%s:\n", info); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 16, 1, (skb)->data, (skb)->len, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int polarity, retry, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int count = sizeof(rset_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Disable fw download */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) gpiod_set_value_cansleep(phy->gpiod_fw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for (polarity = 0; polarity < 2; polarity++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) phy->en_polarity = polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) retry = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) while (retry--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* send reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = i2c_master_send(phy->i2c_dev, rset_cmd, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret == count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) nfc_info(&phy->i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "nfc_en polarity : active %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (polarity == 0 ? "low" : "high"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) nfc_err(&phy->i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "Could not detect nfc_en polarity, fallback to active high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) gpiod_set_value_cansleep(phy->gpiod_fw, run_mode == PN544_FW_MODE ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) phy->run_mode = run_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int pn544_hci_i2c_enable(void *phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct pn544_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pr_info("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) phy->powered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void pn544_hci_i2c_disable(void *phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct pn544_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) gpiod_set_value_cansleep(phy->gpiod_fw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) phy->powered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u16 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) len = skb->len + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *(u8 *)skb_push(skb, 1) = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) crc = crc_ccitt(0xffff, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) crc = ~crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) skb_put_u8(skb, crc & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) skb_put_u8(skb, crc >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) skb_pull(skb, PN544_I2C_FRAME_HEADROOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) skb_trim(skb, PN544_I2C_FRAME_TAILROOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Writing a frame must not return the number of written bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * It must return either zero for success, or <0 for error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * In addition, it must not alter the skb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct pn544_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct i2c_client *client = phy->i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (phy->hard_fault != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return phy->hard_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) usleep_range(3000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pn544_hci_i2c_add_len_crc(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) I2C_DUMP_SKB("i2c frame written", skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) r = i2c_master_send(client, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (r == -EREMOTEIO) { /* Retry, chip was in standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) usleep_range(6000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) r = i2c_master_send(client, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (r >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (r != skb->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) r = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pn544_hci_i2c_remove_len_crc(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int check_crc(u8 *buf, int buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u16 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) len = buf[0] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) crc = crc_ccitt(0xffff, buf, len - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) crc = ~crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pr_err("CRC error 0x%x != 0x%x 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) crc, buf[len - 1], buf[len - 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pr_info("%s: BAD CRC\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 16, 2, buf, buflen, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * that i2c bus will be flushed and that next read will start on a new frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * returned skb contains only LLC header and payload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * -EREMOTEIO : i2c read error (fatal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * -EBADMSG : frame was incorrect and discarded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * -ENOMEM : cannot allocate skb, frame dropped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct i2c_client *client = phy->i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) r = i2c_master_recv(client, &len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (r != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) nfc_err(&client->dev, "cannot read len byte\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) nfc_err(&client->dev, "invalid len byte\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) r = -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *skb = alloc_skb(1 + len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (*skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) skb_put_u8(*skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) r = i2c_master_recv(client, skb_put(*skb, len), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (r != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) kfree_skb(*skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) I2C_DUMP_SKB("i2c frame read", *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) r = check_crc((*skb)->data, (*skb)->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (r != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) kfree_skb(*skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) r = -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) skb_pull(*skb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) skb_trim(*skb, (*skb)->len - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) usleep_range(3000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) flush:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) r = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) usleep_range(3000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct pn544_i2c_fw_frame_response response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct i2c_client *client = phy->i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) r = i2c_master_recv(client, (char *) &response, sizeof(response));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (r != sizeof(response)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) nfc_err(&client->dev, "cannot read fw status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) usleep_range(3000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) switch (response.status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case PN544_FW_CMD_RESULT_CHUNK_OK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return response.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case PN544_FW_CMD_RESULT_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case PN544_FW_CMD_RESULT_BAD_CRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case PN544_FW_CMD_RESULT_ACCESS_DENIED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case PN544_FW_CMD_RESULT_PROTOCOL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case PN544_FW_CMD_RESULT_INVALID_PARAMETER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case PN544_FW_CMD_RESULT_INVALID_LENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -ENOKEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case PN544_FW_CMD_RESULT_MEMORY_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case PN544_FW_CMD_RESULT_COMMAND_REJECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case PN544_FW_CMD_RESULT_WRITE_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case PN544_FW_CMD_RESULT_CHUNK_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Reads an shdlc frame from the chip. This is not as straightforward as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * seems. There are cases where we could loose the frame start synchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * The frame format is len-data-crc, and corruption can occur anywhere while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * transiting on i2c bus, such that we could read an invalid len.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * In order to recover synchronization with the next frame, we must be sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * to read the real amount of data without using the len byte. We do this by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * assuming the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * - the chip will always present only one single complete frame on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * before triggering the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * - the chip will not present a new frame until we have completely read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * the previous one (or until we have handled the interrupt).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * The tricky case is when we read a corrupted len that is less than the real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * len. We must detect this here in order to determine that we need to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * the bus. This is the reason why we check the crc here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct pn544_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct sk_buff *skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!phy || irq != phy->i2c_dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) client = phy->i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_dbg(&client->dev, "IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (phy->hard_fault != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (phy->run_mode == PN544_FW_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) schedule_work(&phy->fw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) r = pn544_hci_i2c_read(phy, &skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (r == -EREMOTEIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) phy->hard_fault = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) nfc_hci_recv_frame(phy->hdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } else if ((r == -ENOMEM) || (r == -EBADMSG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) nfc_hci_recv_frame(phy->hdev, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static struct nfc_phy_ops i2c_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .write = pn544_hci_i2c_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .enable = pn544_hci_i2c_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .disable = pn544_hci_i2c_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 hw_variant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct pn544_i2c_phy *phy = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pr_info("Starting Firmware Download (%s)\n", firmware_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) strcpy(phy->firmware_name, firmware_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) phy->hw_variant = hw_variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) phy->fw_work_state = FW_WORK_STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) schedule_work(&phy->fw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pr_info("Firmware Download Complete, result=%d\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pn544_hci_i2c_disable(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) phy->fw_work_state = FW_WORK_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (phy->fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) release_firmware(phy->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) phy->fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const u8 *data, u16 datalen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 frame[PN544_FW_I2C_MAX_PAYLOAD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct pn544_i2c_fw_frame_write *framep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u16 params_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int framelen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) framep = (struct pn544_i2c_fw_frame_write *) frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) params_len = sizeof(framep->be_dest_addr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) sizeof(framep->be_datalen) + datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) framelen = params_len + sizeof(framep->cmd) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) sizeof(framep->be_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) framep->cmd = PN544_FW_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) put_unaligned_be16(params_len, &framep->be_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) framep->be_dest_addr[2] = dest_addr & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) put_unaligned_be16(datalen, &framep->be_datalen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) memcpy(framep->data, data, datalen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) r = i2c_master_send(client, frame, framelen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (r == framelen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) else if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) const u8 *data, u16 datalen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct pn544_i2c_fw_frame_check frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u16 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* calculate local crc for the data we want to check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) crc = crc_ccitt(0xffff, data, datalen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) frame.cmd = PN544_FW_CMD_CHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) put_unaligned_be16(sizeof(frame.be_start_addr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sizeof(frame.be_datalen) + sizeof(frame.be_crc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &frame.be_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* tell the chip the memory region to which our crc applies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) frame.be_start_addr[1] = (start_addr & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) frame.be_start_addr[2] = start_addr & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) put_unaligned_be16(datalen, &frame.be_datalen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * and give our local crc. Chip will calculate its own crc for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * region and compare with ours.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) put_unaligned_be16(crc, &frame.be_crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) r = i2c_master_send(client, (const char *) &frame, sizeof(frame));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (r == sizeof(frame))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) else if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) phy->fw_blob_dest_addr + phy->fw_written,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) phy->fw_blob_data + phy->fw_written,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) phy->fw_blob_size - phy->fw_written);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) phy->fw_written += r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) const u8 *data, u16 datalen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u8 buf[PN544_FW_I2C_MAX_PAYLOAD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct pn544_i2c_fw_secure_frame *chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int chunklen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) chunk = (struct pn544_i2c_fw_secure_frame *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) put_unaligned_be16(datalen, &chunk->be_datalen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) memcpy(chunk->data, data, datalen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) r = i2c_master_send(phy->i2c_dev, buf, chunklen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (r == chunklen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct pn544_i2c_fw_secure_frame *framep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (phy->fw_written == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) + PN544_FW_SECURE_FRAME_HEADER_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Only secure write command can be chunked*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) framep->cmd != PN544_FW_CMD_SECURE_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* The firmware also have other commands, we just send them directly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) r = i2c_master_send(phy->i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) (const char *) phy->fw_blob_data, phy->fw_blob_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (r == phy->fw_blob_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) else if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) phy->fw_blob_data + phy->fw_written,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) phy->fw_blob_size - phy->fw_written);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) phy->fw_written += r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* SW reset command will not trig any response from PN544 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (framep->cmd == PN544_FW_CMD_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) phy->fw_cmd_result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) schedule_work(&phy->fw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void pn544_hci_i2c_fw_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) fw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct pn544_i2c_fw_blob *blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct pn544_i2c_fw_secure_blob *secure_blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) switch (phy->fw_work_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case FW_WORK_STATE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) r = request_firmware(&phy->fw, phy->firmware_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) &phy->i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) goto exit_state_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) phy->fw_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) switch (phy->hw_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case PN544_HW_VARIANT_C2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) blob = (struct pn544_i2c_fw_blob *) phy->fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) phy->fw_blob_dest_addr = get_unaligned_be32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) &blob->be_destaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) phy->fw_blob_data = blob->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) r = pn544_hci_i2c_fw_write_chunk(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case PN544_HW_VARIANT_C3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) secure_blob = (struct pn544_i2c_fw_secure_blob *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) phy->fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) phy->fw_blob_data = secure_blob->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) phy->fw_size = phy->fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) r = pn544_hci_i2c_fw_secure_write_frame(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) r = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) exit_state_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pn544_hci_i2c_fw_work_complete(phy, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case FW_WORK_STATE_WAIT_WRITE_ANSWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) r = phy->fw_cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) goto exit_state_wait_write_answer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (phy->fw_written == phy->fw_blob_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) phy->fw_blob_dest_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) phy->fw_blob_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) phy->fw_blob_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) goto exit_state_wait_write_answer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) r = pn544_hci_i2c_fw_write_chunk(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) exit_state_wait_write_answer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pn544_hci_i2c_fw_work_complete(phy, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case FW_WORK_STATE_WAIT_CHECK_ANSWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) r = phy->fw_cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) goto exit_state_wait_check_answer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) phy->fw_blob_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (phy->fw_blob_size != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) phy->fw_blob_dest_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) get_unaligned_be32(&blob->be_destaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) phy->fw_blob_data = blob->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) phy->fw_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) r = pn544_hci_i2c_fw_write_chunk(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) exit_state_wait_check_answer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (r < 0 || phy->fw_blob_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) pn544_hci_i2c_fw_work_complete(phy, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) r = phy->fw_cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto exit_state_wait_secure_write_answer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (r == PN544_FW_CMD_RESULT_CHUNK_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) r = pn544_hci_i2c_fw_secure_write_frame(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) goto exit_state_wait_secure_write_answer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (phy->fw_written == phy->fw_blob_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) secure_blob = (struct pn544_i2c_fw_secure_blob *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) (phy->fw_blob_data + phy->fw_blob_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) phy->fw_size -= phy->fw_blob_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PN544_FW_SECURE_BLOB_HEADER_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) + PN544_FW_SECURE_FRAME_HEADER_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) phy->fw_blob_data = secure_blob->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) phy->fw_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) r = pn544_hci_i2c_fw_secure_write_frame(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) exit_state_wait_secure_write_answer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (r < 0 || phy->fw_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pn544_hci_i2c_fw_work_complete(phy, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct acpi_gpio_params enable_gpios = { 1, 0, false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const struct acpi_gpio_params firmware_gpios = { 2, 0, false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const struct acpi_gpio_mapping acpi_pn544_gpios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) { "enable-gpios", &enable_gpios, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { "firmware-gpios", &firmware_gpios, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int pn544_hci_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct pn544_i2c_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_dbg(&client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) nfc_err(&client->dev, "Need I2C_FUNC_I2C\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) phy->fw_work_state = FW_WORK_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) phy->i2c_dev = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) i2c_set_clientdata(client, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) r = devm_acpi_dev_add_driver_gpios(dev, acpi_pn544_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_dbg(dev, "Unable to add GPIO mapping table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Get EN GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (IS_ERR(phy->gpiod_en)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) nfc_err(dev, "Unable to get EN GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return PTR_ERR(phy->gpiod_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Get FW GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) phy->gpiod_fw = devm_gpiod_get(dev, "firmware", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (IS_ERR(phy->gpiod_fw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) nfc_err(dev, "Unable to get FW GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return PTR_ERR(phy->gpiod_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pn544_hci_i2c_platform_init(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) r = devm_request_threaded_irq(&client->dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pn544_hci_i2c_irq_thread_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PN544_HCI_I2C_DRIVER_NAME, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) nfc_err(&client->dev, "Unable to register IRQ handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PN544_HCI_I2C_LLC_MAX_PAYLOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) pn544_hci_i2c_fw_download, &phy->hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int pn544_hci_i2c_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct pn544_i2c_phy *phy = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dev_dbg(&client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) cancel_work_sync(&phy->fw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (phy->fw_work_state != FW_WORK_STATE_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pn544_hci_i2c_fw_work_complete(phy, -ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pn544_hci_remove(phy->hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (phy->powered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pn544_hci_i2c_disable(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const struct of_device_id of_pn544_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) { .compatible = "nxp,pn544-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) MODULE_DEVICE_TABLE(of, of_pn544_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static struct i2c_driver pn544_hci_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .name = PN544_HCI_I2C_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .of_match_table = of_match_ptr(of_pn544_i2c_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .acpi_match_table = ACPI_PTR(pn544_hci_i2c_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .probe = pn544_hci_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .id_table = pn544_hci_i2c_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .remove = pn544_hci_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) module_i2c_driver(pn544_hci_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MODULE_DESCRIPTION(DRIVER_DESC);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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