Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Marvell NFC-over-SPI driver: SPI interface related functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2015, Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This software file (the "File") is distributed by Marvell International
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Ltd. under the terms of the GNU General Public License Version 2, June 1991
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * (the "License").  You may use, redistribute and/or modify this File in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * accordance with the terms and conditions of the License, a copy of which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * is available on the worldwide web at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * this warranty disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/nfc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <net/nfc/nci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <net/nfc/nci_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "nfcmrvl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SPI_WAIT_HANDSHAKE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct nfcmrvl_spi_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct nci_spi *nci_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct completion handshake_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct nfcmrvl_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static irqreturn_t nfcmrvl_spi_int_irq_thread_fn(int irq, void *drv_data_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct nfcmrvl_spi_drv_data *drv_data = drv_data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * Special case where we are waiting for SPI_INT deassertion to start a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (test_and_clear_bit(SPI_WAIT_HANDSHAKE, &drv_data->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		complete(&drv_data->handshake_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* Normal case, SPI_INT deasserted by slave to trigger a master read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	skb = nci_spi_read(drv_data->nci_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		nfc_err(&drv_data->spi->dev, "failed to read spi packet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (nfcmrvl_nci_recv_frame(drv_data->priv, skb) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		nfc_err(&drv_data->spi->dev, "corrupted RX packet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int nfcmrvl_spi_nci_open(struct nfcmrvl_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int nfcmrvl_spi_nci_close(struct nfcmrvl_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int nfcmrvl_spi_nci_send(struct nfcmrvl_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct nfcmrvl_spi_drv_data *drv_data = priv->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* Reinit completion for slave handshake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	reinit_completion(&drv_data->handshake_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	set_bit(SPI_WAIT_HANDSHAKE, &drv_data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * Append a dummy byte at the end of SPI frame. This is due to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * specific DMA implementation in the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	skb_put(skb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* Send the SPI packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	err = nci_spi_send(drv_data->nci_spi, &drv_data->handshake_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			   skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		nfc_err(priv->dev, "spi_send failed %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void nfcmrvl_spi_nci_update_config(struct nfcmrvl_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 					  const void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct nfcmrvl_spi_drv_data *drv_data = priv->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	const struct nfcmrvl_fw_spi_config *config = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	drv_data->nci_spi->xfer_speed_hz = config->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct nfcmrvl_if_ops spi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.nci_open = nfcmrvl_spi_nci_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.nci_close = nfcmrvl_spi_nci_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.nci_send = nfcmrvl_spi_nci_send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.nci_update_config = nfcmrvl_spi_nci_update_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int nfcmrvl_spi_parse_dt(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				struct nfcmrvl_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ret = nfcmrvl_parse_dt(node, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		pr_err("Failed to get generic entries\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ret = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		pr_err("Unable to get irq, error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	pdata->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int nfcmrvl_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct nfcmrvl_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct nfcmrvl_platform_data config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct nfcmrvl_spi_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	drv_data = devm_kzalloc(&spi->dev, sizeof(*drv_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (!drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	drv_data->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	drv_data->priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	spi_set_drvdata(spi, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (!pdata && spi->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		if (nfcmrvl_spi_parse_dt(spi->dev.of_node, &config) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			pdata = &config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ret = devm_request_threaded_irq(&drv_data->spi->dev, pdata->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 					NULL, nfcmrvl_spi_int_irq_thread_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					"nfcmrvl_spi_int", drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		nfc_err(&drv_data->spi->dev, "Unable to register IRQ handler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	drv_data->priv = nfcmrvl_nci_register_dev(NFCMRVL_PHY_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 						  drv_data, &spi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 						  &drv_data->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 						  pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (IS_ERR(drv_data->priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return PTR_ERR(drv_data->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	drv_data->priv->support_fw_dnld = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	drv_data->nci_spi = nci_spi_allocate_spi(drv_data->spi, 0, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 						 drv_data->priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Init completion for slave handshake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	init_completion(&drv_data->handshake_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int nfcmrvl_spi_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct nfcmrvl_spi_drv_data *drv_data = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	nfcmrvl_nci_unregister_dev(drv_data->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct of_device_id of_nfcmrvl_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ .compatible = "marvell,nfc-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_DEVICE_TABLE(of, of_nfcmrvl_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct spi_device_id nfcmrvl_spi_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ "nfcmrvl_spi", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_DEVICE_TABLE(spi, nfcmrvl_spi_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct spi_driver nfcmrvl_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.probe		= nfcmrvl_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.remove		= nfcmrvl_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.id_table	= nfcmrvl_spi_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.name		= "nfcmrvl_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.of_match_table	= of_match_ptr(of_nfcmrvl_spi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) module_spi_driver(nfcmrvl_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_AUTHOR("Marvell International Ltd.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_DESCRIPTION("Marvell NFC-over-SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_LICENSE("GPL v2");