^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __WL3501_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __WL3501_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/ieee80211.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* define for WLA 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define WL3501_BLKSZ 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * ID for input Signals of DRIVER block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * bit[7-5] is block ID: 000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * bit[4-0] is signal ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum wl3501_signals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) WL3501_SIG_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) WL3501_SIG_MD_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) WL3501_SIG_MD_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) WL3501_SIG_ASSOC_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) WL3501_SIG_ASSOC_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) WL3501_SIG_AUTH_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) WL3501_SIG_AUTH_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) WL3501_SIG_DEAUTH_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) WL3501_SIG_DEAUTH_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) WL3501_SIG_DISASSOC_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) WL3501_SIG_DISASSOC_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) WL3501_SIG_GET_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) WL3501_SIG_JOIN_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) WL3501_SIG_PWR_MGMT_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) WL3501_SIG_REASSOC_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) WL3501_SIG_REASSOC_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) WL3501_SIG_SCAN_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) WL3501_SIG_SET_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) WL3501_SIG_START_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) WL3501_SIG_RESYNC_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) WL3501_SIG_SITE_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) WL3501_SIG_SAVE_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) WL3501_SIG_RFTEST_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * ID for input Signals of MLME block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * bit[7-5] is block ID: 010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * bit[4-0] is signal ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) WL3501_SIG_ASSOC_REQ = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) WL3501_SIG_AUTH_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) WL3501_SIG_DEAUTH_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) WL3501_SIG_DISASSOC_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) WL3501_SIG_GET_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) WL3501_SIG_JOIN_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) WL3501_SIG_PWR_MGMT_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) WL3501_SIG_REASSOC_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) WL3501_SIG_SCAN_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) WL3501_SIG_SET_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) WL3501_SIG_START_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) WL3501_SIG_MD_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) WL3501_SIG_RESYNC_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) WL3501_SIG_SITE_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) WL3501_SIG_SAVE_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) WL3501_SIG_RF_TEST_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) WL3501_SIG_MM_CONFIRM = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) WL3501_SIG_MM_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum wl3501_mib_attribs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) WL3501_MIB_ATTR_STATION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) WL3501_MIB_ATTR_AUTH_ALGORITHMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) WL3501_MIB_ATTR_AUTH_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) WL3501_MIB_ATTR_MEDIUM_OCCUPANCY_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) WL3501_MIB_ATTR_CF_POLLABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) WL3501_MIB_ATTR_CFP_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) WL3501_MIB_ATTR_CFPMAX_DURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) WL3501_MIB_ATTR_AUTH_RESP_TMOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) WL3501_MIB_ATTR_RX_DTIMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) WL3501_MIB_ATTR_PRIV_OPT_IMPLEMENTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) WL3501_MIB_ATTR_PRIV_INVOKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) WL3501_MIB_ATTR_WEP_DEFAULT_KEYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) WL3501_MIB_ATTR_WEP_DEFAULT_KEY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) WL3501_MIB_ATTR_WEP_KEY_MAPPINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) WL3501_MIB_ATTR_WEP_KEY_MAPPINGS_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) WL3501_MIB_ATTR_EXCLUDE_UNENCRYPTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) WL3501_MIB_ATTR_WEP_ICV_ERROR_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) WL3501_MIB_ATTR_WEP_UNDECRYPTABLE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) WL3501_MIB_ATTR_WEP_EXCLUDED_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) WL3501_MIB_ATTR_MAC_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) WL3501_MIB_ATTR_GROUP_ADDRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) WL3501_MIB_ATTR_RTS_THRESHOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) WL3501_MIB_ATTR_SHORT_RETRY_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) WL3501_MIB_ATTR_LONG_RETRY_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) WL3501_MIB_ATTR_FRAG_THRESHOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) WL3501_MIB_ATTR_MAX_TX_MSDU_LIFETIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) WL3501_MIB_ATTR_MAX_RX_LIFETIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) WL3501_MIB_ATTR_MANUFACTURER_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) WL3501_MIB_ATTR_PRODUCT_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) WL3501_MIB_ATTR_TX_FRAG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) WL3501_MIB_ATTR_MULTICAST_TX_FRAME_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) WL3501_MIB_ATTR_FAILED_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) WL3501_MIB_ATTR_RX_FRAG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) WL3501_MIB_ATTR_MULTICAST_RX_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) WL3501_MIB_ATTR_FCS_ERROR_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) WL3501_MIB_ATTR_RETRY_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) WL3501_MIB_ATTR_MULTIPLE_RETRY_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) WL3501_MIB_ATTR_RTS_SUCCESS_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) WL3501_MIB_ATTR_RTS_FAILURE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) WL3501_MIB_ATTR_ACK_FAILURE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) WL3501_MIB_ATTR_FRAME_DUPLICATE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) WL3501_MIB_ATTR_PHY_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) WL3501_MIB_ATTR_REG_DOMAINS_SUPPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) WL3501_MIB_ATTR_CURRENT_REG_DOMAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) WL3501_MIB_ATTR_SLOT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) WL3501_MIB_ATTR_CCA_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) WL3501_MIB_ATTR_RX_TX_TURNAROUND_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) WL3501_MIB_ATTR_TX_PLCP_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) WL3501_MIB_ATTR_RX_TX_SWITCH_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) WL3501_MIB_ATTR_TX_RAMP_ON_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) WL3501_MIB_ATTR_TX_RF_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) WL3501_MIB_ATTR_SIFS_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) WL3501_MIB_ATTR_RX_RF_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) WL3501_MIB_ATTR_RX_PLCP_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) WL3501_MIB_ATTR_MAC_PROCESSING_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) WL3501_MIB_ATTR_TX_RAMP_OFF_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) WL3501_MIB_ATTR_PREAMBLE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) WL3501_MIB_ATTR_PLCP_HEADER_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) WL3501_MIB_ATTR_MPDU_DURATION_FACTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) WL3501_MIB_ATTR_AIR_PROPAGATION_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) WL3501_MIB_ATTR_TEMP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) WL3501_MIB_ATTR_CW_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) WL3501_MIB_ATTR_CW_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) WL3501_MIB_ATTR_SUPPORT_DATA_RATES_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) WL3501_MIB_ATTR_SUPPORT_DATA_RATES_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) WL3501_MIB_ATTR_MPDU_MAX_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) WL3501_MIB_ATTR_SUPPORT_TX_ANTENNAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) WL3501_MIB_ATTR_CURRENT_TX_ANTENNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) WL3501_MIB_ATTR_SUPPORT_RX_ANTENNAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) WL3501_MIB_ATTR_DIVERSITY_SUPPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) WL3501_MIB_ATTR_DIVERSITY_SELECTION_RS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) WL3501_MIB_ATTR_NR_SUPPORTED_PWR_LEVELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) WL3501_MIB_ATTR_TX_PWR_LEVEL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) WL3501_MIB_ATTR_TX_PWR_LEVEL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) WL3501_MIB_ATTR_TX_PWR_LEVEL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) WL3501_MIB_ATTR_TX_PWR_LEVEL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) WL3501_MIB_ATTR_TX_PWR_LEVEL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) WL3501_MIB_ATTR_TX_PWR_LEVEL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) WL3501_MIB_ATTR_TX_PWR_LEVEL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) WL3501_MIB_ATTR_TX_PWR_LEVEL8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) WL3501_MIB_ATTR_CURRENT_TX_PWR_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) WL3501_MIB_ATTR_CURRENT_CHAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) WL3501_MIB_ATTR_CCA_MODE_SUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) WL3501_MIB_ATTR_CURRENT_CCA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) WL3501_MIB_ATTR_ED_THRESHOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) WL3501_MIB_ATTR_SINTHESIZER_LOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) WL3501_MIB_ATTR_CURRENT_PWR_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) WL3501_MIB_ATTR_DOZE_TURNON_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) WL3501_MIB_ATTR_RCR33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) WL3501_MIB_ATTR_DEFAULT_CHAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) WL3501_MIB_ATTR_SSID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) WL3501_MIB_ATTR_PWR_MGMT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) WL3501_MIB_ATTR_NET_CAPABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) WL3501_MIB_ATTR_ROUTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum wl3501_net_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) WL3501_NET_TYPE_INFRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) WL3501_NET_TYPE_ADHOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) WL3501_NET_TYPE_ANY_BSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) enum wl3501_scan_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) WL3501_SCAN_TYPE_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) WL3501_SCAN_TYPE_PASSIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) enum wl3501_tx_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) WL3501_TX_RESULT_SUCCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) WL3501_TX_RESULT_NO_BSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) WL3501_TX_RESULT_RETRY_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) enum wl3501_sys_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) WL3501_SYS_TYPE_OPEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) WL3501_SYS_TYPE_SHARE_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) enum wl3501_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) WL3501_STATUS_SUCCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) WL3501_STATUS_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) WL3501_STATUS_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) WL3501_STATUS_REFUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) WL3501_STATUS_MANY_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) WL3501_STATUS_ALREADY_BSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define WL3501_MGMT_CAPABILITY_ESS 0x0001 /* see 802.11 p.58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define WL3501_MGMT_CAPABILITY_IBSS 0x0002 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define WL3501_MGMT_CAPABILITY_CF_POLLABLE 0x0004 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define WL3501_MGMT_CAPABILITY_CF_POLL_REQUEST 0x0008 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define WL3501_MGMT_CAPABILITY_PRIVACY 0x0010 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IW_REG_DOMAIN_FCC 0x10 /* Channel 1 to 11 USA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IW_REG_DOMAIN_DOC 0x20 /* Channel 1 to 11 Canada */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IW_REG_DOMAIN_ETSI 0x30 /* Channel 1 to 13 Europe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IW_REG_DOMAIN_SPAIN 0x31 /* Channel 10 to 11 Spain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IW_REG_DOMAIN_FRANCE 0x32 /* Channel 10 to 13 France */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IW_REG_DOMAIN_MKK 0x40 /* Channel 14 Japan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IW_REG_DOMAIN_MKK1 0x41 /* Channel 1-14 Japan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IW_REG_DOMAIN_ISRAEL 0x50 /* Channel 3 - 9 Israel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IW_MGMT_RATE_LABEL_MANDATORY 128 /* MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum iw_mgmt_rate_labels {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) IW_MGMT_RATE_LABEL_1MBIT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IW_MGMT_RATE_LABEL_2MBIT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IW_MGMT_RATE_LABEL_5_5MBIT = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IW_MGMT_RATE_LABEL_11MBIT = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum iw_mgmt_info_element_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IW_MGMT_INFO_ELEMENT_SSID, /* Service Set Identity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IW_MGMT_INFO_ELEMENT_SUPPORTED_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) IW_MGMT_INFO_ELEMENT_FH_PARAMETER_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IW_MGMT_INFO_ELEMENT_DS_PARAMETER_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) IW_MGMT_INFO_ELEMENT_CS_PARAMETER_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IW_MGMT_INFO_ELEMENT_CS_TIM, /* Traffic Information Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) IW_MGMT_INFO_ELEMENT_IBSS_PARAMETER_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* 7-15: Reserved, unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IW_MGMT_INFO_ELEMENT_CHALLENGE_TEXT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* 17-31 Reserved for challenge text extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* 32-255 Reserved, unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct iw_mgmt_info_element {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 id; /* one of enum iw_mgmt_info_element_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) but sizeof(enum) > sizeof(u8) :-( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct iw_mgmt_essid_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct iw_mgmt_info_element el;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 essid[IW_ESSID_MAX_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * According to 802.11 Wireless Netowors, the definitive guide - O'Reilly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Pg 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IW_DATA_RATE_MAX_LABELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct iw_mgmt_data_rset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct iw_mgmt_info_element el;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 data_rate_labels[IW_DATA_RATE_MAX_LABELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct iw_mgmt_ds_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct iw_mgmt_info_element el;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct iw_mgmt_cf_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct iw_mgmt_info_element el;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 cfp_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 cfp_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u16 cfp_max_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u16 cfp_dur_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct iw_mgmt_ibss_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct iw_mgmt_info_element el;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u16 atim_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct wl3501_tx_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u16 tx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 sync[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u16 sfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 service;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u16 crc16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u16 frame_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u16 duration_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 addr1[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 addr2[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 addr3[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u16 seq_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 addr4[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct wl3501_rx_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u16 rx_next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u16 rc_next_frame_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 rx_blk_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 rx_next_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 rx_next_frame1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) char time[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 service;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u16 crc16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u16 frame_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u16 duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 addr1[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 addr2[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 addr3[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u16 seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 addr4[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct wl3501_start_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 bss_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u16 beacon_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u16 dtim_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u16 probe_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u16 cap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct iw_mgmt_essid_pset ssid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct iw_mgmt_data_rset bss_basic_rset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct iw_mgmt_data_rset operational_rset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct iw_mgmt_cf_pset cf_pset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct iw_mgmt_ds_pset ds_pset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct iw_mgmt_ibss_pset ibss_pset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct wl3501_assoc_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 cap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u16 listen_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct wl3501_assoc_confirm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct wl3501_assoc_ind {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct wl3501_auth_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct wl3501_auth_confirm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct wl3501_get_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u16 mib_attrib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct wl3501_get_confirm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u16 mib_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u16 mib_attrib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 mib_value[100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct wl3501_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u16 beacon_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u16 dtim_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u16 cap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 bss_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 bssid[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct iw_mgmt_essid_pset ssid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct iw_mgmt_ds_pset ds_pset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct iw_mgmt_cf_pset cf_pset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct iw_mgmt_ibss_pset ibss_pset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct iw_mgmt_data_rset bss_basic_rset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct wl3501_join_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct iw_mgmt_data_rset operational_rset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u16 probe_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 timestamp[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u8 local_time[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct wl3501_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct wl3501_join_confirm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct wl3501_pwr_mgmt_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 pwr_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u8 wake_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 receive_dtims;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct wl3501_pwr_mgmt_confirm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct wl3501_scan_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 bss_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u16 probe_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u16 min_chan_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u16 max_chan_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 chan_list[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u8 bssid[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct iw_mgmt_essid_pset ssid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) enum wl3501_scan_type scan_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct wl3501_scan_confirm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) char timestamp[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) char localtime[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct wl3501_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u8 rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct wl3501_start_confirm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct wl3501_md_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u8 routing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 service_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u8 daddr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 saddr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) } addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct wl3501_md_ind {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 routing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 reception;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 service_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u8 daddr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 saddr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct wl3501_md_confirm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 service_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct wl3501_resync_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u16 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 sig_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Definitions for supporting clone adapters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* System Interface Registers (SIR space) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define WL3501_NIC_GCR ((u8)0x00) /* SIR0 - General Conf Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define WL3501_NIC_BSS ((u8)0x01) /* SIR1 - Bank Switching Select Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define WL3501_NIC_LMAL ((u8)0x02) /* SIR2 - Local Mem addr Reg [7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define WL3501_NIC_LMAH ((u8)0x03) /* SIR3 - Local Mem addr Reg [14:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define WL3501_NIC_IODPA ((u8)0x04) /* SIR4 - I/O Data Port A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define WL3501_NIC_IODPB ((u8)0x05) /* SIR5 - I/O Data Port B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define WL3501_NIC_IODPC ((u8)0x06) /* SIR6 - I/O Data Port C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define WL3501_NIC_IODPD ((u8)0x07) /* SIR7 - I/O Data Port D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Bits in GCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define WL3501_GCR_SWRESET ((u8)0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define WL3501_GCR_CORESET ((u8)0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define WL3501_GCR_DISPWDN ((u8)0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define WL3501_GCR_ECWAIT ((u8)0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define WL3501_GCR_ECINT ((u8)0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define WL3501_GCR_INT2EC ((u8)0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define WL3501_GCR_ENECINT ((u8)0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define WL3501_GCR_DAM ((u8)0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Bits in BSS (Bank Switching Select Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define WL3501_BSS_FPAGE0 ((u8)0x20) /* Flash memory page0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define WL3501_BSS_FPAGE1 ((u8)0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define WL3501_BSS_FPAGE2 ((u8)0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define WL3501_BSS_FPAGE3 ((u8)0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define WL3501_BSS_SPAGE0 ((u8)0x00) /* SRAM page0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define WL3501_BSS_SPAGE1 ((u8)0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define WL3501_BSS_SPAGE2 ((u8)0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define WL3501_BSS_SPAGE3 ((u8)0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Define Driver Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Refer IEEE 802.11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Tx packet header, include PLCP and MPDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Tx PLCP Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct wl3501_80211_tx_plcp_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u8 sync[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u16 sfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u8 service;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u16 crc16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct wl3501_80211_tx_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct wl3501_80211_tx_plcp_hdr pclp_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct ieee80211_hdr mac_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) Reserve the beginning Tx space for descriptor use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) TxBlockOffset --> *----*----*----*----* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) (TxFreeDesc) | 0 | 1 | 2 | 3 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) | 4 | 5 | 6 | 7 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) | 8 | 9 | 10 | 11 | TX_DESC * 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) | 12 | 13 | 14 | 15 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) | 16 | 17 | 18 | 19 | /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) TxBufferBegin --> *----*----*----*----* /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) (TxBufferHead) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) (TxBufferTail) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) | Send Buffer |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *-------------------*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) TxBufferEnd -------------------------/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct wl3501_card {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u8 mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct wl3501_get_confirm sig_get_confirm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct wl3501_pwr_mgmt_confirm sig_pwr_mgmt_confirm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u16 tx_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u16 tx_buffer_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u16 tx_buffer_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u16 tx_buffer_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u16 esbq_req_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u16 esbq_req_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 esbq_req_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u16 esbq_req_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u16 esbq_confirm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 esbq_confirm_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u16 esbq_confirm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct iw_mgmt_essid_pset essid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct iw_mgmt_essid_pset keep_essid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 bssid[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int net_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) char nick[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) char card_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) char firmware_date[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u8 chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u8 cap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u16 start_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u16 bss_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u16 join_sta_bss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u8 adhoc_times;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u8 reg_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 version[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct wl3501_scan_confirm bss_set[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct iw_statistics wstats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct iw_spy_data spy_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct iw_public_data wireless_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct pcmcia_device *p_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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