^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2008-2009 Atheros Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission to use, copy, modify, and/or distribute this software for any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * purpose with or without fee is hereby granted, provided that the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * copyright notice and this permission notice appear in all copies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef ATH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ATH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/if_ether.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <net/mac80211.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The key cache is used for h/w cipher state and also for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * tracking station state such as the current tx antenna.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * We also setup a mapping table between key cache slot indices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * and station state to short-circuit node lookups on rx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Different parts have different size key caches. We handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * up to ATH_KEYMAX entries (could dynamically allocate state).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ATH_KEYMAX 128 /* max key cache size we handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ath_ani {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) bool caldone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int longcal_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int shortcal_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int resetcal_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int checkani_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct ath_cycle_counters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 rx_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 rx_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 tx_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) enum ath_device_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ATH_HW_UNAVAILABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ATH_HW_INITIALIZED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum ath_op_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ATH_OP_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ATH_OP_BEACONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ATH_OP_ANI_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ATH_OP_PRIM_STA_VIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ATH_OP_HW_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ATH_OP_SCANNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ATH_OP_MULTI_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ATH_OP_WOW_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum ath_bus_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ATH_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ATH_AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ATH_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct reg_dmn_pair_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 reg_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u16 reg_5ghz_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 reg_2ghz_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct ath_regulatory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) char alpha2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum nl80211_dfs_regions region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 country_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 max_power_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 current_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int16_t power_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct reg_dmn_pair_mapping *regpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum ath_crypt_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ath_keyval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 kv_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 kv_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 kv_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 kv_val[16]; /* TK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 kv_mic[8]; /* Michael MIC key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * supports both MIC keys in the same key cache entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * in that case, kv_mic is the RX key) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum ath_cipher {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ATH_CIPHER_WEP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ATH_CIPHER_AES_OCB = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ATH_CIPHER_AES_CCM = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ATH_CIPHER_CKIP = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ATH_CIPHER_TKIP = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ATH_CIPHER_CLR = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ATH_CIPHER_MIC = 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * struct ath_ops - Register read/write operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @read: Register read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @multi_read: Multiple register read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @write: Register write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @enable_write_buffer: Enable multiple register writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @write_flush: flush buffered register writes and disable buffering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ath_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int (*read)(void *, u32 reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void (*write)(void *, u32 val, u32 reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void (*enable_write_buffer)(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void (*write_flush) (void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void (*enable_rmw_buffer)(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void (*rmw_flush) (void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ath_common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ath_bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ath_ps_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void (*wakeup)(struct ath_common *common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void (*restore)(struct ath_common *common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ath_common {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void *ah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct ieee80211_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int debug_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum ath_device_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long op_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ath_ani ani;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 cachelsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u16 curaid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 macaddr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 curbssid[ETH_ALEN] __aligned(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 bssidmask[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 rx_bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 keymax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DECLARE_BITMAP(keymap, ATH_KEYMAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) enum ath_crypt_caps crypt_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int clockrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) spinlock_t cc_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ath_cycle_counters cc_ani;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct ath_cycle_counters cc_survey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct ath_regulatory regulatory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct ath_regulatory reg_world_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct ath_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const struct ath_bus_ops *bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const struct ath_ps_ops *ps_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool btcoex_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bool disable_ani;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bool bt_ant_diversity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int last_rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return common->ps_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) gfp_t gfp_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void ath_hw_setbssidmask(struct ath_common *common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void ath_key_delete(struct ath_common *common, u8 hw_key_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ath_key_config(struct ath_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct ieee80211_vif *vif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct ieee80211_sta *sta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct ieee80211_key_conf *key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bool ath_hw_keyreset(struct ath_common *common, u16 entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) bool ath_hw_keysetmac(struct ath_common *common, u16 entry, const u8 *mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void ath_hw_cycle_counters_update(struct ath_common *common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int32_t ath_hw_get_listen_time(struct ath_common *common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __printf(3, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void ath_printk(const char *level, const struct ath_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ath_emerg(common, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ath_alert(common, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ath_crit(common, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ath_err(common, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ath_warn(common, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ath_notice(common, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ath_info(common, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * enum ath_debug_level - atheros wireless debug level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @ATH_DBG_RESET: reset processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @ATH_DBG_QUEUE: hardware queue management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @ATH_DBG_EEPROM: eeprom processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @ATH_DBG_CALIBRATE: periodic calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @ATH_DBG_INTERRUPT: interrupt processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @ATH_DBG_REGULATORY: regulatory processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @ATH_DBG_ANI: adaptive noise immunitive processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @ATH_DBG_XMIT: basic xmit operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @ATH_DBG_BEACON: beacon handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @ATH_DBG_CONFIG: configuration of the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @ATH_DBG_PS: power save processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @ATH_DBG_HWTIMER: hardware timer handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @ATH_DBG_BTCOEX: bluetooth coexistance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @ATH_DBG_BSTUCK: stuck beacons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * used exclusively for WLAN-BT coexistence starting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * AR9462.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @ATH_DBG_DFS: radar datection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @ATH_DBG_WOW: Wake on Wireless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @ATH_DBG_DYNACK: dynack handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @ATH_DBG_SPECTRAL_SCAN: FFT spectral scan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @ATH_DBG_ANY: enable all debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * The debug level is used to control the amount and type of debugging output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * we want to see. Each driver has its own method for enabling debugging and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * modifying debug level states -- but this is typically done through a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * module parameter 'debug' along with a respective 'debug' debugfs file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) enum ATH_DEBUG {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ATH_DBG_RESET = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ATH_DBG_QUEUE = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ATH_DBG_EEPROM = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ATH_DBG_CALIBRATE = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ATH_DBG_INTERRUPT = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ATH_DBG_REGULATORY = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ATH_DBG_ANI = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ATH_DBG_XMIT = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ATH_DBG_BEACON = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ATH_DBG_CONFIG = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ATH_DBG_FATAL = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ATH_DBG_PS = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ATH_DBG_BTCOEX = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ATH_DBG_WMI = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ATH_DBG_BSTUCK = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ATH_DBG_MCI = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ATH_DBG_DFS = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ATH_DBG_WOW = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ATH_DBG_CHAN_CTX = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ATH_DBG_DYNACK = 0x00080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ATH_DBG_SPECTRAL_SCAN = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ATH_DBG_ANY = 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ATH_DBG_MAX_LEN 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifdef CONFIG_ATH_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ath_dbg(common, dbg_mask, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline __attribute__ ((format (printf, 3, 4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ath_dbg(common, dbg_mask, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ATH_DBG_WARN(foo, arg...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ATH_DBG_WARN_ON_ONCE(foo) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int __ret_warn_once = !!(foo); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unlikely(__ret_warn_once); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif /* CONFIG_ATH_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /** Returns string describing opmode, or NULL if unknown mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #ifdef CONFIG_ATH_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) const char *ath_opmode_to_string(enum nl80211_iftype opmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return "UNKNOWN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) extern const char *ath_bus_type_strings[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static inline const char *ath_bus_type_to_string(enum ath_bus_type bustype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return ath_bus_type_strings[bustype];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #endif /* ATH_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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