^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef ADM8211_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define ADM8211_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* ADM8211 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* CR32 (SIG) signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ADM8211_SIG1 0x82011317 /* ADM8211A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ADM8211_SIG2 0x82111317 /* ADM8211B/ADM8211C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ADM8211_CSR_READ(r) ioread32(&priv->map->r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ADM8211_CSR_WRITE(r, val) iowrite32((val), &priv->map->r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* CSR (Host Control and Status Registers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct adm8211_csr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __le32 PAR; /* 0x00 CSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) __le32 FRCTL; /* 0x04 CSR0A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) __le32 TDR; /* 0x08 CSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) __le32 WTDP; /* 0x0C CSR1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __le32 RDR; /* 0x10 CSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) __le32 WRDP; /* 0x14 CSR2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) __le32 RDB; /* 0x18 CSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) __le32 TDBH; /* 0x1C CSR3A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) __le32 TDBD; /* 0x20 CSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __le32 TDBP; /* 0x24 CSR4A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __le32 STSR; /* 0x28 CSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __le32 TDBB; /* 0x2C CSR5A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __le32 NAR; /* 0x30 CSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __le32 CSR6A; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __le32 IER; /* 0x38 CSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __le32 TKIPSCEP; /* 0x3C CSR7A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __le32 LPC; /* 0x40 CSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) __le32 CSR_TEST1; /* 0x44 CSR8A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __le32 SPR; /* 0x48 CSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) __le32 CSR_TEST0; /* 0x4C CSR9A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __le32 WCSR; /* 0x50 CSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __le32 WPDR; /* 0x54 CSR10A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __le32 GPTMR; /* 0x58 CSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __le32 GPIO; /* 0x5C CSR11A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __le32 BBPCTL; /* 0x60 CSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __le32 SYNCTL; /* 0x64 CSR12A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __le32 PLCPHD; /* 0x68 CSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __le32 MMIWA; /* 0x6C CSR13A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __le32 MMIRD0; /* 0x70 CSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __le32 MMIRD1; /* 0x74 CSR14A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __le32 TXBR; /* 0x78 CSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __le32 SYNDATA; /* 0x7C CSR15A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __le32 ALCS; /* 0x80 CSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __le32 TOFS2; /* 0x84 CSR17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __le32 CMDR; /* 0x88 CSR18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __le32 PCIC; /* 0x8C CSR19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __le32 PMCSR; /* 0x90 CSR20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __le32 PAR0; /* 0x94 CSR21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __le32 PAR1; /* 0x98 CSR22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __le32 MAR0; /* 0x9C CSR23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __le32 MAR1; /* 0xA0 CSR24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __le32 ATIMDA0; /* 0xA4 CSR25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __le32 ABDA1; /* 0xA8 CSR26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __le32 BSSID0; /* 0xAC CSR27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __le32 TXLMT; /* 0xB0 CSR28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __le32 MIBCNT; /* 0xB4 CSR29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __le32 BCNT; /* 0xB8 CSR30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __le32 TSFTH; /* 0xBC CSR31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __le32 TSC; /* 0xC0 CSR32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __le32 SYNRF; /* 0xC4 CSR33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __le32 BPLI; /* 0xC8 CSR34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __le32 CAP0; /* 0xCC CSR35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __le32 CAP1; /* 0xD0 CSR36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __le32 RMD; /* 0xD4 CSR37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __le32 CFPP; /* 0xD8 CSR38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __le32 TOFS0; /* 0xDC CSR39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __le32 TOFS1; /* 0xE0 CSR40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __le32 IFST; /* 0xE4 CSR41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __le32 RSPT; /* 0xE8 CSR42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __le32 TSFTL; /* 0xEC CSR43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __le32 WEPCTL; /* 0xF0 CSR44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __le32 WESK; /* 0xF4 CSR45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __le32 WEPCNT; /* 0xF8 CSR46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __le32 MACTEST; /* 0xFC CSR47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __le32 FER; /* 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __le32 FEMR; /* 0x104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __le32 FPSR; /* 0x108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __le32 FFER; /* 0x10C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* CSR0 - PAR (PCI Address Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ADM8211_PAR_MWIE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ADM8211_PAR_MRLE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ADM8211_PAR_MRME (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADM8211_PAR_RAP ((1 << 18) | (1 << 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ADM8211_PAR_CAL ((1 << 15) | (1 << 14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ADM8211_PAR_PBL 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADM8211_PAR_BLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ADM8211_PAR_DSL 0x0000007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ADM8211_PAR_BAR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADM8211_PAR_SWR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* CSR1 - FRCTL (Frame Control Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ADM8211_FRCTL_PWRMGT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ADM8211_FRCTL_MAXPSP (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ADM8211_FRCTL_DRVPRSP (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ADM8211_FRCTL_DRVBCON (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ADM8211_FRCTL_AID 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ADM8211_FRCTL_AID_ON 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* CSR5 - STSR (Status Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ADM8211_STSR_PCF (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ADM8211_STSR_BCNTC (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ADM8211_STSR_GPINT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ADM8211_STSR_LinkOff (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ADM8211_STSR_ATIMTC (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ADM8211_STSR_TSFTF (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADM8211_STSR_TSCZ (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ADM8211_STSR_LinkOn (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ADM8211_STSR_SQL (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ADM8211_STSR_WEPTD (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ADM8211_STSR_ATIME (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ADM8211_STSR_TBTT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ADM8211_STSR_NISS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ADM8211_STSR_AISS (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ADM8211_STSR_TEIS (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ADM8211_STSR_FBE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ADM8211_STSR_REIS (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ADM8211_STSR_GPTT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ADM8211_STSR_RPS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ADM8211_STSR_RDU (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ADM8211_STSR_RCI (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ADM8211_STSR_TUF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ADM8211_STSR_TRT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ADM8211_STSR_TLT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ADM8211_STSR_TDU (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ADM8211_STSR_TPS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ADM8211_STSR_TCI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* CSR6 - NAR (Network Access Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ADM8211_NAR_TXCF (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ADM8211_NAR_HF (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ADM8211_NAR_UTR (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ADM8211_NAR_SQ (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ADM8211_NAR_CFP (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ADM8211_NAR_SF (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ADM8211_NAR_TR ((1 << 15) | (1 << 14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ADM8211_NAR_ST (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ADM8211_NAR_OM ((1 << 11) | (1 << 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ADM8211_NAR_MM (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ADM8211_NAR_PR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ADM8211_NAR_EA (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ADM8211_NAR_PB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ADM8211_NAR_STPDMA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ADM8211_NAR_SR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ADM8211_NAR_CTX (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ADM8211_IDLE() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ADM8211_CSR_WRITE(NAR, priv->nar & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ~(ADM8211_NAR_SR | ADM8211_NAR_ST));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ADM8211_CSR_READ(NAR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) msleep(20); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ADM8211_IDLE_RX() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (priv->nar & ADM8211_NAR_SR) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ADM8211_CSR_WRITE(NAR, priv->nar & ~ADM8211_NAR_SR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ADM8211_CSR_READ(NAR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mdelay(20); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ADM8211_RESTORE() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ADM8211_CSR_WRITE(NAR, priv->nar); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* CSR7 - IER (Interrupt Enable Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ADM8211_IER_PCFIE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ADM8211_IER_BCNTCIE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ADM8211_IER_GPIE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ADM8211_IER_LinkOffIE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ADM8211_IER_ATIMTCIE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ADM8211_IER_TSFTFIE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ADM8211_IER_TSCZE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ADM8211_IER_LinkOnIE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ADM8211_IER_SQLIE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ADM8211_IER_WEPIE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ADM8211_IER_ATIMEIE (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ADM8211_IER_TBTTIE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ADM8211_IER_NIE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ADM8211_IER_AIE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ADM8211_IER_TEIE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ADM8211_IER_FBEIE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ADM8211_IER_REIE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ADM8211_IER_GPTIE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ADM8211_IER_RSIE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ADM8211_IER_RUIE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ADM8211_IER_RCIE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ADM8211_IER_TUIE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ADM8211_IER_TRTIE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ADM8211_IER_TLTTIE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ADM8211_IER_TDUIE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ADM8211_IER_TPSIE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ADM8211_IER_TCIE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* CSR9 - SPR (Serial Port Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ADM8211_SPR_SRS (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ADM8211_SPR_SDO (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ADM8211_SPR_SDI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ADM8211_SPR_SCLK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ADM8211_SPR_SCS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* CSR9A - CSR_TEST0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ADM8211_CSR_TEST0_EPNE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ADM8211_CSR_TEST0_EPSNM (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ADM8211_CSR_TEST0_EPTYP (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ADM8211_CSR_TEST0_EPRLD (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* CSR10 - WCSR (Wake-up Control/Status Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ADM8211_WCSR_CRCT (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ADM8211_WCSR_TSFTWE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ADM8211_WCSR_TIMWE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ADM8211_WCSR_ATIMWE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ADM8211_WCSR_KEYWE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ADM8211_WCSR_MPRE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ADM8211_WCSR_LSOE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ADM8211_WCSR_KEYUP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ADM8211_WCSR_TSFTW (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ADM8211_WCSR_TIMW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ADM8211_WCSR_ATIMW (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ADM8211_WCSR_MPR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ADM8211_WCSR_LSO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* CSR11A - GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ADM8211_CSR_GPIO_EN5 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ADM8211_CSR_GPIO_EN4 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ADM8211_CSR_GPIO_EN3 (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ADM8211_CSR_GPIO_EN2 (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ADM8211_CSR_GPIO_EN1 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ADM8211_CSR_GPIO_EN0 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ADM8211_CSR_GPIO_O5 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ADM8211_CSR_GPIO_O4 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ADM8211_CSR_GPIO_O3 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ADM8211_CSR_GPIO_O2 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ADM8211_CSR_GPIO_O1 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ADM8211_CSR_GPIO_O0 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ADM8211_CSR_GPIO_IN 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* CSR12 - BBPCTL (BBP Control port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ADM8211_BBPCTL_MMISEL (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ADM8211_BBPCTL_SPICADD (0x7F << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ADM8211_BBPCTL_RF3000 (0x20 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ADM8211_BBPCTL_TXCE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ADM8211_BBPCTL_RXCE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ADM8211_BBPCTL_CCAP (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ADM8211_BBPCTL_TYPE 0x001c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ADM8211_BBPCTL_WR (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ADM8211_BBPCTL_RD (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ADM8211_BBPCTL_ADDR 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ADM8211_BBPCTL_DATA 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* CSR12A - SYNCTL (Synthesizer Control port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ADM8211_SYNCTL_WR (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ADM8211_SYNCTL_RD (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ADM8211_SYNCTL_CS0 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ADM8211_SYNCTL_CS1 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ADM8211_SYNCTL_CAL (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ADM8211_SYNCTL_SELCAL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ADM8211_SYNCTL_RFtype ((1 << 24) | (1 << 23) | (1 << 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ADM8211_SYNCTL_RFMD (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ADM8211_SYNCTL_GENERAL (0x7 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* SYNCTL 21:0 Data (Si4126: 18-bit data, 4-bit address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* CSR18 - CMDR (Command Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ADM8211_CMDR_PM (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ADM8211_CMDR_APM (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ADM8211_CMDR_RTE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ADM8211_CMDR_DRT ((1 << 3) | (1 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ADM8211_CMDR_DRT_8DW (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ADM8211_CMDR_DRT_16DW (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ADM8211_CMDR_DRT_SF (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* CSR33 - SYNRF (SYNRF direct control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ADM8211_SYNRF_SELSYN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ADM8211_SYNRF_SELRF (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ADM8211_SYNRF_LERF (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ADM8211_SYNRF_LEIF (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ADM8211_SYNRF_SYNCLK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ADM8211_SYNRF_SYNDATA (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ADM8211_SYNRF_PE1 (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ADM8211_SYNRF_PE2 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ADM8211_SYNRF_PA_PE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ADM8211_SYNRF_TR_SW (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ADM8211_SYNRF_TR_SWN (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ADM8211_SYNRF_RADIO (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ADM8211_SYNRF_CAL_EN (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ADM8211_SYNRF_PHYRST (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ADM8211_SYNRF_IF_SELECT_0 (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ADM8211_SYNRF_IF_SELECT_1 ((1 << 31) | (1 << 28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ADM8211_SYNRF_WRITE_SYNDATA_0 (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ADM8211_SYNRF_WRITE_SYNDATA_1 ((1 << 31) | (1 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ADM8211_SYNRF_WRITE_CLOCK_0 (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ADM8211_SYNRF_WRITE_CLOCK_1 ((1 << 31) | (1 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* CSR44 - WEPCTL (WEP Control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ADM8211_WEPCTL_WEPENABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ADM8211_WEPCTL_WPAENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ADM8211_WEPCTL_CURRENT_TABLE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ADM8211_WEPCTL_TABLE_WR (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ADM8211_WEPCTL_TABLE_RD (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define ADM8211_WEPCTL_WEPRXBYP (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ADM8211_WEPCTL_SEL_WEPTABLE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ADM8211_WEPCTL_ADDR (0x000001ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* CSR45 - WESK (Data Entry for Share/Individual Key) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ADM8211_WESK_DATA (0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* FER (Function Event Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ADM8211_FER_INTR_EV_ENT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Si4126 RF Synthesizer - Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SI4126_MAIN_CONF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SI4126_PHASE_DET_GAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SI4126_POWERDOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SI4126_RF1_N_DIV 3 /* only Si4136 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SI4126_RF2_N_DIV 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SI4126_IF_N_DIV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SI4126_RF1_R_DIV 6 /* only Si4136 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SI4126_RF2_R_DIV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SI4126_IF_R_DIV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Main Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SI4126_MAIN_XINDIV2 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SI4126_MAIN_IFDIV ((1 << 11) | (1 << 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Powerdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SI4126_POWERDOWN_PDIB (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SI4126_POWERDOWN_PDRB (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* RF3000 BBP - Control Port Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* 0x00 - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define RF3000_MODEM_CTRL__RX_STATUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define RF3000_CCA_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define RF3000_DIVERSITY__RSSI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define RF3000_RX_SIGNAL_FIELD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define RF3000_RX_LEN_MSB 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define RF3000_RX_LEN_LSB 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define RF3000_RX_SERVICE_FIELD 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define RF3000_TX_VAR_GAIN__TX_LEN_EXT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define RF3000_TX_LEN_MSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define RF3000_TX_LEN_LSB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define RF3000_LOW_GAIN_CALIB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define RF3000_HIGH_GAIN_CALIB 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* ADM8211 revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define ADM8211_REV_AB 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ADM8211_REV_AF 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ADM8211_REV_BA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ADM8211_REV_CA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct adm8211_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) __le32 buffer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __le32 buffer2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define RDES0_STATUS_OWN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define RDES0_STATUS_ES (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define RDES0_STATUS_SQL (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define RDES0_STATUS_DE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define RDES0_STATUS_FS (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define RDES0_STATUS_LS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define RDES0_STATUS_PCF (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define RDES0_STATUS_SFDE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define RDES0_STATUS_SIGE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define RDES0_STATUS_CRC16E (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define RDES0_STATUS_RXTOE (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define RDES0_STATUS_CRC32E (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define RDES0_STATUS_ICVE (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define RDES0_STATUS_DA1 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define RDES0_STATUS_DA0 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define RDES0_STATUS_RXDR ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define RDES0_STATUS_FL (0x00000fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define RDES1_CONTROL_RER (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define RDES1_CONTROL_RCH (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define RDES1_CONTROL_RBS2 (0x00fff000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define RDES1_CONTROL_RBS1 (0x00000fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define RDES1_STATUS_RSSI (0x0000007f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TDES0_CONTROL_OWN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TDES0_CONTROL_DONE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TDES0_CONTROL_TXDR (0x0ff00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define TDES0_STATUS_OWN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define TDES0_STATUS_DONE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TDES0_STATUS_ES (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TDES0_STATUS_TLT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TDES0_STATUS_TRT (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TDES0_STATUS_TUF (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TDES0_STATUS_TRO (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define TDES0_STATUS_SOFBR (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define TDES0_STATUS_ACR (0x00000fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TDES1_CONTROL_IC (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define TDES1_CONTROL_LS (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define TDES1_CONTROL_FS (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define TDES1_CONTROL_TER (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define TDES1_CONTROL_TCH (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define TDES1_CONTROL_RBS2 (0x00fff000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define TDES1_CONTROL_RBS1 (0x00000fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* SRAM offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define ADM8211_SRAM(x) (priv->pdev->revision < ADM8211_REV_BA ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ADM8211_SRAM_A_ ## x : ADM8211_SRAM_B_ ## x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define ADM8211_SRAM_INDIV_KEY 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define ADM8211_SRAM_A_SHARE_KEY 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define ADM8211_SRAM_B_SHARE_KEY 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define ADM8211_SRAM_A_SSID 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define ADM8211_SRAM_B_SSID 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define ADM8211_SRAM_SSID ADM8211_SRAM(SSID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define ADM8211_SRAM_A_SUPP_RATE 0x0191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define ADM8211_SRAM_B_SUPP_RATE 0x00dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define ADM8211_SRAM_SUPP_RATE ADM8211_SRAM(SUPP_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define ADM8211_SRAM_A_SIZE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define ADM8211_SRAM_B_SIZE 0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define ADM8211_SRAM_SIZE ADM8211_SRAM(SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct adm8211_rx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct adm8211_tx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) size_t hdrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PLCP_SIGNAL_1M 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define PLCP_SIGNAL_2M 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define PLCP_SIGNAL_5M5 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PLCP_SIGNAL_11M 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct adm8211_tx_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 da[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 signal; /* PLCP signal / TX rate in 100 Kbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 service;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __le16 frame_body_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __le16 frame_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) __le16 plcp_frag_tail_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) __le16 plcp_frag_head_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) __le16 dur_frag_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) __le16 dur_frag_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u8 addr4[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define ADM8211_TXHDRCTL_SHORT_PREAMBLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define ADM8211_TXHDRCTL_MORE_FRAG (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define ADM8211_TXHDRCTL_MORE_DATA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define ADM8211_TXHDRCTL_FRAG_NO (1 << 3) /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define ADM8211_TXHDRCTL_ENABLE_RTS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER (1 << 15) /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) __le16 header_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) __le16 frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 retry_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 wep2key0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 wep2key1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 wep2key2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 wep2key3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u8 keyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u8 entry_control; // huh??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define RX_COPY_BREAK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define RX_PKT_SIZE 2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct adm8211_eeprom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) __le16 signature; /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 major_version; /* 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 minor_version; /* 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 reserved_1[4]; /* 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 hwaddr[6]; /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 reserved_2[8]; /* 0x1E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __le16 cr49; /* 0x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 cr03; /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 cr28; /* 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 cr29; /* 0x1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u8 country_code; /* 0x1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* specific bbp types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define ADM8211_BBP_RFMD3000 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define ADM8211_BBP_RFMD3002 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define ADM8211_BBP_ADM8011 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 specific_bbptype; /* 0x1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 specific_rftype; /* 0x1D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 reserved_3[2]; /* 0x1E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __le16 device_id; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) __le16 vendor_id; /* 0x22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) __le16 subsystem_id; /* 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) __le16 subsystem_vendor_id; /* 0x26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 maxlat; /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 mingnt; /* 0x29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __le16 cis_pointer_low; /* 0x2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __le16 cis_pointer_high; /* 0x2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) __le16 csr18; /* 0x2E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u8 reserved_4[16]; /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 d1_pwrdara; /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u8 d0_pwrdara; /* 0x41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u8 d3_pwrdara; /* 0x42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 d2_pwrdara; /* 0x43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 antenna_power[14]; /* 0x44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __le16 cis_wordcnt; /* 0x52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 tx_power[14]; /* 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 lpf_cutoff[14]; /* 0x62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 lnags_threshold[14]; /* 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) __le16 checksum; /* 0x7E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u8 cis_data[]; /* 0x80, 384 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct adm8211_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct adm8211_csr __iomem *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct adm8211_desc *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct adm8211_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dma_addr_t rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct adm8211_rx_ring_info *rx_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct adm8211_tx_ring_info *tx_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int rx_ring_size, tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int cur_tx, dirty_tx, cur_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct ieee80211_low_level_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct ieee80211_supported_band band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct ieee80211_channel channels[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 bssid[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 soft_rx_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u8 retry_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u8 ant_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 tx_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 lpf_cutoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 lnags_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct adm8211_eeprom *eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) size_t eeprom_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 nar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define ADM8211_TYPE_INTERSIL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define ADM8211_TYPE_RFMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define ADM8211_TYPE_MARVEL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define ADM8211_TYPE_AIROHA 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define ADM8211_TYPE_ADMTEK 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int rf_type:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int bbp_type:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u8 specific_bbptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ADM8211_RFMD2948 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ADM8211_RFMD2958 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ADM8211_RFMD2958_RF3000_CONTROL_POWER = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ADM8211_MAX2820 = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ADM8211_AL2210L = 0xC, /* Airoha */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) } transceiver_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct ieee80211_chan_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct ieee80211_chan_range cranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {1, 11}, /* FCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {1, 11}, /* IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {1, 13}, /* ETSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {10, 11}, /* SPAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {10, 13}, /* FRANCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {14, 14}, /* MMK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {1, 14}, /* MMK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #endif /* ADM8211_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags