^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Description of Z8530 Z85C30 and Z85230 communications chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _Z8530_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _Z8530_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Conversion routines to/from brg time constants from/to bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * per second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* The Zilog register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FLAG 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Write Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R0 0 /* Register selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R12 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R13 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R15 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RPRIME 16 /* Indicate a prime register access on 230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NULLCODE 0 /* Null Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define POINT_HIGH 0x8 /* Select upper half of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SEND_ABORT 0x18 /* HDLC Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RES_Tx_P 0x28 /* Reset TxINT Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ERR_RES 0x30 /* Error Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RES_H_IUS 0x38 /* Reset highest IUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RES_EOM_L 0xC0 /* Reset EOM latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Write Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TxINT_ENAB 0x2 /* Tx Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PAR_SPEC 0x4 /* Parity is special condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RxINT_DISAB 0 /* Rx Int Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define INT_ERR_Rx 0x18 /* Int on error only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Write Register #2 (Interrupt Vector) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Write Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RxENABLE 0x1 /* Rx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ENT_HM 0x10 /* Enter Hunt Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AUTO_ENAB 0x20 /* Auto Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define Rx5 0x0 /* Rx 5 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define Rx7 0x40 /* Rx 7 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define Rx6 0x80 /* Rx 6 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define Rx8 0xc0 /* Rx 8 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Write Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PAR_ENA 0x1 /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PAR_EVEN 0x2 /* Parity Even/Odd* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SYNC_ENAB 0 /* Sync Modes Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SB1 0x4 /* 1 stop bit/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SB15 0x8 /* 1.5 stop bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SB2 0xc /* 2 stop bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MONSYNC 0 /* 8 Bit Sync character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BISYNC 0x10 /* 16 bit sync character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EXTSYNC 0x30 /* External Sync Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define X1CLK 0x0 /* x1 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define X16CLK 0x40 /* x16 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define X32CLK 0x80 /* x32 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define X64CLK 0xC0 /* x64 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Write Register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RTS 0x2 /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TxENAB 0x8 /* Tx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SND_BRK 0x10 /* Send Break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define Tx5 0x0 /* Tx 5 bits (or less)/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define Tx7 0x20 /* Tx 7 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define Tx6 0x40 /* Tx 6 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define Tx8 0x60 /* Tx 8 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DTR 0x80 /* DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Write Register 8 (transmit buffer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Write Register 9 (Master interrupt control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VIS 1 /* Vector Includes Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define NV 2 /* No Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DLC 4 /* Disable Lower Chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MIE 8 /* Master Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define STATHI 0x10 /* Status high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define NORESET 0 /* No reset on write to R9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CHRB 0x40 /* Reset channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CHRA 0x80 /* Reset channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FHWRES 0xc0 /* Force hardware reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Write Register 10 (misc control bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BIT6 1 /* 6 bit/8bit sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LOOPMODE 2 /* SDLC Loop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MARKIDLE 8 /* Mark/flag on idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GAOP 0x10 /* Go active on poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define NRZ 0 /* NRZ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define NRZI 0x20 /* NRZI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FM1 0x40 /* FM1 (transition = 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FM0 0x60 /* FM0 (transition = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CRCPS 0x80 /* CRC Preset I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Write Register 11 (Clock Mode control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TRxCXT 0 /* TRxC = Xtal output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TRxCTC 1 /* TRxC = Transmit clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TRxCBR 2 /* TRxC = BR Generator Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TRxCDP 3 /* TRxC = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TRxCOI 4 /* TRxC O/I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TCRTxCP 0 /* Transmit clock = RTxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TCTRxCP 8 /* Transmit clock = TRxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TCBR 0x10 /* Transmit clock = BR Generator output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TCDPLL 0x18 /* Transmit clock = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RCRTxCP 0 /* Receive clock = RTxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RCBR 0x40 /* Receive clock = BR Generator output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RCDPLL 0x60 /* Receive clock = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Write Register 12 (lower byte of baud rate generator time constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Write Register 13 (upper byte of baud rate generator time constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Write Register 14 (Misc control bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BRENABL 1 /* Baud rate generator enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BRSRC 2 /* Baud rate generator source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DTRREQ 4 /* DTR/Request function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AUTOECHO 8 /* Auto Echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define LOOPBAK 0x10 /* Local loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SEARCH 0x20 /* Enter search mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RMC 0x40 /* Reset missing clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DISDPLL 0x60 /* Disable DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SSBR 0x80 /* Set DPLL source = BR generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SFMM 0xc0 /* Set FM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SNRZI 0xe0 /* Set NRZI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Write Register 15 (external/status interrupt control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PRIME 1 /* R5' etc register access (Z85C30/230 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ZCIE 2 /* Zero count IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FIFOE 4 /* Z85230 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DCDIE 8 /* DCD IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SYNCIE 0x10 /* Sync/hunt IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CTSIE 0x20 /* CTS IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TxUIE 0x40 /* Tx Underrun/EOM IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BRKIE 0x80 /* Break/Abort IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Read Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define Rx_CH_AV 0x1 /* Rx Character Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ZCOUNT 0x2 /* Zero count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DCD 0x8 /* DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SYNC_HUNT 0x10 /* Sync/hunt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CTS 0x20 /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TxEOM 0x40 /* Tx underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BRK_ABRT 0x80 /* Break/Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Read Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ALL_SNT 0x1 /* All sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Residue Data for 8 Rx bits/char programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RES3 0x8 /* 0/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RES4 0x4 /* 0/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RES5 0xc /* 0/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RES6 0x2 /* 0/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RES7 0xa /* 0/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RES8 0x6 /* 0/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RES18 0xe /* 1/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RES28 0x0 /* 2/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Special Rx Condition Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PAR_ERR 0x10 /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define Rx_OVR 0x20 /* Rx Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CRC_ERR 0x40 /* CRC/Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define END_FR 0x80 /* End of Frame (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Read Register 2 (channel b only) - Interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Read Register 3 (interrupt pending register) ch a only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CHBTxIP 0x2 /* Channel B Tx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CHBRxIP 0x4 /* Channel B Rx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CHATxIP 0x10 /* Channel A Tx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CHARxIP 0x20 /* Channel A Rx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Read Register 8 (receive data register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Read Register 10 (misc status bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ONLOOP 2 /* On loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define LOOPSEND 0x10 /* Loop sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK2MIS 0x40 /* Two clocks missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK1MIS 0x80 /* One clock missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Read Register 12 (lower byte of baud rate generator constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Read Register 13 (upper byte of baud rate generator constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Read Register 15 (value of WR 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Interrupt handling functions for this SCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct z8530_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct z8530_irqhandler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void (*rx)(struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void (*tx)(struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) void (*status)(struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * A channel of the Z8530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct z8530_channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct z8530_irqhandler *irqs; /* IRQ handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Synchronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u16 count; /* Buyes received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u16 max; /* Most we can receive this frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u16 mtu; /* MTU of the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 *dptr; /* Pointer into rx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct sk_buff *skb; /* Buffer dptr points into */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct sk_buff *skb2; /* Pending buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 status; /* Current DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 dcdcheck; /* which bit to check for line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 sync; /* Set if in sync mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 regs[32]; /* Register map for the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 pendregs[32]; /* Pending register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct sk_buff *tx_skb; /* Buffer being transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct sk_buff *tx_next_skb; /* Next transmit buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 *tx_ptr; /* Byte pointer into the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 *tx_next_ptr; /* Next pointer to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u8 *tx_dma_buf[2]; /* TX flip buffers for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 tx_dma_used; /* Flip buffer usage toggler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u16 txcount; /* Count of bytes to transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void (*rx_function)(struct z8530_channel *, struct sk_buff *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Sync DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 rxdma; /* DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 txdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 rxdma_on; /* DMA active if flag set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 txdma_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 dma_num; /* Buffer we are DMAing into */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 dma_ready; /* Is the other buffer free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 dma_tx; /* TX is to use DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 *rx_buf[2]; /* The flip buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * System
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct z8530_dev *dev; /* Z85230 chip instance we are from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long ctrlio; /* I/O ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long dataio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * For PC we encode this way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define Z8530_PORT_SLEEP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define Z8530_PORT_OF(x) ((x)&0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 rx_overrun; /* Overruns - not done yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 rx_crc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Bound device pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void *private; /* For our owner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct net_device *netdevice; /* Network layer device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Async features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct tty_struct *tty; /* Attached terminal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int line; /* Minor number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) wait_queue_head_t open_wait; /* Tasks waiting to open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) wait_queue_head_t close_wait; /* and for close to end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long event; /* Pending events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int fdcount; /* # of fd on device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int blocked_open; /* # of blocked opens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int x_char; /* XON/XOF char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned char *xmit_buf; /* Transmit pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int xmit_head; /* Transmit ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int xmit_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int xmit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int xmit_fifo_size; /* Transmit FIFO info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int close_delay; /* Do we wait for drain on close ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned short closing_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* We need to know the current clock divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * to read the bps rate the chip has currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int zs_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int baud_base; /* Baud parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int custom_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned char tx_active; /* character is being xmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned char tx_stopped; /* output is suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) spinlock_t *lock; /* Device lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Each Z853x0 device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct z8530_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) char *name; /* Device instance name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct z8530_channel chanA; /* SCC channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct z8530_channel chanB; /* SCC channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define Z8530 0 /* NMOS dinosaur */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define Z85C30 1 /* CMOS - better */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define Z85230 2 /* CMOS with real FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int irq; /* Interrupt for the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int active; /* Soft interrupt enable - the Mac doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) always have a hard disable on its 8530s... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) extern u8 z8530_dead_port[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) extern u8 z8530_hdlc_kilostream_85230[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) extern u8 z8530_hdlc_kilostream[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) irqreturn_t z8530_interrupt(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) void z8530_describe(struct z8530_dev *, char *mapping, unsigned long io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int z8530_init(struct z8530_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int z8530_shutdown(struct z8530_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int z8530_sync_open(struct net_device *, struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int z8530_sync_close(struct net_device *, struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int z8530_sync_dma_open(struct net_device *, struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int z8530_sync_dma_close(struct net_device *, struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int z8530_sync_txdma_open(struct net_device *, struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int z8530_sync_txdma_close(struct net_device *, struct z8530_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int z8530_channel_load(struct z8530_channel *, u8 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Standard interrupt vector sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) extern struct z8530_irqhandler z8530_sync, z8530_async, z8530_nop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * Asynchronous Interfacing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * The size of the serial xmit buffer is 1 page, or 4096 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SERIAL_XMIT_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define WAKEUP_CHARS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Events are used to schedule things to happen at timer-interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * time, instead of at rs interrupt time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define RS_EVENT_WRITE_WAKEUP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Internal flags used only by kernel/chr_drv/serial.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #endif /* !(_Z8530_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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