Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) .psize 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)   wanXL serial card driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)   card firmware part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)   Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	DPRAM BDs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	0x000 - 0x050 TX#0	0x050 - 0x140 RX#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	0x140 - 0x190 TX#1	0x190 - 0x280 RX#1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	0x280 - 0x2D0 TX#2	0x2D0 - 0x3C0 RX#2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	0x3C0 - 0x410 TX#3	0x410 - 0x500 RX#3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	000 5FF 1536 Bytes Dual-Port RAM User Data / BDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	600 6FF 256 Bytes Dual-Port RAM User Data / BDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	700 7FF 256 Bytes Dual-Port RAM User Data / BDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	C00 CBF 192 Bytes Dual-Port RAM Parameter RAM Page 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	D00 DBF 192 Bytes Dual-Port RAM Parameter RAM Page 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	E00 EBF 192 Bytes Dual-Port RAM Parameter RAM Page 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	F00 FBF 192 Bytes Dual-Port RAM Parameter RAM Page 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	local interrupts		    level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	NMI					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	PIT timer, CPM (RX/TX complete)		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	PCI9060	DMA and PCI doorbells		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	Cable - not used			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/hdlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/hdlc/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include "wanxl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* memory addresses and offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) MAX_RAM_SIZE	= 16 * 1024 * 1024	// max RAM supported by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) PCI9060_VECTOR	= 0x0000006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) CPM_IRQ_BASE	= 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) ERROR_VECTOR	= CPM_IRQ_BASE * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) SCC1_VECTOR	= (CPM_IRQ_BASE + 0x1E) * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) SCC2_VECTOR	= (CPM_IRQ_BASE + 0x1D) * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) SCC3_VECTOR	= (CPM_IRQ_BASE + 0x1C) * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) SCC4_VECTOR	= (CPM_IRQ_BASE + 0x1B) * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) CPM_IRQ_LEVEL	= 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) TIMER_IRQ	= 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) TIMER_IRQ_LEVEL = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) PITR_CONST	= 0x100 + 16		// 1 Hz timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) MBAR		= 0x0003FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) VALUE_WINDOW	= 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) ORDER_WINDOW	= 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) PLX		= 0xFFF90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) CSRA		= 0xFFFB0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) CSRB		= 0xFFFB0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) CSRC		= 0xFFFB0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) CSRD		= 0xFFFB0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) STATUS_CABLE_LL		= 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) STATUS_CABLE_DTR	= 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) DPRBASE		= 0xFFFC0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) SCC1_BASE	= DPRBASE + 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) MISC_BASE	= DPRBASE + 0xCB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) SCC2_BASE	= DPRBASE + 0xD00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) SCC3_BASE	= DPRBASE + 0xE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) SCC4_BASE	= DPRBASE + 0xF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) // offset from SCCx_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) // SCC_xBASE contain offsets from DPRBASE and must be divisible by 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) SCC_RBASE	= 0		// 16-bit RxBD base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) SCC_TBASE	= 2		// 16-bit TxBD base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) SCC_RFCR	= 4		// 8-bit Rx function code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) SCC_TFCR	= 5		// 8-bit Tx function code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) SCC_MRBLR	= 6		// 16-bit maximum Rx buffer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) SCC_C_MASK	= 0x34		// 32-bit CRC constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) SCC_C_PRES	= 0x38		// 32-bit CRC preset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) SCC_MFLR	= 0x46		// 16-bit max Rx frame length (without flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) REGBASE		= DPRBASE + 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) PICR		= REGBASE + 0x026	// 16-bit periodic irq control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) PITR		= REGBASE + 0x02A	// 16-bit periodic irq timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) OR1		= REGBASE + 0x064	// 32-bit RAM bank #1 options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) CICR		= REGBASE + 0x540	// 32(24)-bit CP interrupt config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) CIMR		= REGBASE + 0x548	// 32-bit CP interrupt mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) CISR		= REGBASE + 0x54C	// 32-bit CP interrupts in-service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) PADIR		= REGBASE + 0x550	// 16-bit PortA data direction bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) PAPAR		= REGBASE + 0x552	// 16-bit PortA pin assignment bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) PAODR		= REGBASE + 0x554	// 16-bit PortA open drain bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) PADAT		= REGBASE + 0x556	// 16-bit PortA data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PCDIR		= REGBASE + 0x560	// 16-bit PortC data direction bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PCPAR		= REGBASE + 0x562	// 16-bit PortC pin assignment bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PCSO		= REGBASE + 0x564	// 16-bit PortC special options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PCDAT		= REGBASE + 0x566	// 16-bit PortC data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PCINT		= REGBASE + 0x568	// 16-bit PortC interrupt control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CR		= REGBASE + 0x5C0	// 16-bit Command register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SCC1_REGS	= REGBASE + 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SCC2_REGS	= REGBASE + 0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SCC3_REGS	= REGBASE + 0x640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SCC4_REGS	= REGBASE + 0x660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SICR		= REGBASE + 0x6EC	// 32-bit SI clock route
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) // offset from SCCx_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SCC_GSMR_L	= 0x00	// 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SCC_GSMR_H	= 0x04	// 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SCC_PSMR	= 0x08	// 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SCC_TODR	= 0x0C	// 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SCC_DSR		= 0x0E	// 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SCC_SCCE	= 0x10	// 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SCC_SCCM	= 0x14	// 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SCC_SCCS	= 0x17	// 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #if QUICC_MEMCPY_USES_PLX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.macro memcpy_from_pci src, dest, len // len must be < 8 MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	addl #3, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	andl #0xFFFFFFFC, \len		// always copy n * 4 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	movel \src, PLX_DMA_0_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	movel \dest, PLX_DMA_0_LOCAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	movel \len, PLX_DMA_0_LENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	movel #0x0103, PLX_DMA_CMD_STS	// start channel 0 transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	bsr memcpy_from_pci_run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.macro memcpy_to_pci src, dest, len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	addl #3, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	andl #0xFFFFFFFC, \len		// always copy n * 4 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	movel \src, PLX_DMA_1_LOCAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	movel \dest, PLX_DMA_1_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	movel \len, PLX_DMA_1_LENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	movel #0x0301, PLX_DMA_CMD_STS	// start channel 1 transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bsr memcpy_to_pci_run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.macro memcpy src, dest, len	// len must be < 65536 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	movel %d7, -(%sp)		// src and dest must be < 256 MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	movel \len, %d7			// bits 0 and 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	lsrl #2, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	andl \len, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	beq 99f				// only 0 - 3 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	subl #1, \len			// for dbf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 98:	movel (\src)+, (\dest)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	dbfw \len, 98b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 99:	movel %d7, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	btstl #1, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	beq 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	movew (\src)+, (\dest)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 99:	btstl #0, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	beq 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	moveb (\src)+, (\dest)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 99:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	movel (%sp)+, %d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.macro memcpy_from_pci src, dest, len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	addl #VALUE_WINDOW, \src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	memcpy \src, \dest, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.macro memcpy_to_pci src, dest, len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	addl #VALUE_WINDOW, \dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	memcpy \src, \dest, \len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.macro wait_for_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 99:	btstl #0, CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	bne 99b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /****************************** card initialization *******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.global _start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) _start:	bra init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.org _start + 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ch_status_addr:	.long 0, 0, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rx_descs_addr:	.long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #if DETECT_RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	movel OR1, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	andl #0xF00007FF, %d0		// mask AMxx bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	movel %d0, OR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	addl #VALUE_WINDOW, rx_descs_addr // PCI addresses of shared data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	clrl %d0			// D0 = 4 * port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) init_1:	tstl ch_status_addr(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	beq init_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	addl #VALUE_WINDOW, ch_status_addr(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) init_2:	addl #4, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	cmpl #4 * 4, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	bne init_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	movel #pci9060_interrupt, PCI9060_VECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	movel #error_interrupt, ERROR_VECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	movel #port_interrupt_1, SCC1_VECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	movel #port_interrupt_2, SCC2_VECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	movel #port_interrupt_3, SCC3_VECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	movel #port_interrupt_4, SCC4_VECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	movel #timer_interrupt, TIMER_IRQ * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	movel #0x78000000, CIMR		// only SCCx IRQs from CPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	movew #(TIMER_IRQ_LEVEL << 8) + TIMER_IRQ, PICR	// interrupt from PIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	movew #PITR_CONST, PITR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	// SCC1=SCCa SCC2=SCCb SCC3=SCCc SCC4=SCCd prio=4 HP=-1 IRQ=64-79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	movel #0xD41F40 + (CPM_IRQ_LEVEL << 13), CICR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	movel #0x543, PLX_DMA_0_MODE	// 32-bit, Ready, Burst, IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	movel #0x543, PLX_DMA_1_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	movel #0x0, PLX_DMA_0_DESC	// from PCI to local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	movel #0x8, PLX_DMA_1_DESC	// from local to PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	movel #0x101, PLX_DMA_CMD_STS	// enable both DMA channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	// enable local IRQ, DMA, doorbells and PCI IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	orl #0x000F0300, PLX_INTERRUPT_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #if DETECT_RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	bsr ram_test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	movel #1, PLX_MAILBOX_5		// non-zero value = init complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	bsr check_csr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	movew #0xFFFF, PAPAR		// all pins are clocks/data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	clrw PADIR			// first function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	clrw PCSO			// CD and CTS always active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /****************************** main loop *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) main:	movel channel_stats, %d7	// D7 = doorbell + irq status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	clrl channel_stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	tstl %d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	bne main_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	// nothing to do - wait for next event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	stop #0x2200			// supervisor + IRQ level 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	movew #0x2700, %sr		// disable IRQs again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	bra main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) main_1:	clrl %d0			// D0 = 4 * port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	clrl %d6			// D6 = doorbell to host value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) main_l: btstl #DOORBELL_TO_CARD_CLOSE_0, %d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	beq main_op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	bclrl #DOORBELL_TO_CARD_OPEN_0, %d7 // in case both bits are set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	bsr close_port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) main_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	btstl #DOORBELL_TO_CARD_OPEN_0, %d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	beq main_cl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	bsr open_port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) main_cl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	btstl #DOORBELL_TO_CARD_TX_0, %d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	beq main_txend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	bsr tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) main_txend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	btstl #TASK_SCC_0, %d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	beq main_next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	bsr tx_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	bsr rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) main_next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	lsrl #1, %d7			// port status for next port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	addl #4, %d0			// D0 = 4 * next port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	cmpl #4 * 4, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	bne main_l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	movel %d6, PLX_DOORBELL_FROM_CARD // signal the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	bra main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /****************************** open port *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) open_port:				// D0 = 4 * port, D6 = doorbell to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	movel ch_status_addr(%d0), %a0	// A0 = port status address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	tstl STATUS_OPEN(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	bne open_port_ret		// port already open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	movel #1, STATUS_OPEN(%a0)	// confirm the port is open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) // setup BDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	clrl tx_in(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	clrl tx_out(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	clrl tx_count(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	clrl rx_in(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	movel SICR, %d1			// D1 = clock settings in SICR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	andl clocking_mask(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	cmpl #CLOCK_TXFROMRX, STATUS_CLOCKING(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	bne open_port_clock_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	orl clocking_txfromrx(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	bra open_port_set_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) open_port_clock_ext:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	orl clocking_ext(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) open_port_set_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	movel %d1, SICR			// update clock settings in SICR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	orw #STATUS_CABLE_DTR, csr_output(%d0)	// DTR on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	bsr check_csr			// call with disabled timer interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) // Setup TX descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	movel first_buffer(%d0), %d1	// D1 = starting buffer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	movel tx_first_bd(%d0), %a1	// A1 = starting TX BD address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	movel #TX_BUFFERS - 2, %d2	// D2 = TX_BUFFERS - 1 counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	movel #0x18000000, %d3		// D3 = initial TX BD flags: Int + Last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	cmpl #PARITY_NONE, STATUS_PARITY(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	beq open_port_tx_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	bsetl #26, %d3			// TX BD flag: Transmit CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) open_port_tx_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	movel %d3, (%a1)+		// TX flags + length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	movel %d1, (%a1)+		// buffer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	addl #BUFFER_LENGTH, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	dbfw %d2, open_port_tx_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	bsetl #29, %d3			// TX BD flag: Wrap (last BD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	movel %d3, (%a1)+		// Final TX flags + length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	movel %d1, (%a1)+		// buffer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) // Setup RX descriptors			// A1 = starting RX BD address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	movel #RX_BUFFERS - 2, %d2	// D2 = RX_BUFFERS - 1 counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) open_port_rx_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	movel #0x90000000, (%a1)+	// RX flags + length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	movel %d1, (%a1)+		// buffer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	addl #BUFFER_LENGTH, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	dbfw %d2, open_port_rx_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	movel #0xB0000000, (%a1)+	// Final RX flags + length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	movel %d1, (%a1)+		// buffer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) // Setup port parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	movel scc_base_addr(%d0), %a1	// A1 = SCC_BASE address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	movel scc_reg_addr(%d0), %a2	// A2 = SCC_REGS address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	movel #0xFFFF, SCC_SCCE(%a2)	// clear status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	movel #0x0000, SCC_SCCM(%a2)	// interrupt mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	movel tx_first_bd(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	movew %d1, SCC_TBASE(%a1)	// D1 = offset of first TxBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	addl #TX_BUFFERS * 8, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	movew %d1, SCC_RBASE(%a1)	// D1 = offset of first RxBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	moveb #0x8, SCC_RFCR(%a1)	// Intel mode, 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	moveb #0x8, SCC_TFCR(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) // Parity settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	cmpl #PARITY_CRC16_PR1_CCITT, STATUS_PARITY(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	bne open_port_parity_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	clrw SCC_PSMR(%a2)		// CRC16-CCITT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	movel #0xF0B8, SCC_C_MASK(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	movel #0xFFFF, SCC_C_PRES(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	movew #2, parity_bytes(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	bra open_port_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) open_port_parity_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	cmpl #PARITY_CRC32_PR1_CCITT, STATUS_PARITY(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	bne open_port_parity_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	movew #0x0800, SCC_PSMR(%a2)	// CRC32-CCITT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	movel #0xDEBB20E3, SCC_C_MASK(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	movel #0xFFFFFFFF, SCC_C_PRES(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	movew #4, parity_bytes(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	bra open_port_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) open_port_parity_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	cmpl #PARITY_CRC16_PR0_CCITT, STATUS_PARITY(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	bne open_port_parity_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	clrw SCC_PSMR(%a2)		// CRC16-CCITT preset 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	movel #0xF0B8, SCC_C_MASK(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	clrl SCC_C_PRES(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	movew #2, parity_bytes(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	bra open_port_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) open_port_parity_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	cmpl #PARITY_CRC32_PR0_CCITT, STATUS_PARITY(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	bne open_port_parity_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	movew #0x0800, SCC_PSMR(%a2)	// CRC32-CCITT preset 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	movel #0xDEBB20E3, SCC_C_MASK(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	clrl SCC_C_PRES(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	movew #4, parity_bytes(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	bra open_port_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) open_port_parity_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	clrw SCC_PSMR(%a2)		// no parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	movel #0xF0B8, SCC_C_MASK(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	movel #0xFFFF, SCC_C_PRES(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	movew #HDLC_MAX_MRU, SCC_MFLR(%a1) // 0 bytes for CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	clrw parity_bytes(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) open_port_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	movel #0x00000003, SCC_GSMR_H(%a2) // RTSM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	cmpl #ENCODING_NRZI, STATUS_ENCODING(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	bne open_port_nrz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	movel #0x10040900, SCC_GSMR_L(%a2) // NRZI: TCI Tend RECN+TENC=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	bra open_port_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) open_port_nrz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	movel #0x10040000, SCC_GSMR_L(%a2) // NRZ: TCI Tend RECN+TENC=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) open_port_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	movew #BUFFER_LENGTH, SCC_MRBLR(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	movel %d0, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	lsll #4, %d1			// D1 bits 7 and 6 = port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	orl #1, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	movew %d1, CR			// Init SCC RX and TX params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	wait_for_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	// TCI Tend ENR ENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	movew #0x001F, SCC_SCCM(%a2)	// TXE RXF BSY TXB RXB interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	orl #0x00000030, SCC_GSMR_L(%a2) // enable SCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) open_port_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /****************************** close port ****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) close_port:				// D0 = 4 * port, D6 = doorbell to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	movel scc_reg_addr(%d0), %a0	// A0 = SCC_REGS address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	clrw SCC_SCCM(%a0)		// no SCC interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	andl #0xFFFFFFCF, SCC_GSMR_L(%a0) // Disable ENT and ENR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	andw #~STATUS_CABLE_DTR, csr_output(%d0) // DTR off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	bsr check_csr			// call with disabled timer interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	movel ch_status_addr(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	clrl STATUS_OPEN(%d1)		// confirm the port is closed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /****************************** transmit packet ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) // queue packets for transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) tx:					// D0 = 4 * port, D6 = doorbell to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	cmpl #TX_BUFFERS, tx_count(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	beq tx_ret			// all DB's = descs in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	movel tx_out(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	movel %d1, %d2			// D1 = D2 = tx_out BD# = desc#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	mulul #DESC_LENGTH, %d2		// D2 = TX desc offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	addl ch_status_addr(%d0), %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	addl #STATUS_TX_DESCS, %d2	// D2 = TX desc address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	cmpl #PACKET_FULL, (%d2)	// desc status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	bne tx_ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) // queue it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	movel 4(%d2), %a0		// PCI address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	lsll #3, %d1			// BD is 8-bytes long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	addl tx_first_bd(%d0), %d1	// D1 = current tx_out BD addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	movel 4(%d1), %a1		// A1 = dest address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	movel 8(%d2), %d2		// D2 = length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	movew %d2, 2(%d1)		// length into BD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	memcpy_from_pci %a0, %a1, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	bsetl #31, (%d1)		// CP go ahead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) // update tx_out and tx_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	movel tx_out(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	addl #1, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	cmpl #TX_BUFFERS, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	bne tx_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	clrl %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) tx_1:	movel %d1, tx_out(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	addl #1, tx_count(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	bra tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) tx_ret: rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /****************************** packet received ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) // Service receive buffers		// D0 = 4 * port, D6 = doorbell to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) rx:	movel rx_in(%d0), %d1		// D1 = rx_in BD#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	lsll #3, %d1			// BD is 8-bytes long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	addl rx_first_bd(%d0), %d1	// D1 = current rx_in BD address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	movew (%d1), %d2		// D2 = RX BD flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	btstl #15, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	bne rx_ret			// BD still empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	btstl #1, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	bne rx_overrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	tstw parity_bytes(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	bne rx_parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	bclrl #2, %d2			// do not test for CRC errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rx_parity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	andw #0x0CBC, %d2		// mask status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	cmpw #0x0C00, %d2		// correct frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	bne rx_bad_frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	clrl %d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	movew 2(%d1), %d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	subw parity_bytes(%d0), %d3	// D3 = packet length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	cmpw #HDLC_MAX_MRU, %d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	bgt rx_bad_frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rx_good_frame:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	movel rx_out, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	mulul #DESC_LENGTH, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	addl rx_descs_addr, %d2		// D2 = RX desc address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	cmpl #PACKET_EMPTY, (%d2)	// desc stat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	bne rx_overrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	movel %d3, 8(%d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	movel 4(%d1), %a0		// A0 = source address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	movel 4(%d2), %a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	tstl %a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	beq rx_ignore_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	memcpy_to_pci %a0, %a1, %d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) rx_ignore_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	movel packet_full(%d0), (%d2)	// update desc stat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) // update D6 and rx_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	bsetl #DOORBELL_FROM_CARD_RX, %d6 // signal host that RX completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	movel rx_out, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	addl #1, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	cmpl #RX_QUEUE_LENGTH, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	bne rx_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	clrl %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) rx_1:	movel %d2, rx_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) rx_free_bd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	andw #0xF000, (%d1)		// clear CM and error bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	bsetl #31, (%d1)		// free BD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) // update rx_in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	movel rx_in(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	addl #1, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	cmpl #RX_BUFFERS, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	bne rx_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	clrl %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rx_2:	movel %d1, rx_in(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	bra rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rx_overrun:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	movel ch_status_addr(%d0), %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	addl #1, STATUS_RX_OVERRUNS(%d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	bra rx_free_bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) rx_bad_frame:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	movel ch_status_addr(%d0), %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	addl #1, STATUS_RX_FRAME_ERRORS(%d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	bra rx_free_bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rx_ret: rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /****************************** packet transmitted ********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) // Service transmit buffers		// D0 = 4 * port, D6 = doorbell to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) tx_end:	tstl tx_count(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	beq tx_end_ret			// TX buffers already empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	movel tx_in(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	movel %d1, %d2			// D1 = D2 = tx_in BD# = desc#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	lsll #3, %d1			// BD is 8-bytes long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	addl tx_first_bd(%d0), %d1	// D1 = current tx_in BD address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	movew (%d1), %d3		// D3 = TX BD flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	btstl #15, %d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	bne tx_end_ret			// BD still being transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) // update D6, tx_in and tx_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	orl bell_tx(%d0), %d6		// signal host that TX desc freed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	subl #1, tx_count(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	movel tx_in(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	addl #1, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	cmpl #TX_BUFFERS, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	bne tx_end_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	clrl %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tx_end_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	movel %d1, tx_in(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) // free host's descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	mulul #DESC_LENGTH, %d2		// D2 = TX desc offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	addl ch_status_addr(%d0), %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	addl #STATUS_TX_DESCS, %d2	// D2 = TX desc address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	btstl #1, %d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	bne tx_end_underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	movel #PACKET_SENT, (%d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	bra tx_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tx_end_underrun:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	movel #PACKET_UNDERRUN, (%d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	bra tx_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) tx_end_ret: rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /****************************** PLX PCI9060 DMA memcpy ****************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #if QUICC_MEMCPY_USES_PLX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) // called with interrupts disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) memcpy_from_pci_run:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	movel %d0, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	movew %sr, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) memcpy_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	movel PLX_DMA_CMD_STS, %d0	// do not btst PLX register directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	btstl #4, %d0			// transfer done?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	bne memcpy_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	stop #0x2200			// enable PCI9060 interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	movew #0x2700, %sr		// disable interrupts again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	bra memcpy_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) memcpy_to_pci_run:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	movel %d0, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	movew %sr, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) memcpy_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	movel PLX_DMA_CMD_STS, %d0	// do not btst PLX register directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	btstl #12, %d0			// transfer done?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	bne memcpy_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	stop #0x2200			// enable PCI9060 interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	movew #0x2700, %sr		// disable interrupts again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	bra memcpy_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) memcpy_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	movew (%sp)+, %sr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	movel (%sp)+, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /****************************** PLX PCI9060 interrupt *****************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pci9060_interrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	movel %d0, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	movel PLX_DOORBELL_TO_CARD, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	movel %d0, PLX_DOORBELL_TO_CARD	// confirm all requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	orl %d0, channel_stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	movel #0x0909, PLX_DMA_CMD_STS	// clear DMA ch #0 and #1 interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	movel (%sp)+, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	rte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /****************************** SCC interrupts ************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) port_interrupt_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	orl #0, SCC1_REGS + SCC_SCCE; // confirm SCC events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	orl #1 << TASK_SCC_0, channel_stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	movel #0x40000000, CISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	rte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) port_interrupt_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	orl #0, SCC2_REGS + SCC_SCCE; // confirm SCC events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	orl #1 << TASK_SCC_1, channel_stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	movel #0x20000000, CISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	rte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) port_interrupt_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	orl #0, SCC3_REGS + SCC_SCCE; // confirm SCC events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	orl #1 << TASK_SCC_2, channel_stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	movel #0x10000000, CISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	rte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) port_interrupt_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 	orl #0, SCC4_REGS + SCC_SCCE; // confirm SCC events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	orl #1 << TASK_SCC_3, channel_stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	movel #0x08000000, CISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 	rte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) error_interrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	rte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /****************************** cable and PM routine ******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) // modified registers: none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) check_csr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 	movel %d0, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	movel %d1, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 	movel %d2, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 	movel %a0, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	movel %a1, -(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 	clrl %d0			// D0 = 4 * port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	movel #CSRA, %a0		// A0 = CSR address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) check_csr_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	movew (%a0), %d1		// D1 = CSR input bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	andl #0xE7, %d1			// PM and cable sense bits (no DCE bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 	cmpw #STATUS_CABLE_V35 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 	bne check_csr_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 	movew #0x0E08, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	bra check_csr_valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) check_csr_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	cmpw #STATUS_CABLE_X21 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 	bne check_csr_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	movew #0x0408, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	bra check_csr_valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) check_csr_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 	cmpw #STATUS_CABLE_V24 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 	bne check_csr_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 	movew #0x0208, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 	bra check_csr_valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) check_csr_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 	cmpw #STATUS_CABLE_EIA530 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 	bne check_csr_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	movew #0x0D08, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 	bra check_csr_valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) check_csr_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 	movew #0x0008, %d1		// D1 = disable everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 	movew #0x80E7, %d2		// D2 = input mask: ignore DSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 	bra check_csr_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) check_csr_valid:			// D1 = mode and IRQ bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 	movew csr_output(%d0), %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 	andw #0x3000, %d2		// D2 = requested LL and DTR bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 	orw %d2, %d1			// D1 = all requested output bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 	movew #0x80FF, %d2		// D2 = input mask: include DSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) check_csr_write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 	cmpw old_csr_output(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 	beq check_csr_input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 	movew %d1, old_csr_output(%d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 	movew %d1, (%a0)		// Write CSR output bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) check_csr_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	movew (PCDAT), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 	andw dcd_mask(%d0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 	beq check_csr_dcd_on		// DCD and CTS signals are negated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	movew (%a0), %d1		// D1 = CSR input bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 	andw #~STATUS_CABLE_DCD, %d1	// DCD off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 	bra check_csr_previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) check_csr_dcd_on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 	movew (%a0), %d1		// D1 = CSR input bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 	orw #STATUS_CABLE_DCD, %d1	// DCD on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) check_csr_previous:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	andw %d2, %d1			// input mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 	movel ch_status_addr(%d0), %a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 	cmpl STATUS_CABLE(%a1), %d1	// check for change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	beq check_csr_next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	movel %d1, STATUS_CABLE(%a1)	// update status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 	movel bell_cable(%d0), PLX_DOORBELL_FROM_CARD	// signal the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) check_csr_next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 	addl #2, %a0			// next CSR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 	addl #4, %d0			// D0 = 4 * next port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	cmpl #4 * 4, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 	bne check_csr_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	movel (%sp)+, %a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	movel (%sp)+, %a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 	movel (%sp)+, %d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	movel (%sp)+, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 	movel (%sp)+, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /****************************** timer interrupt ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) timer_interrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 	bsr check_csr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 	rte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /****************************** RAM sizing and test *******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #if DETECT_RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ram_test:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 	movel #0x12345678, %d1		// D1 = test value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 	movel %d1, (128 * 1024 - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 	movel #128 * 1024, %d0		// D0 = RAM size tested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ram_test_size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 	cmpl #MAX_RAM_SIZE, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 	beq ram_test_size_found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	movel %d0, %a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 	addl #128 * 1024 - 4, %a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 	cmpl (%a0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 	beq ram_test_size_check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ram_test_next_size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	lsll #1, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	bra ram_test_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ram_test_size_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 	eorl #0xFFFFFFFF, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 	movel %d1, (128 * 1024 - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 	cmpl (%a0), %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 	bne ram_test_next_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ram_test_size_found:			// D0 = RAM size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 	movel %d0, %a0			// A0 = fill ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 	subl #firmware_end + 4, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 	lsrl #2, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 	movel %d0, %d1			// D1 = DBf counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ram_test_fill:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 	movel %a0, -(%a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	dbfw %d1, ram_test_fill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 	subl #0x10000, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 	cmpl #0xFFFFFFFF, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 	bne ram_test_fill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ram_test_loop:				// D0 = DBf counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 	cmpl (%a0)+, %a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 	dbnew %d0, ram_test_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 	bne ram_test_found_bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 	subl #0x10000, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 	cmpl #0xFFFFFFFF, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 	bne ram_test_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 	bra ram_test_all_ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ram_test_found_bad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 	subl #4, %a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ram_test_all_ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 	movel %a0, PLX_MAILBOX_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /****************************** constants *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) scc_reg_addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 	.long SCC1_REGS, SCC2_REGS, SCC3_REGS, SCC4_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) scc_base_addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 	.long SCC1_BASE, SCC2_BASE, SCC3_BASE, SCC4_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) tx_first_bd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 	.long DPRBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 	.long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 	.long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8 * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 	.long DPRBASE + (TX_BUFFERS + RX_BUFFERS) * 8 * 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) rx_first_bd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 	.long DPRBASE + TX_BUFFERS * 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 	.long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 	.long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8 * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 	.long DPRBASE + TX_BUFFERS * 8 + (TX_BUFFERS + RX_BUFFERS) * 8 * 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) first_buffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 	.long BUFFERS_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 	.long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) 	.long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) 	.long BUFFERS_ADDR + (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) bell_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 	.long 1 << DOORBELL_FROM_CARD_TX_0, 1 << DOORBELL_FROM_CARD_TX_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 	.long 1 << DOORBELL_FROM_CARD_TX_2, 1 << DOORBELL_FROM_CARD_TX_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) bell_cable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) 	.long 1 << DOORBELL_FROM_CARD_CABLE_0, 1 << DOORBELL_FROM_CARD_CABLE_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 	.long 1 << DOORBELL_FROM_CARD_CABLE_2, 1 << DOORBELL_FROM_CARD_CABLE_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) packet_full:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) 	.long PACKET_FULL, PACKET_FULL + 1, PACKET_FULL + 2, PACKET_FULL + 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) clocking_ext:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) 	.long 0x0000002C, 0x00003E00, 0x002C0000, 0x3E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) clocking_txfromrx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) 	.long 0x0000002D, 0x00003F00, 0x002D0000, 0x3F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) clocking_mask:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 	.long 0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dcd_mask:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 	.word 0x020, 0, 0x080, 0, 0x200, 0, 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 	.ascii "wanXL firmware\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) 	.asciz "Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /****************************** variables *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) 		.align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) channel_stats:	.long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) tx_in:		.long 0, 0, 0, 0	// transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) tx_out:		.long 0, 0, 0, 0	// received from host for transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) tx_count:	.long 0, 0, 0, 0	// currently in transmit queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) rx_in:		.long 0, 0, 0, 0	// received from port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rx_out:		.long 0			// transmitted to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) parity_bytes:	.word 0, 0, 0, 0, 0, 0, 0 // only 4 words are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) csr_output:	.word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) old_csr_output:	.word 0, 0, 0, 0, 0, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) 		.align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) firmware_end:				// must be dword-aligned