^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * wanXL serial card driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * definitions common to host driver and card firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RESET_WHILE_LOADING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* you must rebuild the firmware if any of the following is changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DETECT_RAM 0 /* needed for > 4MB RAM, 16 MB maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define QUICC_MEMCPY_USES_PLX 1 /* must be used if the host has > 256 MB RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define STATUS_CABLE_V35 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STATUS_CABLE_X21 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STATUS_CABLE_V24 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STATUS_CABLE_EIA530 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STATUS_CABLE_INVALID 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STATUS_CABLE_NONE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STATUS_CABLE_DCE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STATUS_CABLE_DSR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STATUS_CABLE_DCD 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STATUS_CABLE_PM_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PDM_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TX_BUFFERS 10 /* per port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RX_BUFFERS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RX_QUEUE_LENGTH 40 /* card->host queue length - per card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PACKET_EMPTY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PACKET_FULL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PACKET_SENT 0x20 /* TX only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PACKET_UNDERRUN 0x30 /* TX only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PACKET_PORT_MASK 0x03 /* RX only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* bit numbers in PLX9060 doorbell registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DOORBELL_FROM_CARD_TX_0 0 /* packet sent by the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DOORBELL_FROM_CARD_TX_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DOORBELL_FROM_CARD_TX_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DOORBELL_FROM_CARD_TX_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DOORBELL_FROM_CARD_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DOORBELL_FROM_CARD_CABLE_0 5 /* cable/PM/etc. changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DOORBELL_FROM_CARD_CABLE_1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DOORBELL_FROM_CARD_CABLE_2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DOORBELL_FROM_CARD_CABLE_3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DOORBELL_TO_CARD_OPEN_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DOORBELL_TO_CARD_OPEN_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DOORBELL_TO_CARD_OPEN_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DOORBELL_TO_CARD_OPEN_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DOORBELL_TO_CARD_CLOSE_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DOORBELL_TO_CARD_CLOSE_1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DOORBELL_TO_CARD_CLOSE_2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DOORBELL_TO_CARD_CLOSE_3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DOORBELL_TO_CARD_TX_0 8 /* outbound packet queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DOORBELL_TO_CARD_TX_1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DOORBELL_TO_CARD_TX_2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DOORBELL_TO_CARD_TX_3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* firmware-only status bits, starting from last DOORBELL_TO_CARD + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TASK_SCC_0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TASK_SCC_1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TASK_SCC_2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TASK_SCC_3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ALIGN32(x) (((x) + 3) & 0xFFFFFFFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BUFFER_LENGTH ALIGN32(HDLC_MAX_MRU + 4) /* 4 bytes for 32-bit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Address of TX and RX buffers in 68360 address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BUFFERS_ADDR 0x4000 /* 16 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PLX_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PLX_OFFSET PLX + 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PLX_MAILBOX_0 (PLX_OFFSET + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PLX_MAILBOX_1 (PLX_OFFSET + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PLX_MAILBOX_2 (PLX_OFFSET + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PLX_MAILBOX_3 (PLX_OFFSET + 0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PLX_MAILBOX_4 (PLX_OFFSET + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PLX_MAILBOX_5 (PLX_OFFSET + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PLX_MAILBOX_6 (PLX_OFFSET + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PLX_MAILBOX_7 (PLX_OFFSET + 0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PLX_DOORBELL_TO_CARD (PLX_OFFSET + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PLX_DOORBELL_FROM_CARD (PLX_OFFSET + 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PLX_INTERRUPT_CS (PLX_OFFSET + 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PLX_CONTROL (PLX_OFFSET + 0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PLX_DMA_0_MODE (PLX + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PLX_DMA_0_PCI (PLX + 0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PLX_DMA_0_LOCAL (PLX + 0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PLX_DMA_0_LENGTH (PLX + 0x10C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PLX_DMA_0_DESC (PLX + 0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLX_DMA_1_MODE (PLX + 0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PLX_DMA_1_PCI (PLX + 0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PLX_DMA_1_LOCAL (PLX + 0x11C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PLX_DMA_1_LENGTH (PLX + 0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PLX_DMA_1_DESC (PLX + 0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PLX_DMA_CMD_STS (PLX + 0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PLX_DMA_ARBITR_0 (PLX + 0x12C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PLX_DMA_ARBITR_1 (PLX + 0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DESC_LENGTH 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* offsets from start of status_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* card to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STATUS_OPEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define STATUS_CABLE (STATUS_OPEN + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define STATUS_RX_OVERRUNS (STATUS_CABLE + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STATUS_RX_FRAME_ERRORS (STATUS_RX_OVERRUNS + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* host to card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define STATUS_PARITY (STATUS_RX_FRAME_ERRORS + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define STATUS_ENCODING (STATUS_PARITY + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define STATUS_CLOCKING (STATUS_ENCODING + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define STATUS_TX_DESCS (STATUS_CLOCKING + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) volatile u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 address; /* PCI address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) volatile u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }desc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) // Card to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) volatile u32 open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) volatile u32 cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) volatile u32 rx_overruns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) volatile u32 rx_frame_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) // Host to card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 clocking;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) desc_t tx_descs[TX_BUFFERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }port_status_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif /* __ASSEMBLER__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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