^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/tdm/line_ctrl/slic_ds26522.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Zhao Qiang <B45475@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DS26522_RF_ADDR_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DS26522_RF_ADDR_END 0xef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DS26522_GLB_ADDR_START 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DS26522_GLB_ADDR_END 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DS26522_TF_ADDR_START 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DS26522_TF_ADDR_END 0x1ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DS26522_LIU_ADDR_START 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DS26522_LIU_ADDR_END 0x101f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DS26522_TEST_ADDR_START 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DS26522_TEST_ADDR_END 0x101f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DS26522_BERT_ADDR_START 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DS26522_BERT_ADDR_END 0x110f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DS26522_RMMR_ADDR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DS26522_RCR1_ADDR 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DS26522_RCR3_ADDR 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DS26522_RIOCR_ADDR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DS26522_GTCR1_ADDR 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DS26522_GFCR_ADDR 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DS26522_GTCR2_ADDR 0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DS26522_GTCCR_ADDR 0xf3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DS26522_GLSRR_ADDR 0xf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DS26522_GFSRR_ADDR 0xf6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DS26522_IDR_ADDR 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DS26522_E1TAF_ADDR 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DS26522_E1TNAF_ADDR 0x165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DS26522_TMMR_ADDR 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DS26522_TCR1_ADDR 0x181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DS26522_TIOCR_ADDR 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DS26522_LTRCR_ADDR 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DS26522_LTITSR_ADDR 0x1001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DS26522_LMCR_ADDR 0x1002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DS26522_LRISMR_ADDR 0x1007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX_NUM_OF_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PQ_MDS_8E1T1_BRD_REV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PQ_MDS_8E1T1_PLD_REV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DS26522_GTCCR_BPREFSEL_REFCLKIN 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DS26522_GTCCR_BFREQSEL_1544KHZ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DS26522_GTCCR_FREQSEL_1544KHZ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DS26522_GTCCR_BFREQSEL_2048KHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DS26522_GTCCR_FREQSEL_2048KHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DS26522_GFCR_BPCLK_2048KHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DS26522_GTCR2_TSSYNCOUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS26522_GTCR1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DS26522_GFSRR_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DS26522_GFSRR_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DS26522_GLSRR_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DS26522_GLSRR_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DS26522_RMMR_SFTRST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DS26522_RMMR_FRM_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DS26522_RMMR_INIT_DONE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DS26522_RMMR_T1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DS26522_RMMR_E1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DS26522_E1TAF_DEFAULT 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DS26522_E1TNAF_DEFAULT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DS26522_TMMR_SFTRST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DS26522_TMMR_FRM_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DS26522_TMMR_INIT_DONE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DS26522_TMMR_T1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DS26522_TMMR_E1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DS26522_RCR1_T1_SYNCT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DS26522_RCR1_T1_RB8ZS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DS26522_RCR1_T1_SYNCC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DS26522_RCR1_E1_HDB3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DS26522_RCR1_E1_CCS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DS26522_RIOCR_1544KHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DS26522_RIOCR_2048KHZ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DS26522_RIOCR_RSIO_OUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DS26522_RCR3_FLB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DS26522_TIOCR_1544KHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DS26522_TIOCR_2048KHZ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DS26522_TIOCR_TSIO_OUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DS26522_TCR1_TB8ZS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DS26522_LTRCR_T1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DS26522_LTRCR_E1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DS26522_LTITSR_TLIS_75OHM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DS26522_LTITSR_LBOS_75OHM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DS26522_LTITSR_TLIS_100OHM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DS26522_LTITSR_TLIS_0DB_CSU 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DS26522_LRISMR_75OHM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DS26522_LRISMR_100OHM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DS26522_LRISMR_MAX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DS26522_LMCR_TE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum line_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) LINE_RATE_T1, /* T1 line rate (1.544 Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) LINE_RATE_E1 /* E1 line rate (2.048 Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enum tdm_trans_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) NORMAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FRAMER_LB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum card_support_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) LM_CARD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DS26522_CARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) NO_CARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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