^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* sbni.h: definitions for a Granch SBNI12 driver, version 5.0.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Written 2001 Denis I.Timofeev (timofeev@granch.ru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file is distributed under the GNU GPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef SBNI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define SBNI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifdef SBNI_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DP( A ) A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DP( A )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* We don't have official vendor id yet... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SBNI_PCI_VENDOR 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SBNI_PCI_DEVICE 0x9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ISA_MODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SBNI_IO_EXTENT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum sbni_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) CSR0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) CSR1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DAT = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* CSR0 mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) BU_EMP = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RC_CHK = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CT_ZER = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) TR_REQ = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) TR_RDY = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) EN_INT = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RC_RDY = 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* CSR1 mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PR_RES 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct sbni_csr1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef __LITTLE_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 rxl : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 rate : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 rate : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 rxl : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* fields in frame header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FRAME_ACK_MASK (unsigned short)0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FRAME_LEN_MASK (unsigned short)0x03FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FRAME_FIRST (unsigned short)0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FRAME_RETRY (unsigned short)0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FRAME_SENT_BAD (unsigned short)0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FRAME_SENT_OK (unsigned short)0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* state flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FL_WAIT_ACK = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FL_NEED_RESEND = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FL_PREV_OK = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FL_SLOW_MODE = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FL_SECONDARY = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_SBNI_MULTILINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FL_SLAVE = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FL_LINE_DOWN = 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEFAULT_IOBASEADDR = 0x210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEFAULT_INTERRUPTNUMBER = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEFAULT_RATE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEFAULT_FRAME_LEN = 1012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DEF_RXL_DELTA -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEF_RXL 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SBNI_SIG 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SBNI_MIN_LEN 60 /* Shortest Ethernet frame without FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SBNI_MAX_FRAME 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ETHER_MAX_LEN 1518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SBNI_TIMEOUT (HZ/10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TR_ERROR_COUNT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CHANGE_LEVEL_START_TICKS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SBNI_MAX_NUM_CARDS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* internal SBNI-specific statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct sbni_in_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 all_rx_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 bad_rx_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 timeout_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 all_tx_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 resend_tx_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* SBNI ioctl params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SIOCDEVGETINSTATS SIOCDEVPRIVATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SIOCDEVRESINSTATS SIOCDEVPRIVATE+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SIOCDEVGHWSTATE SIOCDEVPRIVATE+2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SIOCDEVSHWSTATE SIOCDEVPRIVATE+3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SIOCDEVENSLAVE SIOCDEVPRIVATE+4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SIOCDEVEMANSIPATE SIOCDEVPRIVATE+5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* data packet for SIOCDEVGHWSTATE/SIOCDEVSHWSTATE ioctl requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct sbni_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 rxl : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 rate : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 fixed_rxl : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 slow_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 mac_addr : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * CRC-32 stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CRC32(c,crc) (crc32tab[((size_t)(crc) ^ (c)) & 0xff] ^ (((crc) >> 8) & 0x00FFFFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* CRC generator 0xEDB88320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* CRC remainder 0x2144DF1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* CRC initial value 0x00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CRC32_REMAINDER 0x2144DF1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CRC32_INITIAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #ifndef __initdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define __initdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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