^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Goramo PCI200SYN synchronous serial card driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002-2008 Krzysztof Halasa <khc@pm.waw.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Sources of information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Hitachi HD64572 SCA-II User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * PLX Technology Inc. PCI9052 Data Book
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/hdlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "hd64572.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #undef DEBUG_PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCI200SYN_PLX_SIZE 0x80 /* PLX control window size (128b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCI200SYN_SCA_SIZE 0x400 /* SCA window size (1Kb) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX_TX_BUFFERS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int pci_clock_freq = 33000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLOCK_BASE pci_clock_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * PLX PCI9052 local configuration and shared runtime registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * This structure can be used to access 9052 registers (memory mapped).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 loc_rom_range; /* 10h : Local ROM Range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 loc_rom_base; /* 24h : Local ROM Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }plx9052;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) typedef struct port_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct card_s *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) spinlock_t lock; /* TX lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sync_serial_settings settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int rxpart; /* partial frame received, next frame invalid*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned short encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned short parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u16 rxin; /* rx ring buffer 'in' pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 txin; /* tx ring buffer 'in' and 'last' pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 txlast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 rxs, txs, tmc; /* SCA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 chan; /* physical port # - 0 or 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }port_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) typedef struct card_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 __iomem *rambase; /* buffer memory base (virtual) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 __iomem *scabase; /* SCA memory base (virtual) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) plx9052 __iomem *plxbase;/* PLX registers memory base (virtual) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 rx_ring_buffers; /* number of buffers in a ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u16 buff_offset; /* offset of first buffer of first channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 irq; /* interrupt request level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) port_t ports[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }card_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define get_port(card, port) (&card->ports[port])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define sca_flush(card) (sca_in(IER0, card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline void new_memcpy_toio(char __iomem *dest, char *src, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) len = length > 256 ? 256 : length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) memcpy_toio(dest, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dest += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) src += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) length -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) readb(dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } while (len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #undef memcpy_toio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define memcpy_toio new_memcpy_toio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #include "hd64572.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void pci200_set_iface(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) card_t *card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 rxs = port->rxs & CLK_BRG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 txs = port->txs & CLK_BRG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) port->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch(port->settings.clock_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case CLOCK_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rxs |= CLK_BRG; /* BRG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case CLOCK_TXINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rxs |= CLK_LINE; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case CLOCK_TXFROMRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rxs |= CLK_LINE; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) default: /* EXTernal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rxs |= CLK_LINE; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) port->rxs = rxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) port->txs = txs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sca_out(rxs, msci + RXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sca_out(txs, msci + TXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sca_set_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int pci200_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int result = hdlc_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sca_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pci200_set_iface(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sca_flush(port->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int pci200_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sca_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sca_flush(dev_to_port(dev)->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) hdlc_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const size_t size = sizeof(sync_serial_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) sync_serial_settings new_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #ifdef DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (cmd == SIOCDEVPRIVATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sca_dump_rings(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (cmd != SIOCWANDEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) switch(ifr->ifr_settings.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case IF_GET_IFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ifr->ifr_settings.type = IF_IFACE_V35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ifr->ifr_settings.size < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ifr->ifr_settings.size = size; /* data size wanted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (copy_to_user(line, &port->settings, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case IF_IFACE_V35:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case IF_IFACE_SYNC_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (copy_from_user(&new_line, line, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (new_line.clock_type != CLOCK_EXT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) new_line.clock_type != CLOCK_TXFROMRX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) new_line.clock_type != CLOCK_INT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) new_line.clock_type != CLOCK_TXINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -EINVAL; /* No such clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (new_line.loopback != 0 && new_line.loopback != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) memcpy(&port->settings, &new_line, size); /* Update settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pci200_set_iface(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sca_flush(port->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void pci200_pci_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) card_t *card = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (card->ports[i].card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unregister_hdlc_device(card->ports[i].netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (card->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) free_irq(card->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (card->rambase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) iounmap(card->rambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (card->scabase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) iounmap(card->scabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (card->plxbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) iounmap(card->plxbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (card->ports[0].netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) free_netdev(card->ports[0].netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (card->ports[1].netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) free_netdev(card->ports[1].netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct net_device_ops pci200_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .ndo_open = pci200_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .ndo_stop = pci200_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .ndo_start_xmit = hdlc_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .ndo_do_ioctl = pci200_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int pci200_pci_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) card_t *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 __iomem *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 ramsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 ramphys; /* buffer memory base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 scaphys; /* SCA memory base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 plxphys; /* PLX registers memory base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) i = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) i = pci_request_regions(pdev, "PCI200SYN");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) card = kzalloc(sizeof(card_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (card == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pci_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) card->ports[0].netdev = alloc_hdlcdev(&card->ports[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) card->ports[1].netdev = alloc_hdlcdev(&card->ports[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!card->ports[0].netdev || !card->ports[1].netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pr_err("unable to allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pci200_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pci_resource_len(pdev, 3) < 16384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pr_err("invalid card EEPROM parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pci200_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) card->rambase = pci_ioremap_bar(pdev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (card->plxbase == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) card->scabase == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) card->rambase == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pr_err("ioremap() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pci200_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Reset PLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) p = &card->plxbase->init_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(readl(p) | 0x40000000, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) readl(p); /* Flush the write - do not use sca_flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(readl(p) & ~0x40000000, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) readl(p); /* Flush the write - do not use sca_flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ramsize = sca_detect_ram(card, card->rambase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pci_resource_len(pdev, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* number of TX + RX buffers for one port - this is dual port card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) card->rx_ring_buffers = i - card->tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) card->rx_ring_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pr_info("%u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ramsize / 1024, ramphys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (card->tx_ring_buffers < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pr_err("RAM test failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pci200_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Enable interrupts on the PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) p = &card->plxbase->intr_ctrl_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writew(readw(p) | 0x0040, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Allocate IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pci200syn", card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pr_warn("could not allocate IRQ%d\n", pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pci200_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) card->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sca_init(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) port_t *port = &card->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct net_device *dev = port->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) hdlc_device *hdlc = dev_to_hdlc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) port->chan = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev->irq = card->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev->mem_start = ramphys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev->mem_end = ramphys + ramsize - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev->tx_queue_len = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev->netdev_ops = &pci200_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hdlc->attach = sca_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) hdlc->xmit = sca_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) port->settings.clock_type = CLOCK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) port->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sca_init_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (register_hdlc_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pr_err("unable to register hdlc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) port->card = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pci200_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) netdev_info(dev, "PCI200SYN channel %d\n", port->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sca_flush(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct pci_device_id pci200_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PCI_DEVICE_ID_PLX_PCI200SYN, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct pci_driver pci200_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .name = "PCI200SYN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .id_table = pci200_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .probe = pci200_pci_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .remove = pci200_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int __init pci200_init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pr_err("Invalid PCI clock frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return pci_register_driver(&pci200_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void __exit pci200_cleanup_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pci_unregister_driver(&pci200_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_DEVICE_TABLE(pci, pci200_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) module_param(pci_clock_freq, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) module_init(pci200_init_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) module_exit(pci200_cleanup_module);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags