^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cyclades PC300 synchronous serial card driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Sources of information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Hitachi HD64572 SCA-II User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Original Cyclades PC300 Linux driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This driver currently supports only PC300/RSV (V.24/V.35) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * PC300/X21 cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/hdlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "hd64572.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #undef DEBUG_PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PC300_PLX_SIZE 0x80 /* PLX control window size (128 B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PC300_SCA_SIZE 0x400 /* SCA window size (1 KB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX_TX_BUFFERS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int pci_clock_freq = 33000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int use_crystal_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static unsigned int CLOCK_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Masks to access the init_ctrl PLX register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PC300_CLKSEL_MASK (0x00000004UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PC300_CTYPE_MASK (0x00000800UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * PLX PCI9050-1 local configuration and shared runtime registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * This structure can be used to access 9050 registers (memory mapped).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 loc_rom_range; /* 10h : Local ROM Range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 loc_rom_base; /* 24h : Local ROM Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }plx9050;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) typedef struct port_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct card_s *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) spinlock_t lock; /* TX lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) sync_serial_settings settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int rxpart; /* partial frame received, next frame invalid*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned short encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned short parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 rxin; /* rx ring buffer 'in' pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u16 txin; /* tx ring buffer 'in' and 'last' pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u16 txlast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 rxs, txs, tmc; /* SCA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 chan; /* physical port # - 0 or 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }port_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) typedef struct card_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int type; /* RSV, X21, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int n_ports; /* 1 or 2 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 __iomem *rambase; /* buffer memory base (virtual) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 __iomem *scabase; /* SCA memory base (virtual) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 init_ctrl_value; /* Saved value - 9050 bug workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 rx_ring_buffers; /* number of buffers in a ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 buff_offset; /* offset of first buffer of first channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 irq; /* interrupt request level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) port_t ports[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }card_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define get_port(card, port) ((port) < (card)->n_ports ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (&(card)->ports[port]) : (NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #include "hd64572.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void pc300_set_iface(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) card_t *card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 __iomem * init_ctrl = &card->plxbase->init_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u16 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 rxs = port->rxs & CLK_BRG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 txs = port->txs & CLK_BRG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) port->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) switch(port->settings.clock_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case CLOCK_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rxs |= CLK_BRG; /* BRG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case CLOCK_TXINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rxs |= CLK_LINE; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case CLOCK_TXFROMRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rxs |= CLK_LINE; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) default: /* EXTernal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rxs |= CLK_LINE; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) port->rxs = rxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) port->txs = txs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sca_out(rxs, msci + RXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sca_out(txs, msci + TXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sca_set_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (port->card->type == PC300_RSV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (port->iface == IF_IFACE_V35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel(card->init_ctrl_value |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PC300_CHMEDIA_MASK(port->chan), init_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel(card->init_ctrl_value &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ~PC300_CHMEDIA_MASK(port->chan), init_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int pc300_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int result = hdlc_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sca_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pc300_set_iface(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int pc300_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sca_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) hdlc_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const size_t size = sizeof(sync_serial_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sync_serial_settings new_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int new_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (cmd == SIOCDEVPRIVATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sca_dump_rings(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (cmd != SIOCWANDEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ifr->ifr_settings.type == IF_GET_IFACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ifr->ifr_settings.type = port->iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ifr->ifr_settings.size < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ifr->ifr_settings.size = size; /* data size wanted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (copy_to_user(line, &port->settings, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (port->card->type == PC300_X21 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ifr->ifr_settings.type == IF_IFACE_X21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) new_type = IF_IFACE_X21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else if (port->card->type == PC300_RSV &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ifr->ifr_settings.type == IF_IFACE_V35))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) new_type = IF_IFACE_V35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else if (port->card->type == PC300_RSV &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ifr->ifr_settings.type == IF_IFACE_V24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) new_type = IF_IFACE_V24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (copy_from_user(&new_line, line, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (new_line.clock_type != CLOCK_EXT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) new_line.clock_type != CLOCK_TXFROMRX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) new_line.clock_type != CLOCK_INT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) new_line.clock_type != CLOCK_TXINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EINVAL; /* No such clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (new_line.loopback != 0 && new_line.loopback != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) memcpy(&port->settings, &new_line, size); /* Update settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) port->iface = new_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pc300_set_iface(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void pc300_pci_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) card_t *card = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (card->ports[i].card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unregister_hdlc_device(card->ports[i].netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (card->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) free_irq(card->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (card->rambase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) iounmap(card->rambase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (card->scabase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) iounmap(card->scabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (card->plxbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) iounmap(card->plxbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (card->ports[0].netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) free_netdev(card->ports[0].netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (card->ports[1].netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) free_netdev(card->ports[1].netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct net_device_ops pc300_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .ndo_open = pc300_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .ndo_stop = pc300_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .ndo_start_xmit = hdlc_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .ndo_do_ioctl = pc300_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int pc300_pci_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) card_t *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 __iomem *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 ramsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 ramphys; /* buffer memory base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 scaphys; /* SCA memory base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 plxphys; /* PLX registers memory base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) i = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) i = pci_request_regions(pdev, "PC300");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) card = kzalloc(sizeof(card_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (card == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pci_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pci_resource_len(pdev, 3) < 16384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pr_err("invalid card EEPROM parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pc300_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) card->plxbase = ioremap(plxphys, PC300_PLX_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) card->scabase = ioremap(scaphys, PC300_SCA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) card->rambase = pci_ioremap_bar(pdev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (card->plxbase == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) card->scabase == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) card->rambase == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pr_err("ioremap() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pc300_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* PLX PCI 9050 workaround for local configuration register read bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pdev->device == PCI_DEVICE_ID_PC300_TE_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) card->type = PC300_TE; /* not fully supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else if (card->init_ctrl_value & PC300_CTYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) card->type = PC300_X21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) card->type = PC300_RSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pdev->device == PCI_DEVICE_ID_PC300_TE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) card->n_ports = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) card->n_ports = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (i = 0; i < card->n_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!(card->ports[i].netdev = alloc_hdlcdev(&card->ports[i]))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pr_err("unable to allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pc300_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Reset PLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) p = &card->plxbase->init_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(card->init_ctrl_value | 0x40000000, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) readl(p); /* Flush the write - do not use sca_flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(card->init_ctrl_value, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) readl(p); /* Flush the write - do not use sca_flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Reload Config. Registers from EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) writel(card->init_ctrl_value | 0x20000000, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) readl(p); /* Flush the write - do not use sca_flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) writel(card->init_ctrl_value, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) readl(p); /* Flush the write - do not use sca_flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ramsize = sca_detect_ram(card, card->rambase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pci_resource_len(pdev, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (use_crystal_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) card->init_ctrl_value &= ~PC300_CLKSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) card->init_ctrl_value |= PC300_CLKSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* number of TX + RX buffers for one port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) card->rx_ring_buffers = i - card->tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) card->buff_offset = card->n_ports * sizeof(pkt_desc) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) (card->tx_ring_buffers + card->rx_ring_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pr_info("PC300/%s, %u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) card->type == PC300_X21 ? "X21" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) card->type == PC300_TE ? "TE" : "RSV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ramsize / 1024, ramphys, pdev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) card->tx_ring_buffers, card->rx_ring_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (card->tx_ring_buffers < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pr_err("RAM test failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pc300_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Enable interrupts on the PCI bridge, LINTi1 active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writew(0x0041, &card->plxbase->intr_ctrl_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Allocate IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pr_warn("could not allocate IRQ%d\n", pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pc300_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) card->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sca_init(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) // COTE not set - allows better TX DMA settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sca_out(0x10, BTCR, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for (i = 0; i < card->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) port_t *port = &card->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct net_device *dev = port->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) hdlc_device *hdlc = dev_to_hdlc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) port->chan = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev->irq = card->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev->mem_start = ramphys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev->mem_end = ramphys + ramsize - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev->tx_queue_len = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev->netdev_ops = &pc300_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hdlc->attach = sca_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) hdlc->xmit = sca_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) port->settings.clock_type = CLOCK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) port->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (card->type == PC300_X21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) port->iface = IF_IFACE_X21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) port->iface = IF_IFACE_V35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) sca_init_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (register_hdlc_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pr_err("unable to register hdlc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) port->card = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pc300_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) netdev_info(dev, "PC300 channel %d\n", port->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct pci_device_id pc300_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static struct pci_driver pc300_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .name = "PC300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .id_table = pc300_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .probe = pc300_pci_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .remove = pc300_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int __init pc300_init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pr_err("Invalid PCI clock frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (use_crystal_clock != 0 && use_crystal_clock != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pr_err("Invalid 'use_crystal_clock' value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return pci_register_driver(&pc300_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void __exit pc300_cleanup_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pci_unregister_driver(&pc300_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MODULE_DESCRIPTION("Cyclades PC300 serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_DEVICE_TABLE(pci, pc300_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) module_param(pci_clock_freq, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) module_param(use_crystal_clock, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_PARM_DESC(use_crystal_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "Use 24.576 MHz clock instead of PCI clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) module_init(pc300_init_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) module_exit(pc300_cleanup_module);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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