^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SDL Inc. RISCom/N2 synchronous serial card driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Note: integrated CSU/DSU/DDS are not supported by this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Sources of information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Hitachi HD64570 SCA User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * SDL Inc. PPP/HDLC/CISCO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/hdlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "hd64570.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char* version = "SDL RISCom/N2 driver version: 1.15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char* devname = "RISCom/N2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #undef DEBUG_PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USE_WINDOWSIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USE_BUS16BITS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLOCK_BASE 9830400 /* 9.8304 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAX_PAGES 16 /* 16 RAM pages at max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX_RAM_SIZE 0x80000 /* 512 KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #if MAX_RAM_SIZE > MAX_PAGES * USE_WINDOWSIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #undef MAX_RAM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX_RAM_SIZE (MAX_PAGES * USE_WINDOWSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define N2_IOPORTS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NEED_DETECT_RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NEED_SCA_MSCI_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX_TX_BUFFERS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static char *hw; /* pointer to hw=xxx command line string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* RISCom/N2 Board Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* PC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define N2_PCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCR_RUNSCA 1 /* Run 64570 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCR_VPM 2 /* Enable VPM - needed if using RAM above 1 MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCR_ENWIN 4 /* Open window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCR_BUS16 8 /* 16-bit bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Memory Base Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define N2_BAR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Page Scan Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define N2_PSR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WIN16K 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WIN32K 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WIN64K 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PSR_WINBITS 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PSR_DMAEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PSR_PAGEBITS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Modem Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define N2_MCR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLOCK_OUT_PORT1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLOCK_OUT_PORT0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TX422_PORT1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TX422_PORT0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DSR_PORT1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DSR_PORT0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DTR_PORT1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DTR_PORT0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) typedef struct port_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct card_s *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spinlock_t lock; /* TX lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) sync_serial_settings settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int valid; /* port enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int rxpart; /* partial frame received, next frame invalid*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned short encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned short parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 rxin; /* rx ring buffer 'in' pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 txin; /* tx ring buffer 'in' and 'last' pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 txlast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 rxs, txs, tmc; /* SCA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 phy_node; /* physical port # - 0 or 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 log_node; /* logical port # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }port_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) typedef struct card_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 __iomem *winbase; /* ISA window base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 phy_winbase; /* ISA physical base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 ram_size; /* number of bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u16 io; /* IO Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 buff_offset; /* offset of first buffer of first channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 rx_ring_buffers; /* number of buffers in a ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 irq; /* IRQ (3-15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) port_t ports[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct card_s *next_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }card_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static card_t *first_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static card_t **new_card = &first_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define sca_reg(reg, card) (0x8000 | (card)->io | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ((reg) & 0x0F) | (((reg) & 0xF0) << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define sca_in(reg, card) inb(sca_reg(reg, card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define sca_out(value, reg, card) outb(value, sca_reg(reg, card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define sca_inw(reg, card) inw(sca_reg(reg, card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define sca_outw(value, reg, card) outw(value, sca_reg(reg, card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define port_to_card(port) ((port)->card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define log_node(port) ((port)->log_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define phy_node(port) ((port)->phy_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define winsize(card) (USE_WINDOWSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define winbase(card) ((card)->winbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define get_port(card, port) ((card)->ports[port].valid ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &(card)->ports[port] : NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static __inline__ u8 sca_get_page(card_t *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return inb(card->io + N2_PSR) & PSR_PAGEBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static __inline__ void openwin(card_t *card, u8 page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 psr = inb(card->io + N2_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #include "hd64570.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void n2_set_iface(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) card_t *card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int io = card->io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 mcr = inb(io + N2_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 rxs = port->rxs & CLK_BRG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 txs = port->txs & CLK_BRG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) switch(port->settings.clock_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case CLOCK_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rxs |= CLK_BRG_RX; /* BRG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) txs |= CLK_RXCLK_TX; /* RX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case CLOCK_TXINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rxs |= CLK_LINE_RX; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) txs |= CLK_BRG_TX; /* BRG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case CLOCK_TXFROMRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rxs |= CLK_LINE_RX; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) txs |= CLK_RXCLK_TX; /* RX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) default: /* Clock EXTernal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rxs |= CLK_LINE_RX; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) txs |= CLK_LINE_TX; /* TXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) outb(mcr, io + N2_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) port->rxs = rxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) port->txs = txs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sca_out(rxs, msci + RXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sca_out(txs, msci + TXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sca_set_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int n2_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int io = port->card->io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) result = hdlc_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) outb(mcr, io + N2_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) sca_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) n2_set_iface(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int n2_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int io = port->card->io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sca_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) outb(mcr, io + N2_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) hdlc_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int n2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) const size_t size = sizeof(sync_serial_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) sync_serial_settings new_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #ifdef DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (cmd == SIOCDEVPRIVATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) sca_dump_rings(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (cmd != SIOCWANDEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) switch(ifr->ifr_settings.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case IF_GET_IFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ifr->ifr_settings.size < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ifr->ifr_settings.size = size; /* data size wanted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (copy_to_user(line, &port->settings, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case IF_IFACE_SYNC_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if(!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (copy_from_user(&new_line, line, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (new_line.clock_type != CLOCK_EXT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) new_line.clock_type != CLOCK_TXFROMRX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) new_line.clock_type != CLOCK_INT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) new_line.clock_type != CLOCK_TXINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -EINVAL; /* No such clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (new_line.loopback != 0 && new_line.loopback != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) memcpy(&port->settings, &new_line, size); /* Update settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) n2_set_iface(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void n2_destroy_card(card_t *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (cnt = 0; cnt < 2; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (card->ports[cnt].card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct net_device *dev = port_to_dev(&card->ports[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unregister_hdlc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (card->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) free_irq(card->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (card->winbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) iounmap(card->winbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) release_mem_region(card->phy_winbase, USE_WINDOWSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (card->io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) release_region(card->io, N2_IOPORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (card->ports[0].dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) free_netdev(card->ports[0].dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (card->ports[1].dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) free_netdev(card->ports[1].dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct net_device_ops n2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ndo_open = n2_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .ndo_stop = n2_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .ndo_start_xmit = hdlc_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .ndo_do_ioctl = n2_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int __init n2_run(unsigned long io, unsigned long irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned long winbase, long valid0, long valid1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) card_t *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 cnt, pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pr_err("invalid I/O port value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (irq < 3 || irq > 15 || irq == 6) /* FIXME */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pr_err("invalid IRQ value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pr_err("invalid RAM value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) card = kzalloc(sizeof(card_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (card == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) card->ports[0].dev = alloc_hdlcdev(&card->ports[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) card->ports[1].dev = alloc_hdlcdev(&card->ports[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!card->ports[0].dev || !card->ports[1].dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pr_err("unable to allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) n2_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!request_region(io, N2_IOPORTS, devname)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pr_err("I/O port region in use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) n2_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) card->io = io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (request_irq(irq, sca_intr, 0, devname, card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pr_err("could not allocate IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) n2_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) card->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pr_err("could not request RAM window\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) n2_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) card->phy_winbase = winbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) card->winbase = ioremap(winbase, USE_WINDOWSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!card->winbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) pr_err("ioremap() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) n2_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) outb(0, io + N2_PCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) outb(winbase >> 12, io + N2_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) switch (USE_WINDOWSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case 16384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) outb(WIN16K, io + N2_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 32768:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) outb(WIN32K, io + N2_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case 65536:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) outb(WIN64K, io + N2_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pr_err("invalid window size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) n2_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) outb(pcr, io + N2_PCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) card->ram_size = sca_detect_ram(card, card->winbase, MAX_RAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* number of TX + RX buffers for one port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) i = card->ram_size / ((valid0 + valid1) * (sizeof(pkt_desc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) HDLC_MAX_MRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) card->rx_ring_buffers = i - card->tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) card->buff_offset = (valid0 + valid1) * sizeof(pkt_desc) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) (card->tx_ring_buffers + card->rx_ring_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pr_info("RISCom/N2 %u KB RAM, IRQ%u, using %u TX + %u RX packets rings\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) card->ram_size / 1024, card->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) card->tx_ring_buffers, card->rx_ring_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (card->tx_ring_buffers < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pr_err("RAM test failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) n2_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pcr |= PCR_RUNSCA; /* run SCA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) outb(pcr, io + N2_PCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) outb(0, io + N2_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) sca_init(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) for (cnt = 0; cnt < 2; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) port_t *port = &card->ports[cnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct net_device *dev = port_to_dev(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) hdlc_device *hdlc = dev_to_hdlc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) port->phy_node = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) port->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if ((cnt == 1) && valid0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) port->log_node = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev->mem_start = winbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev->mem_end = winbase + USE_WINDOWSIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev->tx_queue_len = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev->netdev_ops = &n2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) hdlc->attach = sca_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hdlc->xmit = sca_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) port->settings.clock_type = CLOCK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) port->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (register_hdlc_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pr_warn("unable to register hdlc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) port->card = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) n2_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) sca_init_port(port); /* Set up SCA memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) netdev_info(dev, "RISCom/N2 node %d\n", port->phy_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) *new_card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) new_card = &card->next_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int __init n2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (hw==NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pr_info("no card initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EINVAL; /* no parameters specified, abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pr_info("%s\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long io, irq, ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) long valid[2] = { 0, 0 }; /* Default = both ports disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) io = simple_strtoul(hw, &hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (*hw++ != ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) irq = simple_strtoul(hw, &hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (*hw++ != ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ram = simple_strtoul(hw, &hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (*hw++ != ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) while(1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (*hw == '0' && !valid[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) valid[0] = 1; /* Port 0 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) else if (*hw == '1' && !valid[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) valid[1] = 1; /* Port 1 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!valid[0] && !valid[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break; /* at least one port must be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (*hw == ':' || *hw == '\x0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) n2_run(io, irq, ram, valid[0], valid[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (*hw == '\x0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return first_card ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }while(*hw++ == ':');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pr_err("invalid hardware parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return first_card ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void __exit n2_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) card_t *card = first_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) while (card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) card_t *ptr = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) card = card->next_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) n2_destroy_card(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) module_init(n2_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) module_exit(n2_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MODULE_DESCRIPTION("RISCom/N2 serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) module_param(hw, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MODULE_PARM_DESC(hw, "io,irq,ram,ports:io,irq,...");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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