^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hitachi (now Renesas) SCA-II HD64572 driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Source of information: HD64572 SCA-II User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * We use the following SCA memory map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Packet buffer descriptor rings - starting from card->rambase:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Packet data buffers - starting from card->rambase + buff_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/hdlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "hd64572.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NAPI_WEIGHT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define get_msci(port) (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define get_dmac_rx(port) (port->chan ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define get_dmac_tx(port) (port->chan ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define sca_in(reg, card) readb(card->scabase + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define sca_out(value, reg, card) writeb(value, card->scabase + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define sca_inw(reg, card) readw(card->scabase + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define sca_outw(value, reg, card) writew(value, card->scabase + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define sca_inl(reg, card) readl(card->scabase + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define sca_outl(value, reg, card) writel(value, card->scabase + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int sca_poll(struct napi_struct *napi, int budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline port_t* dev_to_port(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return dev_to_hdlc(dev)->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline void enable_intr(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* enable DMIB and MSCI RXINTA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) sca_outl(sca_inl(IER0, port->card) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (port->chan ? 0x08002200 : 0x00080022), IER0, port->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline void disable_intr(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) sca_outl(sca_inl(IER0, port->card) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (port->chan ? 0x00FF00FF : 0xFF00FF00), IER0, port->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 rx_buffs = port->card->rx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u16 tx_buffs = port->card->tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return port->chan * (rx_buffs + tx_buffs) + transmit * rx_buffs + desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Descriptor offset always fits in 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return (pkt_desc __iomem *)(port->card->rambase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) desc_offset(port, desc, transmit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return port->card->buff_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline void sca_set_carrier(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!(sca_in(get_msci(port) + ST3, port->card) & ST3_DCD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef DEBUG_LINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) printk(KERN_DEBUG "%s: sca_set_carrier on\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) port->netdev.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) netif_carrier_on(port->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifdef DEBUG_LINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) printk(KERN_DEBUG "%s: sca_set_carrier off\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) port->netdev.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) netif_carrier_off(port->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void sca_init_port(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) card_t *card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u16 dmac_rx = get_dmac_rx(port), dmac_tx = get_dmac_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int transmit, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) port->rxin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) port->txin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) port->txlast = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for (transmit = 0; transmit < 2; transmit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 buffs = transmit ? card->tx_ring_buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) : card->rx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (i = 0; i < buffs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pkt_desc __iomem *desc = desc_address(port, i, transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 chain_off = desc_offset(port, i + 1, transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 buff_off = buffer_offset(port, i, transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(chain_off, &desc->cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(buff_off, &desc->bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writew(0, &desc->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writeb(0, &desc->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* DMA disable - to halt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sca_out(0, DSR_RX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sca_out(0, DSR_TX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* software ABORT - to initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sca_out(DCR_ABORT, DCR_RX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) sca_out(DCR_ABORT, DCR_TX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* current desc addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sca_outl(desc_offset(port, 0, 0), dmac_rx + CDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) sca_outl(desc_offset(port, card->tx_ring_buffers - 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dmac_rx + EDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sca_outl(desc_offset(port, 0, 1), dmac_tx + CDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sca_outl(desc_offset(port, 0, 1), dmac_tx + EDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* clear frame end interrupt counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) sca_out(DCR_CLEAR_EOF, DCR_RX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) sca_out(DCR_CLEAR_EOF, DCR_TX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) sca_outw(HDLC_MAX_MRU, dmac_rx + BFLL, card); /* set buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sca_out(0x14, DMR_RX(port->chan), card); /* Chain mode, Multi-frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sca_out(DIR_EOME, DIR_RX(port->chan), card); /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sca_out(DSR_DE, DSR_RX(port->chan), card); /* DMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sca_out(0x14, DMR_TX(port->chan), card); /* Chain mode, Multi-frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sca_out(DIR_EOME, DIR_TX(port->chan), card); /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sca_set_carrier(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) netif_napi_add(port->netdev, &port->napi, sca_poll, NAPI_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* MSCI interrupt service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline void sca_msci_intr(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u16 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) card_t* card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (sca_in(msci + ST1, card) & ST1_CDCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Reset MSCI CDCD status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sca_out(ST1_CDCD, msci + ST1, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sca_set_carrier(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u16 rxin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct net_device *dev = port->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) len = readw(&desc->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) skb = dev_alloc_skb(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) buff = buffer_offset(port, rxin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) memcpy_fromio(skb->data, card->rambase + buff, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef DEBUG_PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) debug_frame(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev->stats.rx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) skb->protocol = hdlc_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Receive DMA service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static inline int sca_rx_done(port_t *port, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct net_device *dev = port->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 dmac = get_dmac_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) card_t *card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int received = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Reset DSR status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DSR_RX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (stat & DSR_BOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Dropped one or more frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) while (received < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 desc_off = desc_offset(port, port->rxin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pkt_desc __iomem *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 cda = sca_inl(dmac + CDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break; /* No frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) desc = desc_address(port, port->rxin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) stat = readb(&desc->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!(stat & ST_RX_EOM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) port->rxpart = 1; /* partial frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) else if ((stat & ST_ERROR_MASK) || port->rxpart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (stat & ST_RX_OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ST_RX_RESBIT)) || port->rxpart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) else if (stat & ST_RX_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (stat & ST_RX_EOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) port->rxpart = 0; /* received last fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sca_rx(card, port, desc, port->rxin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) received++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Set new error descriptor address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sca_outl(desc_off, dmac + EDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) port->rxin = (port->rxin + 1) % card->rx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* make sure RX DMA is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) sca_out(DSR_DE, DSR_RX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Transmit DMA service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static inline void sca_tx_done(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct net_device *dev = port->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) card_t* card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) stat = sca_in(DSR_TX(port->chan), card); /* read DMA Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Reset DSR status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DSR_TX(port->chan), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pkt_desc __iomem *desc = desc_address(port, port->txlast, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 stat = readb(&desc->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!(stat & ST_TX_OWNRSHP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break; /* not yet transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (stat & ST_TX_UNDRRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev->stats.tx_bytes += readw(&desc->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writeb(0, &desc->stat); /* Free descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) port->txlast = (port->txlast + 1) % card->tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int sca_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) port_t *port = container_of(napi, port_t, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 isr0 = sca_inl(ISR0, port->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int received = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (isr0 & (port->chan ? 0x08000000 : 0x00080000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) sca_msci_intr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (isr0 & (port->chan ? 0x00002000 : 0x00000020))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) sca_tx_done(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (isr0 & (port->chan ? 0x00000200 : 0x00000002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) received = sca_rx_done(port, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (received < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) napi_complete_done(napi, received);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) enable_intr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static irqreturn_t sca_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) card_t *card = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 isr0 = sca_inl(ISR0, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int i, handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) port_t *port = get_port(card, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (port && (isr0 & (i ? 0x08002200 : 0x00080022))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) disable_intr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) napi_schedule(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static void sca_set_port(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) card_t* card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u16 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 md2 = sca_in(msci + MD2, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int tmc, br = 10, brv = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (port->settings.clock_rate > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Try lower br for better accuracy*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) br--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) brv >>= 1; /* brv = 2^9 = 512 max in specs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) tmc = CLOCK_BASE / brv / port->settings.clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }while (br > 1 && tmc <= 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (tmc < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tmc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) brv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else if (tmc > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) tmc = 256; /* tmc=0 means 256 - low baud rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) port->settings.clock_rate = CLOCK_BASE / brv / tmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) br = 9; /* Minimum clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) tmc = 256; /* 8bit = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) port->settings.clock_rate = CLOCK_BASE / (256 * 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) port->txs = (port->txs & ~CLK_BRG_MASK) | br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) port->tmc = tmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* baud divisor - time constant*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sca_out(port->tmc, msci + TMCR, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) sca_out(port->tmc, msci + TMCT, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Set BRG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sca_out(port->rxs, msci + RXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sca_out(port->txs, msci + TXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (port->settings.loopback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) md2 |= MD2_LOOPBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) md2 &= ~MD2_LOOPBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) sca_out(md2, msci + MD2, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void sca_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) card_t* card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u16 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 md0, md2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) switch(port->encoding) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case ENCODING_NRZ: md2 = MD2_NRZ; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case ENCODING_NRZI: md2 = MD2_NRZI; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) default: md2 = MD2_MANCHESTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (port->settings.loopback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) md2 |= MD2_LOOPBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) switch(port->parity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) default: md0 = MD0_HDLC | MD0_CRC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) sca_out(CMD_RESET, msci + CMD, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sca_out(md0, msci + MD0, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) sca_out(0x00, msci + MD1, card); /* no address field check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) sca_out(md2, msci + MD2, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Skip the rest of underrun frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* We're using the following interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) - RXINTA (DCD changes only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) - DMIB (EOM - single frame transfer complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sca_outl(IE0_RXINTA | IE0_CDCD, msci + IE0, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sca_out(port->tmc, msci + TMCR, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sca_out(port->tmc, msci + TMCT, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sca_out(port->rxs, msci + RXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) sca_out(port->txs, msci + TXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sca_out(CMD_TX_ENABLE, msci + CMD, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sca_out(CMD_RX_ENABLE, msci + CMD, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sca_set_carrier(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) enable_intr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) napi_enable(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void sca_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* reset channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) sca_out(CMD_RESET, get_msci(port) + CMD, port->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) disable_intr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) napi_disable(&port->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int sca_attach(struct net_device *dev, unsigned short encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned short parity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (encoding != ENCODING_NRZ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) encoding != ENCODING_NRZI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) encoding != ENCODING_FM_MARK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) encoding != ENCODING_FM_SPACE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) encoding != ENCODING_MANCHESTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (parity != PARITY_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) parity != PARITY_CRC16_PR0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) parity != PARITY_CRC16_PR1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) parity != PARITY_CRC32_PR1_CCITT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) parity != PARITY_CRC16_PR1_CCITT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_to_port(dev)->encoding = encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_to_port(dev)->parity = parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #ifdef DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void sca_dump_rings(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) card_t *card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u16 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) sca_inl(get_dmac_rx(port) + CDAL, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sca_inl(get_dmac_rx(port) + EDAL, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sca_in(DSR_RX(port->chan), card), port->rxin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) sca_in(DSR_RX(port->chan), card) & DSR_DE ? "" : "in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) for (cnt = 0; cnt < port->card->rx_ring_buffers; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "last=%u %sactive",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) sca_inl(get_dmac_tx(port) + CDAL, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sca_inl(get_dmac_tx(port) + EDAL, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) sca_in(DSR_TX(port->chan), card), port->txin, port->txlast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) sca_in(DSR_TX(port->chan), card) & DSR_DE ? "" : "in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (cnt = 0; cnt < port->card->tx_ring_buffers; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) sca_in(get_msci(port) + MD0, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) sca_in(get_msci(port) + MD1, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) sca_in(get_msci(port) + MD2, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) sca_in(get_msci(port) + ST0, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) sca_in(get_msci(port) + ST1, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) sca_in(get_msci(port) + ST2, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) sca_in(get_msci(port) + ST3, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) sca_in(get_msci(port) + ST4, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) sca_in(get_msci(port) + FST, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) sca_in(get_msci(port) + CST0, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) sca_in(get_msci(port) + CST1, card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sca_inl(ISR0, card), sca_inl(ISR1, card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #endif /* DEBUG_RINGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) card_t *card = port->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pkt_desc __iomem *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 buff, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) spin_lock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) desc = desc_address(port, port->txin + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #ifdef DEBUG_PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) debug_frame(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) desc = desc_address(port, port->txin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) buff = buffer_offset(port, port->txin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) memcpy_toio(card->rambase + buff, skb->data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) writew(len, &desc->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) writeb(ST_TX_EOM, &desc->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) port->txin = (port->txin + 1) % card->tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) sca_outl(desc_offset(port, port->txin, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) get_dmac_tx(port) + EDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) sca_out(DSR_DE, DSR_TX(port->chan), card); /* Enable TX DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) desc = desc_address(port, port->txin + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (readb(&desc->stat)) /* allow 1 packet gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) spin_unlock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Round RAM size to 32 bits, fill from end to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 i = ramsize &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) i -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) writel(i ^ 0x12345678, rambase + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } while (i > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (i = 0; i < ramsize ; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (readl(rambase + i) != (i ^ 0x12345678))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void sca_init(card_t *card, int wait_states)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) sca_out(wait_states, WCRL, card); /* Wait Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) sca_out(wait_states, WCRM, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sca_out(wait_states, WCRH, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) sca_out(0, DMER, card); /* DMA Master disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) sca_out(0x03, PCR, card); /* DMA priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sca_out(0, DSR_TX(0), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) sca_out(0, DSR_RX(1), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sca_out(0, DSR_TX(1), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) sca_out(DMER_DME, DMER, card); /* DMA Master enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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