Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __HD64570_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __HD64570_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)    and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)    Source: HD64570 SCA User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* SCA Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define LPR    0x00		/* Low Power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* Wait controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PABR0  0x02		/* Physical Address Boundary 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PABR1  0x03		/* Physical Address Boundary 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define WCRL   0x04		/* Wait Control L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define WCRM   0x05		/* Wait Control M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define WCRH   0x06		/* Wait Control H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PCR    0x08		/* DMA Priority Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DMER   0x09		/* DMA Master Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ISR0   0x10		/* Interrupt Status 0  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ISR1   0x11		/* Interrupt Status 1  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ISR2   0x12		/* Interrupt Status 2  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IER0   0x14		/* Interrupt Enable 0  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IER1   0x15		/* Interrupt Enable 1  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IER2   0x16		/* Interrupt Enable 2  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ITCR   0x18		/* Interrupt Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IVR    0x1A		/* Interrupt Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IMVR   0x1C		/* Interrupt Modified Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* MSCI channel (port) 0 registers - offset 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)    MSCI channel (port) 1 registers - offset 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MSCI0_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MSCI1_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TRBL   0x00		/* TX/RX buffer L */ 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TRBH   0x01		/* TX/RX buffer H */ 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ST0    0x02		/* Status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ST1    0x03		/* Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ST2    0x04		/* Status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ST3    0x05		/* Status 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define FST    0x06		/* Frame Status  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IE0    0x08		/* Interrupt Enable 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IE1    0x09		/* Interrupt Enable 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IE2    0x0A		/* Interrupt Enable 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define FIE    0x0B		/* Frame Interrupt Enable  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CMD    0x0C		/* Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MD0    0x0E		/* Mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MD1    0x0F		/* Mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MD2    0x10		/* Mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CTL    0x11		/* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SA0    0x12		/* Sync/Address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SA1    0x13		/* Sync/Address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IDL    0x14		/* Idle Pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TMC    0x15		/* Time Constant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define RXS    0x16		/* RX Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TXS    0x17		/* TX Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TRC0   0x18		/* TX Ready Control 0 */ 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TRC1   0x19		/* TX Ready Control 1 */ 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define RRC    0x1A		/* RX Ready Control */ 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CST0   0x1C		/* Current Status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CST1   0x1D		/* Current Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* Timer channel 0 (port 0 RX) registers - offset 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)    Timer channel 1 (port 0 TX) registers - offset 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)    Timer channel 2 (port 1 RX) registers - offset 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)    Timer channel 3 (port 1 TX) registers - offset 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TIMER0RX_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define TIMER0TX_OFFSET 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define TIMER1RX_OFFSET 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TIMER1TX_OFFSET 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TCNTL  0x00		/* Up-counter L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TCNTH  0x01		/* Up-counter H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TCONRL 0x02		/* Constant L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TCONRH 0x03		/* Constant H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TCSR   0x04		/* Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TEPR   0x05		/* Expand Prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* DMA channel 0 (port 0 RX) registers - offset 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)    DMA channel 1 (port 0 TX) registers - offset 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)    DMA channel 2 (port 1 RX) registers - offset 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)    DMA channel 3 (port 1 TX) registers - offset 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DMAC0RX_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DMAC0TX_OFFSET 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DMAC1RX_OFFSET 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DMAC1TX_OFFSET 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BARL   0x00		/* Buffer Address L (chained block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BARH   0x01		/* Buffer Address H (chained block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BARB   0x02		/* Buffer Address B (chained block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DARL   0x00		/* RX Destination Addr L (single block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DARH   0x01		/* RX Destination Addr H (single block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DARB   0x02		/* RX Destination Addr B (single block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SARL   0x04		/* TX Source Address L (single block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SARH   0x05		/* TX Source Address H (single block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SARB   0x06		/* TX Source Address B (single block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CPB    0x06		/* Chain Pointer Base (chained block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CDAL   0x08		/* Current Descriptor Addr L (chained block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CDAH   0x09		/* Current Descriptor Addr H (chained block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EDAL   0x0A		/* Error Descriptor Addr L (chained block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EDAH   0x0B		/* Error Descriptor Addr H (chained block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BFLL   0x0C		/* RX Receive Buffer Length L (chained block)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BFLH   0x0D		/* RX Receive Buffer Length H (chained block)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BCRL   0x0E		/* Byte Count L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BCRH   0x0F		/* Byte Count H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DSR    0x10		/* DMA Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DMR    0x11		/* DMA Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FCT    0x13		/* Frame End Interrupt Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DIR    0x14		/* DMA Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DCR    0x15		/* DMA Command  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Descriptor Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u16 cp;			/* Chain Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u32 bp;			/* Buffer Pointer (24 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u16 len;		/* Data Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u8 stat;		/* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u8 unused;		/* pads to 2-byte boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }__packed pkt_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Packet Descriptor Status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ST_TX_EOM     0x80	/* End of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ST_TX_EOT     0x01	/* End of transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ST_RX_EOM     0x80	/* End of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ST_RX_SHORT   0x40	/* Short frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ST_RX_ABORT   0x20	/* Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ST_RX_RESBIT  0x10	/* Residual bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ST_RX_OVERRUN 0x08	/* Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ST_RX_CRC     0x04	/* CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ST_ERROR_MASK 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DIR_EOTE      0x80      /* Transfer completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DIR_EOME      0x40      /* Frame Transfer Completed (chained-block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DIR_BOFE      0x20      /* Buffer Overflow/Underflow (chained-block)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DIR_COFE      0x10      /* Counter Overflow (chained-block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DSR_EOT       0x80      /* Transfer completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DSR_EOM       0x40      /* Frame Transfer Completed (chained-block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DSR_BOF       0x20      /* Buffer Overflow/Underflow (chained-block)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DSR_COF       0x10      /* Counter Overflow (chained-block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DSR_DE        0x02	/* DMA Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DSR_DWE       0x01      /* DMA Write Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* DMA Master Enable Register (DMER) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DMER_DME      0x80	/* DMA Master Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CMD_RESET     0x21	/* Reset Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CMD_TX_ENABLE 0x02	/* Start transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CMD_RX_ENABLE 0x12	/* Start receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MD0_HDLC      0x80	/* Bit-sync HDLC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MD0_CRC_ENA   0x04	/* Enable CRC code calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MD0_CRC_CCITT 0x02	/* CCITT CRC instead of CRC-16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MD0_CRC_PR1   0x01	/* Initial all-ones instead of all-zeros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MD0_CRC_NONE  0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MD0_CRC_16_0  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MD0_CRC_16    0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MD0_CRC_ITU_0 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MD0_CRC_ITU   0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MD2_NRZ	      0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MD2_NRZI      0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MD2_MANCHESTER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MD2_FM_MARK   0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MD2_FM_SPACE  0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MD2_LOOPBACK  0x03      /* Local data Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CTL_NORTS     0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CTL_IDLE      0x10	/* Transmit an idle pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CTL_UDRNC     0x20	/* Idle after CRC or FCS+flag transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ST0_TXRDY     0x02	/* TX ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ST0_RXRDY     0x01	/* RX ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ST1_UDRN      0x80	/* MSCI TX underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ST1_CDCD      0x04	/* DCD level changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ST3_CTS       0x08	/* modem input - /CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ST3_DCD       0x04	/* modem input - /DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IE0_TXINT     0x80	/* TX INT MSCI interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IE0_RXINTA    0x40	/* RX INT A MSCI interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IE1_UDRN      0x80	/* TX underrun MSCI interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IE1_CDCD      0x04	/* DCD level changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DCR_ABORT     0x01	/* Software abort command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DCR_CLEAR_EOF 0x02	/* Clear EOF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* TX and RX Clock Source - RXS and TXS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_BRG_MASK  0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_LINE_RX   0x00	/* TX/RX clock line input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_LINE_TX   0x00	/* TX/RX line input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_BRG_RX    0x40	/* internal baud rate generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_BRG_TX    0x40	/* internal baud rate generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_RXCLK_TX  0x60	/* TX clock from RX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif