^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hitachi SCA HD64570 driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Source of information: Hitachi HD64570 SCA User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * We use the following SCA memory map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Packet buffer descriptor rings - starting from winbase or win0base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Packet data buffers - starting from winbase + buff_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/hdlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "hd64570.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline struct net_device *port_to_dev(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline int sca_intr_status(card_t *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 isr0 = sca_in(ISR0, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 isr1 = sca_in(ISR1, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!(result & SCA_INTR_DMAC_TX(0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (sca_in(DSR_TX(0), card) & DSR_EOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) result |= SCA_INTR_DMAC_TX(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!(result & SCA_INTR_DMAC_TX(1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (sca_in(DSR_TX(1), card) & DSR_EOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) result |= SCA_INTR_DMAC_TX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline port_t* dev_to_port(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return dev_to_hdlc(dev)->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline u16 next_desc(port_t *port, u16 desc, int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) : port_to_card(port)->rx_ring_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return log_node(port) * (rx_buffs + tx_buffs) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) transmit * rx_buffs + desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Descriptor offset always fits in 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef PAGE0_ALWAYS_MAPPED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return (pkt_desc __iomem *)(win0base(port_to_card(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) + desc_offset(port, desc, transmit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return (pkt_desc __iomem *)(winbase(port_to_card(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) + desc_offset(port, desc, transmit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return port_to_card(port)->buff_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline void sca_set_carrier(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #ifdef DEBUG_LINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) printk(KERN_DEBUG "%s: sca_set_carrier on\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) port_to_dev(port)->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) netif_carrier_on(port_to_dev(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef DEBUG_LINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) printk(KERN_DEBUG "%s: sca_set_carrier off\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) port_to_dev(port)->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) netif_carrier_off(port_to_dev(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void sca_init_port(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) card_t *card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int transmit, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) port->rxin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) port->txin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) port->txlast = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #ifndef PAGE0_ALWAYS_MAPPED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) openwin(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (transmit = 0; transmit < 2; transmit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u16 buffs = transmit ? card->tx_ring_buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) : card->rx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < buffs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pkt_desc __iomem *desc = desc_address(port, i, transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u16 chain_off = desc_offset(port, i + 1, transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 buff_off = buffer_offset(port, i, transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writew(chain_off, &desc->cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writel(buff_off, &desc->bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writew(0, &desc->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writeb(0, &desc->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* DMA disable - to halt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sca_out(0, transmit ? DSR_TX(phy_node(port)) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DSR_RX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* software ABORT - to initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DCR_RX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* current desc addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sca_out(0, dmac + CPB, card); /* pointer base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!transmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sca_outw(desc_offset(port, buffs - 1, transmit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dmac + EDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* clear frame end interrupt counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DCR_RX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!transmit) { /* Receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* set buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Chain mode, Multi-frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sca_out(0x14, DMR_RX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* DMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else { /* Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Chain mode, Multi-frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) sca_out(0x14, DMR_TX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* enable underflow interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sca_set_carrier(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #ifdef NEED_SCA_MSCI_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* MSCI interrupt service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline void sca_msci_intr(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u16 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) card_t* card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Reset MSCI TX underrun and CDCD status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (stat & ST1_UDRN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* TX Underrun error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) port_to_dev(port)->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) port_to_dev(port)->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (stat & ST1_CDCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sca_set_carrier(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u16 rxin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct net_device *dev = port_to_dev(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) len = readw(&desc->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) skb = dev_alloc_skb(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) buff = buffer_offset(port, rxin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) page = buff / winsize(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) buff = buff % winsize(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) maxlen = winsize(card) - buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) openwin(card, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (len > maxlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) openwin(card, page + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) memcpy_fromio(skb->data, winbase(card) + buff, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifndef PAGE0_ALWAYS_MAPPED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) openwin(card, 0); /* select pkt_desc table page back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #ifdef DEBUG_PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) debug_frame(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev->stats.rx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) skb->protocol = hdlc_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Receive DMA interrupt service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static inline void sca_rx_intr(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct net_device *dev = port_to_dev(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u16 dmac = get_dmac_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) card_t *card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Reset DSR status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DSR_RX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (stat & DSR_BOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Dropped one or more frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 desc_off = desc_offset(port, port->rxin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pkt_desc __iomem *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 cda = sca_inw(dmac + CDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break; /* No frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) desc = desc_address(port, port->rxin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) stat = readb(&desc->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!(stat & ST_RX_EOM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) port->rxpart = 1; /* partial frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else if ((stat & ST_ERROR_MASK) || port->rxpart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (stat & ST_RX_OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ST_RX_RESBIT)) || port->rxpart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else if (stat & ST_RX_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (stat & ST_RX_EOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) port->rxpart = 0; /* received last fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) sca_rx(card, port, desc, port->rxin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Set new error descriptor address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) sca_outw(desc_off, dmac + EDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) port->rxin = next_desc(port, port->rxin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* make sure RX DMA is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Transmit DMA interrupt service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline void sca_tx_intr(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct net_device *dev = port_to_dev(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 dmac = get_dmac_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) card_t* card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Reset DSR status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DSR_TX(phy_node(port)), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pkt_desc __iomem *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 desc_off = desc_offset(port, port->txlast, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 cda = sca_inw(dmac + CDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break; /* Transmitter is/will_be sending this frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) desc = desc_address(port, port->txlast, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev->stats.tx_bytes += readw(&desc->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writeb(0, &desc->stat); /* Free descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) port->txlast = next_desc(port, port->txlast, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static irqreturn_t sca_intr(int irq, void* dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) card_t *card = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u8 page = sca_get_page(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) while((stat = sca_intr_status(card)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) port_t *port = get_port(card, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (stat & SCA_INTR_MSCI(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sca_msci_intr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (stat & SCA_INTR_DMAC_RX(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sca_rx_intr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (stat & SCA_INTR_DMAC_TX(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) sca_tx_intr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) openwin(card, page); /* Restore original page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void sca_set_port(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) card_t* card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u16 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u8 md2 = sca_in(msci + MD2, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int tmc, br = 10, brv = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (port->settings.clock_rate > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Try lower br for better accuracy*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) br--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) brv >>= 1; /* brv = 2^9 = 512 max in specs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tmc = CLOCK_BASE / brv / port->settings.clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }while (br > 1 && tmc <= 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (tmc < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tmc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) brv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) } else if (tmc > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tmc = 256; /* tmc=0 means 256 - low baud rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) port->settings.clock_rate = CLOCK_BASE / brv / tmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) br = 9; /* Minimum clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tmc = 256; /* 8bit = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) port->settings.clock_rate = CLOCK_BASE / (256 * 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) port->txs = (port->txs & ~CLK_BRG_MASK) | br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) port->tmc = tmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* baud divisor - time constant*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) sca_out(port->tmc, msci + TMC, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Set BRG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) sca_out(port->rxs, msci + RXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) sca_out(port->txs, msci + TXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (port->settings.loopback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) md2 |= MD2_LOOPBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) md2 &= ~MD2_LOOPBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) sca_out(md2, msci + MD2, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void sca_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) card_t* card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u16 msci = get_msci(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 md0, md2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) switch(port->encoding) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case ENCODING_NRZ: md2 = MD2_NRZ; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case ENCODING_NRZI: md2 = MD2_NRZI; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) default: md2 = MD2_MANCHESTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (port->settings.loopback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) md2 |= MD2_LOOPBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) switch(port->parity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) default: md0 = MD0_HDLC | MD0_CRC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sca_out(CMD_RESET, msci + CMD, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sca_out(md0, msci + MD0, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) sca_out(0x00, msci + MD1, card); /* no address field check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) sca_out(md2, msci + MD2, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) sca_out(CTL_IDLE, msci + CTL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Allow at least 8 bytes before requesting RX DMA operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* TX with higher priority and possibly with shorter transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* We're using the following interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) - TXINT (DMAC completed all transmisions, underrun or DCD change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) - all DMA interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) sca_set_carrier(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* MSCI TX INT and RX INT A IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) IER0, card); /* TXINT and RXINT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* enable DMA IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) IER1, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) sca_out(port->tmc, msci + TMC, card); /* Restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sca_out(port->rxs, msci + RXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sca_out(port->txs, msci + TXS, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sca_out(CMD_TX_ENABLE, msci + CMD, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sca_out(CMD_RX_ENABLE, msci + CMD, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void sca_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) card_t* card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* reset channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* disable MSCI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) IER0, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* disable DMA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) IER1, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int sca_attach(struct net_device *dev, unsigned short encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned short parity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (encoding != ENCODING_NRZ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) encoding != ENCODING_NRZI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) encoding != ENCODING_FM_MARK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) encoding != ENCODING_FM_SPACE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) encoding != ENCODING_MANCHESTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (parity != PARITY_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) parity != PARITY_CRC16_PR0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) parity != PARITY_CRC16_PR1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) parity != PARITY_CRC16_PR0_CCITT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) parity != PARITY_CRC16_PR1_CCITT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_to_port(dev)->encoding = encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_to_port(dev)->parity = parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #ifdef DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static void sca_dump_rings(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) card_t *card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u16 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #ifndef PAGE0_ALWAYS_MAPPED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 page = sca_get_page(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) openwin(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) sca_inw(get_dmac_rx(port) + CDAL, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sca_inw(get_dmac_rx(port) + EDAL, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) sca_in(DSR_RX(phy_node(port)), card), port->rxin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) "last=%u %sactive",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) sca_inw(get_dmac_tx(port) + CDAL, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) sca_inw(get_dmac_tx(port) + EDAL, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, ST: %02x %02x %02x %02x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) " FST: %02x CST: %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sca_in(get_msci(port) + MD0, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sca_in(get_msci(port) + MD1, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) sca_in(get_msci(port) + MD2, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) sca_in(get_msci(port) + ST0, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) sca_in(get_msci(port) + ST1, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sca_in(get_msci(port) + ST2, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) sca_in(get_msci(port) + ST3, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) sca_in(get_msci(port) + FST, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) sca_in(get_msci(port) + CST0, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) sca_in(get_msci(port) + CST1, card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) sca_in(ISR1, card), sca_in(ISR2, card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #ifndef PAGE0_ALWAYS_MAPPED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) openwin(card, page); /* Restore original page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif /* DEBUG_RINGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) card_t *card = port_to_card(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pkt_desc __iomem *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 buff, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u8 page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) spin_lock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) desc = desc_address(port, port->txin + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #ifdef DEBUG_PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) debug_frame(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) desc = desc_address(port, port->txin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) buff = buffer_offset(port, port->txin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) page = buff / winsize(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) buff = buff % winsize(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) maxlen = winsize(card) - buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) openwin(card, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (len > maxlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) memcpy_toio(winbase(card) + buff, skb->data, maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) openwin(card, page + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) memcpy_toio(winbase(card) + buff, skb->data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #ifndef PAGE0_ALWAYS_MAPPED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) openwin(card, 0); /* select pkt_desc table page back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) writew(len, &desc->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) writeb(ST_TX_EOM, &desc->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) port->txin = next_desc(port, port->txin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) sca_outw(desc_offset(port, port->txin, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) get_dmac_tx(port) + EDAL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) desc = desc_address(port, port->txin + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (readb(&desc->stat)) /* allow 1 packet gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) spin_unlock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #ifdef NEED_DETECT_RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Round RAM size to 32 bits, fill from end to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 i = ramsize &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 size = winsize(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) openwin(card, (i - 4) / size); /* select last window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) i -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if ((i + 4) % size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) openwin(card, i / size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) writel(i ^ 0x12345678, rambase + i % size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } while (i > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) for (i = 0; i < ramsize ; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (i % size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) openwin(card, i / size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (readl(rambase + i % size) != (i ^ 0x12345678))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #endif /* NEED_DETECT_RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static void sca_init(card_t *card, int wait_states)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) sca_out(wait_states, WCRL, card); /* Wait Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) sca_out(wait_states, WCRM, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) sca_out(wait_states, WCRH, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) sca_out(0, DMER, card); /* DMA Master disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) sca_out(0x03, PCR, card); /* DMA priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) sca_out(0, DSR_TX(0), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) sca_out(0, DSR_RX(1), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) sca_out(0, DSR_TX(1), card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) sca_out(DMER_DME, DMER, card); /* DMA Master enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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