^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* $Id: cosa.h,v 1.6 1999/01/06 14:02:44 kas Exp $ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995-1997 Jan "Yenya" Kasprzak <kas@fi.muni.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef COSA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define COSA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* status register - output bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SR_RX_DMA_ENA 0x04 /* receiver DMA enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SR_TX_DMA_ENA 0x08 /* transmitter DMA enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SR_RST 0x10 /* SRP reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SR_USR_INT_ENA 0x20 /* user interrupt enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SR_TX_INT_ENA 0x40 /* transmitter interrupt enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SR_RX_INT_ENA 0x80 /* receiver interrupt enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* status register - input bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SR_USR_RQ 0x20 /* user interrupt request pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SR_TX_RDY 0x40 /* transmitter empty (ready) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SR_RX_RDY 0x80 /* receiver data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SR_UP_REQUEST 0x02 /* request from SRP to transfer data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) up to PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SR_DOWN_REQUEST 0x01 /* SRP is able to transfer data down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) from PC to SRP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SR_END_OF_TRANSFER 0x03 /* SRP signalize end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) transfer (up or down) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SR_CMD_FROM_SRP_MASK 0x03 /* mask to get SRP command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* bits in driver status byte definitions : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SR_RDY_RCV 0x01 /* ready to receive packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SR_RDY_SND 0x02 /* ready to send packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SR_CMD_PND 0x04 /* command pending */ /* not currently used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* ???? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SR_PKT_UP 0x01 /* transfer of packet up in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SR_PKT_DOWN 0x02 /* transfer of packet down in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SR_LOAD_ADDR 0x4400 /* SRP microcode load address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SR_START_ADDR 0x4400 /* SRP microcode start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define COSA_LOAD_ADDR 0x400 /* SRP microcode load address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define COSA_MAX_FIRMWARE_SIZE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* ioctls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct cosa_download {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int addr, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) char __user *code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Reset the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define COSAIORSET _IO('C',0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Start microcode at given address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define COSAIOSTRT _IOW('C',0xf1, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Read the block from the device memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define COSAIORMEM _IOWR('C',0xf2, struct cosa_download *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* actually the struct cosa_download itself; this is to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * the ioctl number same as in 2.4 in order to keep the user-space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * utils compatible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Write the block to the device memory (i.e. download the microcode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define COSAIODOWNLD _IOW('C',0xf2, struct cosa_download *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* actually the struct cosa_download itself; this is to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * the ioctl number same as in 2.4 in order to keep the user-space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * utils compatible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Read the device type (one of "srp", "cosa", and "cosa8" for now) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define COSAIORTYPE _IOR('C',0xf3, char *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Read the device identification string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define COSAIORIDSTR _IOR('C',0xf4, char *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Maximum length of the identification string. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define COSA_MAX_ID_STRING 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Increment/decrement the module usage count :-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* #define COSAIOMINC _IO('C',0xf5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* #define COSAIOMDEC _IO('C',0xf6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Get the total number of cards installed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define COSAIONRCARDS _IO('C',0xf7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Get the number of channels on this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define COSAIONRCHANS _IO('C',0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Set the driver for the bus-master operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define COSAIOBMSET _IOW('C', 0xf9, unsigned short)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define COSA_BM_OFF 0 /* Bus-mastering off - use ISA DMA (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define COSA_BM_ON 1 /* Bus-mastering on - faster but untested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Gets the busmaster status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define COSAIOBMGET _IO('C', 0xfa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif /* !COSA_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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