^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Moxa C101 synchronous serial card driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Sources of information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Hitachi HD64570 SCA User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Moxa C101 User's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/hdlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "hd64570.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const char* version = "Moxa C101 driver version: 1.15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char* devname = "C101";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #undef DEBUG_PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define C101_PAGE 0x1D00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define C101_DTR 0x1E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define C101_SCA 0x1F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define C101_WINDOW_SIZE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define C101_MAPPED_RAM_SIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RAM_SIZE (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TX_RING_BUFFERS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLOCK_BASE 9830400 /* 9.8304 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PAGE0_ALWAYS_MAPPED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static char *hw; /* pointer to hw=xxx command line string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) typedef struct card_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) spinlock_t lock; /* TX lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 __iomem *win0base; /* ISA window base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 phy_winbase; /* ISA physical base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) sync_serial_settings settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int rxpart; /* partial frame received, next frame invalid*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned short encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned short parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 rx_ring_buffers; /* number of buffers in a ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 tx_ring_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 buff_offset; /* offset of first buffer of first channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 rxin; /* rx ring buffer 'in' pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 txin; /* tx ring buffer 'in' and 'last' pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u16 txlast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 rxs, txs, tmc; /* SCA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 irq; /* IRQ (3-15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct card_s *next_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }card_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) typedef card_t port_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static card_t *first_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static card_t **new_card = &first_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define sca_in(reg, card) readb((card)->win0base + C101_SCA + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define sca_out(value, reg, card) writeb(value, (card)->win0base + C101_SCA + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define sca_inw(reg, card) readw((card)->win0base + C101_SCA + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define sca_outw(value, reg, card) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg + 1));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define port_to_card(port) (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define log_node(port) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define phy_node(port) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define winsize(card) (C101_WINDOW_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define win0base(card) ((card)->win0base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define winbase(card) ((card)->win0base + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define get_port(card, port) (card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void sca_msci_intr(port_t *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline u8 sca_get_page(card_t *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return card->page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void openwin(card_t *card, u8 page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) card->page = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writeb(page, card->win0base + C101_PAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #include "hd64570.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline void set_carrier(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) netif_carrier_on(port_to_dev(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) netif_carrier_off(port_to_dev(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void sca_msci_intr(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Reset MSCI TX underrun and CDCD (ignored) status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (stat & ST1_UDRN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* TX Underrun error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) port_to_dev(port)->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) port_to_dev(port)->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (stat & ST1_CDCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) set_carrier(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void c101_set_iface(port_t *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 rxs = port->rxs & CLK_BRG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 txs = port->txs & CLK_BRG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) switch(port->settings.clock_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case CLOCK_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) rxs |= CLK_BRG_RX; /* TX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) txs |= CLK_RXCLK_TX; /* BRG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case CLOCK_TXINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rxs |= CLK_LINE_RX; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) txs |= CLK_BRG_TX; /* BRG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case CLOCK_TXFROMRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rxs |= CLK_LINE_RX; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) txs |= CLK_RXCLK_TX; /* RX clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) default: /* EXTernal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rxs |= CLK_LINE_RX; /* RXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) txs |= CLK_LINE_TX; /* TXC input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) port->rxs = rxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) port->txs = txs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sca_out(rxs, MSCI1_OFFSET + RXS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sca_out(txs, MSCI1_OFFSET + TXS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) sca_set_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int c101_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) result = hdlc_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writeb(1, port->win0base + C101_DTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sca_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) set_carrier(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* enable MSCI1 CDCD interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) c101_set_iface(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int c101_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) sca_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writeb(0, port->win0base + C101_DTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) hdlc_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) const size_t size = sizeof(sync_serial_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sync_serial_settings new_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) port_t *port = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef DEBUG_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (cmd == SIOCDEVPRIVATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sca_dump_rings(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sca_in(MSCI1_OFFSET + ST0, port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sca_in(MSCI1_OFFSET + ST1, port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sca_in(MSCI1_OFFSET + ST2, port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sca_in(MSCI1_OFFSET + ST3, port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (cmd != SIOCWANDEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) switch(ifr->ifr_settings.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case IF_GET_IFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ifr->ifr_settings.size < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ifr->ifr_settings.size = size; /* data size wanted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (copy_to_user(line, &port->settings, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case IF_IFACE_SYNC_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if(!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (copy_from_user(&new_line, line, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (new_line.clock_type != CLOCK_EXT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) new_line.clock_type != CLOCK_TXFROMRX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) new_line.clock_type != CLOCK_INT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) new_line.clock_type != CLOCK_TXINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL; /* No such clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (new_line.loopback != 0 && new_line.loopback != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) memcpy(&port->settings, &new_line, size); /* Update settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) c101_set_iface(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void c101_destroy_card(card_t *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) readb(card->win0base + C101_PAGE); /* Resets SCA? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (card->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) free_irq(card->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (card->win0base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) iounmap(card->win0base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) free_netdev(card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct net_device_ops c101_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .ndo_open = c101_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .ndo_stop = c101_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .ndo_start_xmit = hdlc_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .ndo_do_ioctl = c101_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int __init c101_run(unsigned long irq, unsigned long winbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) hdlc_device *hdlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) card_t *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pr_err("invalid IRQ value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pr_err("invalid RAM value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) card = kzalloc(sizeof(card_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (card == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) card->dev = alloc_hdlcdev(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!card->dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pr_err("unable to allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (request_irq(irq, sca_intr, 0, devname, card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pr_err("could not allocate IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) c101_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) card->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pr_err("could not request RAM window\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) c101_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) card->phy_winbase = winbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!card->win0base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pr_err("could not map I/O address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) c101_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) card->tx_ring_buffers = TX_RING_BUFFERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) card->rx_ring_buffers = RX_RING_BUFFERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) readb(card->win0base + C101_PAGE); /* Resets SCA? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) writeb(0, card->win0base + C101_PAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sca_init(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev = port_to_dev(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) hdlc = dev_to_hdlc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spin_lock_init(&card->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev->mem_start = winbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev->tx_queue_len = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev->netdev_ops = &c101_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) hdlc->attach = sca_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) hdlc->xmit = sca_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) card->settings.clock_type = CLOCK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) result = register_hdlc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pr_warn("unable to register hdlc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) c101_destroy_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) sca_init_port(card); /* Set up C101 memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) set_carrier(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) netdev_info(dev, "Moxa C101 on IRQ%u, using %u TX + %u RX packets rings\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) card->irq, card->tx_ring_buffers, card->rx_ring_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *new_card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) new_card = &card->next_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int __init c101_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (hw == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pr_info("no card initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EINVAL; /* no parameters specified, abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pr_info("%s\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long irq, ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) irq = simple_strtoul(hw, &hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (*hw++ != ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ram = simple_strtoul(hw, &hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (*hw == ':' || *hw == '\x0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) c101_run(irq, ram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (*hw == '\x0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return first_card ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }while(*hw++ == ':');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pr_err("invalid hardware parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return first_card ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void __exit c101_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) card_t *card = first_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) while (card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) card_t *ptr = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) card = card->next_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unregister_hdlc_device(port_to_dev(ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) c101_destroy_card(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) module_init(c101_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) module_exit(c101_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_DESCRIPTION("Moxa C101 serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) module_param(hw, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_PARM_DESC(hw, "irq,ram:irq,...");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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