^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Linux driver for VMware's vmxnet3 ethernet NIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Free Software Foundation; version 2 of the License and no later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * NON INFRINGEMENT. See the GNU General Public License for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * The full GNU General Public License is included in this distribution in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * the file called "COPYING".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Maintained by: pv-drivers@vmware.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <net/ip6_checksum.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "vmxnet3_int.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) char vmxnet3_driver_name[] = "vmxnet3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * PCI Device ID Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Last entry must be all 0s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct pci_device_id vmxnet3_pciid_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int enable_mq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Enable/Disable the given intr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Enable/Disable all intrs used by the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for (i = 0; i < adapter->intr.num_intrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) vmxnet3_enable_intr(adapter, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) adapter->shared->devRead.intrConf.intrCtrl &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) adapter->shared->devRead.intrConf.intrCtrl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) for (i = 0; i < adapter->intr.num_intrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) vmxnet3_disable_intr(adapter, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return tq->stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tq->stopped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tq->stopped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) tq->stopped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tq->num_stop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Check the link state. This may start or stop the tx queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) adapter->link_speed = ret >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret & 1) { /* Link is up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) adapter->link_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) netif_carrier_on(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (affectTxQueue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) vmxnet3_tq_start(&adapter->tx_queue[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) netdev_info(adapter->netdev, "NIC Link is Down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) netif_carrier_off(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (affectTxQueue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) vmxnet3_process_events(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 events = le32_to_cpu(adapter->shared->ecr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) vmxnet3_ack_events(adapter, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Check if link state has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (events & VMXNET3_ECR_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) vmxnet3_check_link(adapter, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Check if there is an error on xmit/recv queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) VMXNET3_CMD_GET_QUEUE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (adapter->tqd_start[i].status.stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(&adapter->netdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "%s: tq[%d] error 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) adapter->netdev->name, i, le32_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) adapter->tqd_start[i].status.error));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (adapter->rqd_start[i].status.stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(&adapter->netdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "%s: rq[%d] error 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) adapter->netdev->name, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) adapter->rqd_start[i].status.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) schedule_work(&adapter->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * The device expects the bitfields in shared structures to be written in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * little endian. When CPU is big endian, the following routines are used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * correctly read and write into ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * The general technique used here is : double word bitfields are defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * opposite order for big endian architecture. Then before reading them in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * driver the complete double word is translated using le32_to_cpu. Similarly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * After the driver writes into bitfields, cpu_to_le32 is used to translate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * double words into required format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * In order to avoid touching bits in shared structure more than once, temporary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * descriptors are used. These are passed as srcDesc to following functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct Vmxnet3_RxDesc *dstDesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 *src = (u32 *)srcDesc + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 *dst = (u32 *)dstDesc + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dstDesc->addr = le64_to_cpu(srcDesc->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *dst = le32_to_cpu(*src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct Vmxnet3_TxDesc *dstDesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 *src = (u32 *)(srcDesc + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 *dst = (u32 *)(dstDesc + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Working backwards so that the gen bit is set at the end. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for (i = 2; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dst--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *dst = cpu_to_le32(*src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct Vmxnet3_RxCompDesc *dstDesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 *src = (u32 *)srcDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 *dst = (u32 *)dstDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *dst = le32_to_cpu(*src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Used to read bitfield values from double words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 temp = le32_to_cpu(*bitfield);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 mask = ((1 << size) - 1) << pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) temp &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) temp >>= pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) VMXNET3_TCD_GEN_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) (dstrcd) = (tmp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) vmxnet3_RxCompToCPU((rcd), (tmp)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) (dstrxd) = (tmp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) vmxnet3_RxDescToCPU((rxd), (tmp)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (tbi->map_type == VMXNET3_MAP_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PCI_DMA_TODEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else if (tbi->map_type == VMXNET3_MAP_PAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PCI_DMA_TODEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* no out of order completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) skb = tq->buf_info[eop_idx].skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) BUG_ON(skb == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tq->buf_info[eop_idx].skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) while (tq->tx_ring.next2comp != eop_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* update next2comp w/o tx_lock. Since we are marking more,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * instead of less, tx ring entries avail, the worst case is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * that the tx routine incorrectly re-queues a pkt due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * insufficient tx ring entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) entries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int completed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) union Vmxnet3_GenericDesc *gdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Prevent any &gdesc->tcd field from being (speculatively)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * read before (&gdesc->tcd)->gen is read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dma_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) &gdesc->tcd), tq, adapter->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (completed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) spin_lock(&tq->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) netif_carrier_ok(adapter->netdev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) vmxnet3_tq_wake(tq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spin_unlock(&tq->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct vmxnet3_tx_buf_info *tbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tbi = tq->buf_info + tq->tx_ring.next2comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (tbi->skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_kfree_skb_any(tbi->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) tbi->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* sanity check, verify all buffers are indeed unmapped and freed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (i = 0; i < tq->tx_ring.size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) BUG_ON(tq->buf_info[i].skb != NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) tq->tx_ring.gen = VMXNET3_INIT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tq->comp_ring.gen = VMXNET3_INIT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) tq->comp_ring.next2proc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (tq->tx_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) sizeof(struct Vmxnet3_TxDesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) tq->tx_ring.base, tq->tx_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tq->tx_ring.base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (tq->data_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tq->data_ring.size * tq->txdata_desc_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tq->data_ring.base, tq->data_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) tq->data_ring.base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (tq->comp_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) sizeof(struct Vmxnet3_TxCompDesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) tq->comp_ring.base, tq->comp_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tq->comp_ring.base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (tq->buf_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) tq->tx_ring.size * sizeof(tq->buf_info[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) tq->buf_info, tq->buf_info_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) tq->buf_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Destroy all tx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* reset the tx ring contents to 0 and reset the tx ring states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) memset(tq->tx_ring.base, 0, tq->tx_ring.size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sizeof(struct Vmxnet3_TxDesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tq->tx_ring.gen = VMXNET3_INIT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) memset(tq->data_ring.base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) tq->data_ring.size * tq->txdata_desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* reset the tx comp ring contents to 0 and reset comp ring states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) memset(tq->comp_ring.base, 0, tq->comp_ring.size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sizeof(struct Vmxnet3_TxCompDesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) tq->comp_ring.next2proc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tq->comp_ring.gen = VMXNET3_INIT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* reset the bookkeeping data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) for (i = 0; i < tq->tx_ring.size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* stats are not reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) size_t sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) tq->comp_ring.base || tq->buf_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &tq->tx_ring.basePA, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!tq->tx_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) netdev_err(adapter->netdev, "failed to allocate tx ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tq->data_ring.size * tq->txdata_desc_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &tq->data_ring.basePA, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!tq->data_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) &tq->comp_ring.basePA, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!tq->comp_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sz = tq->tx_ring.size * sizeof(tq->buf_info[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tq->buf_info = dma_alloc_coherent(&adapter->pdev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &tq->buf_info_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!tq->buf_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) vmxnet3_tq_destroy(tq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * starting from ring->next2fill, allocate rx buffers for the given ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * are allocated or allocation fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int num_to_alloc, struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int num_allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) while (num_allocated <= num_to_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct vmxnet3_rx_buf_info *rbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) union Vmxnet3_GenericDesc *gd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rbi = rbi_base + ring->next2fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) gd = ring->base + ring->next2fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (rbi->skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) rbi->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (unlikely(rbi->skb == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) rq->stats.rx_buf_alloc_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) rbi->dma_addr = dma_map_single(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) &adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) rbi->skb->data, rbi->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (dma_mapping_error(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) rbi->dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_kfree_skb_any(rbi->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) rq->stats.rx_buf_alloc_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* rx buffer skipped by the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) rbi->len != PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (rbi->page == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) rbi->page = alloc_page(GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (unlikely(rbi->page == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) rq->stats.rx_buf_alloc_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rbi->dma_addr = dma_map_page(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) &adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) rbi->page, 0, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (dma_mapping_error(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) rbi->dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) put_page(rbi->page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) rq->stats.rx_buf_alloc_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* rx buffers skipped by the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) | val | rbi->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Fill the last buffer but dont mark it ready, or else the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * device will think that the queue is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (num_allocated == num_to_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) num_allocated++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) vmxnet3_cmd_ring_adv_next2fill(ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) netdev_dbg(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) num_allocated, ring->next2fill, ring->next2comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* so that the device can distinguish a full ring and an empty ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return num_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct vmxnet3_rx_buf_info *rbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) __skb_frag_set_page(frag, rbi->page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) skb_frag_off_set(frag, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) skb_frag_size_set(frag, rcd->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) skb->data_len += rcd->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) skb->truesize += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) skb_shinfo(skb)->nr_frags++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 dw2, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned long buf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) union Vmxnet3_GenericDesc *gdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct vmxnet3_tx_buf_info *tbi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) BUG_ON(ctx->copy_size > skb_headlen(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* use the previous gen bit for the SOP desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) gdesc = ctx->sop_txd; /* both loops below can be skipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* no need to map the buffer if headers are copied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ctx->copy_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tq->tx_ring.next2fill *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) tq->txdata_desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ctx->sop_txd->dword[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) tbi = tq->buf_info + tq->tx_ring.next2fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) tbi->map_type = VMXNET3_MAP_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) netdev_dbg(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "txd[%u]: 0x%Lx 0x%x 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) tq->tx_ring.next2fill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) le64_to_cpu(ctx->sop_txd->txd.addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* use the right gen for non-SOP desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* linear part can use multiple tx desc if it's big */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) len = skb_headlen(skb) - ctx->copy_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) buf_offset = ctx->copy_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (len < VMXNET3_MAX_TX_BUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) buf_size = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dw2 |= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) buf_size = VMXNET3_MAX_TX_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* spec says that for TxDesc.len, 0 == 2^14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) tbi = tq->buf_info + tq->tx_ring.next2fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) tbi->map_type = VMXNET3_MAP_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) skb->data + buf_offset, buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PCI_DMA_TODEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) tbi->len = buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) gdesc->dword[2] = cpu_to_le32(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) gdesc->dword[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) netdev_dbg(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "txd[%u]: 0x%Lx 0x%x 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) len -= buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) buf_offset += buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) buf_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) len = skb_frag_size(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) tbi = tq->buf_info + tq->tx_ring.next2fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (len < VMXNET3_MAX_TX_BUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) buf_size = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dw2 |= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) buf_size = VMXNET3_MAX_TX_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* spec says that for TxDesc.len, 0 == 2^14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) tbi->map_type = VMXNET3_MAP_PAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) buf_offset, buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) tbi->len = buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) gdesc->dword[2] = cpu_to_le32(dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) gdesc->dword[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) netdev_dbg(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "txd[%u]: 0x%llx %u %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) len -= buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) buf_offset += buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ctx->eop_txd = gdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* set the last buf_info for the pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) tbi->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Init all tx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * parse relevant protocol headers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * For a tso pkt, relevant headers are L2/3/4 including options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * For a pkt requesting csum offloading, they are L2/3 and may include L4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * if it's a TCP/UDP pkt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * -1: error happens during parsing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * 0: protocol headers parsed, but too big to be copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * 1: protocol headers parsed and copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * Other effects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * 1. related *ctx fields are updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * 2. ctx->copy_size is # of bytes copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * 3. the portion to be copied is guaranteed to be in the linear part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct vmxnet3_tx_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 protocol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (ctx->mss) { /* TSO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ctx->l4_offset = skb_inner_transport_offset(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ctx->l4_hdr_size = inner_tcp_hdrlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ctx->l4_offset = skb_transport_offset(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ctx->l4_hdr_size = tcp_hdrlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* For encap packets, skb_checksum_start_offset refers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * to inner L4 offset. Thus, below works for encap as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * well as non-encap case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ctx->l4_offset = skb_checksum_start_offset(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (VMXNET3_VERSION_GE_4(adapter) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) skb->encapsulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct iphdr *iph = inner_ip_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (iph->version == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) protocol = iph->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) const struct ipv6hdr *ipv6h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ipv6h = inner_ipv6_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) protocol = ipv6h->nexthdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (ctx->ipv4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) const struct iphdr *iph = ip_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) protocol = iph->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else if (ctx->ipv6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) const struct ipv6hdr *ipv6h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ipv6h = ipv6_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) protocol = ipv6h->nexthdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) switch (protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case IPPROTO_TCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) tcp_hdrlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case IPPROTO_UDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ctx->l4_hdr_size = sizeof(struct udphdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ctx->l4_hdr_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ctx->copy_size = min(ctx->l4_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ctx->l4_hdr_size, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ctx->l4_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ctx->l4_hdr_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* copy as much as allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ctx->copy_size = min_t(unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) tq->txdata_desc_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) skb_headlen(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (skb->len <= VMXNET3_HDR_COPY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ctx->copy_size = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* make sure headers are accessible directly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) tq->stats.oversized_hdr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ctx->copy_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * copy relevant protocol headers to the transmit ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * For a tso pkt, relevant headers are L2/3/4 including options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * For a pkt requesting csum offloading, they are L2/3 and may include L4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * if it's a TCP/UDP pkt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * Note that this requires that vmxnet3_parse_hdr be called first to set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * appropriate bits in ctx first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct vmxnet3_tx_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct Vmxnet3_TxDataDesc *tdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) tq->tx_ring.next2fill *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) tq->txdata_desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) memcpy(tdd->data, skb->data, ctx->copy_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) netdev_dbg(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "copy %u bytes to dataRing[%u]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ctx->copy_size, tq->tx_ring.next2fill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) vmxnet3_prepare_inner_tso(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct vmxnet3_tx_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct tcphdr *tcph = inner_tcp_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct iphdr *iph = inner_ip_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (iph->version == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) iph->check = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) IPPROTO_TCP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct ipv6hdr *iph = inner_ipv6_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) IPPROTO_TCP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) vmxnet3_prepare_tso(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct vmxnet3_tx_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct tcphdr *tcph = tcp_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (ctx->ipv4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct iphdr *iph = ip_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) iph->check = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) IPPROTO_TCP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) } else if (ctx->ipv6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) tcp_v6_gso_csum_prep(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static int txd_estimate(const struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * Transmits a pkt thru a given tq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * NETDEV_TX_OK: descriptors are setup successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * NETDEV_TX_OK: error occurred, the pkt is dropped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * NETDEV_TX_BUSY: tx ring is full, queue is stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * Side-effects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * 1. tx ring may be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * 2. tq stats may be updated accordingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * 3. shared->txNumDeferred may be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct vmxnet3_adapter *adapter, struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int num_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int tx_num_deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct vmxnet3_tx_ctx ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) union Vmxnet3_GenericDesc *gdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Use temporary descriptor to avoid touching bits multiple times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) union Vmxnet3_GenericDesc tempTxDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) count = txd_estimate(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ctx.mss = skb_shinfo(skb)->gso_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (ctx.mss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (skb_header_cloned(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (unlikely(pskb_expand_head(skb, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GFP_ATOMIC) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) tq->stats.drop_tso++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) goto drop_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) tq->stats.copy_skb_header++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (skb->encapsulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) vmxnet3_prepare_inner_tso(skb, &ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) vmxnet3_prepare_tso(skb, &ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* non-tso pkts must not use more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * VMXNET3_MAX_TXD_PER_PKT entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (skb_linearize(skb) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) tq->stats.drop_too_many_frags++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) goto drop_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) tq->stats.linearized++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* recalculate the # of descriptors to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) BUG_ON(ret <= 0 && ctx.copy_size != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* hdrs parsed, check against other limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (ctx.mss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (unlikely(ctx.l4_offset + ctx.l4_hdr_size >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) VMXNET3_MAX_TX_BUF_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) tq->stats.drop_oversized_hdr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) goto drop_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (unlikely(ctx.l4_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) skb->csum_offset >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) VMXNET3_MAX_CSUM_OFFSET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) tq->stats.drop_oversized_hdr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) goto drop_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) tq->stats.drop_hdr_inspect_err++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) goto drop_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) spin_lock_irqsave(&tq->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) tq->stats.tx_ring_full++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) netdev_dbg(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) "tx queue stopped on %s, next2comp %u"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) " next2fill %u\n", adapter->netdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) tq->tx_ring.next2comp, tq->tx_ring.next2fill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) vmxnet3_tq_stop(tq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) spin_unlock_irqrestore(&tq->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* fill tx descs related to addr & len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) goto unlock_drop_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* setup the EOP desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* setup the SOP desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) gdesc = &tempTxDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) gdesc->dword[2] = ctx.sop_txd->dword[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) gdesc->dword[3] = ctx.sop_txd->dword[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) gdesc = ctx.sop_txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (ctx.mss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) gdesc->txd.om = VMXNET3_OM_ENCAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) gdesc->txd.msscof = ctx.mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) gdesc->txd.oco = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) gdesc->txd.om = VMXNET3_OM_TSO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) gdesc->txd.msscof = ctx.mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (VMXNET3_VERSION_GE_4(adapter) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) skb->encapsulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) gdesc->txd.hlen = ctx.l4_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ctx.l4_hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) gdesc->txd.om = VMXNET3_OM_ENCAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) gdesc->txd.msscof = 0; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) gdesc->txd.hlen = ctx.l4_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) gdesc->txd.om = VMXNET3_OM_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) gdesc->txd.msscof = ctx.l4_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) skb->csum_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) gdesc->txd.om = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) gdesc->txd.msscof = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) num_pkts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) le32_add_cpu(&tq->shared->txNumDeferred, num_pkts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) tx_num_deferred += num_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (skb_vlan_tag_present(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) gdesc->txd.ti = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) gdesc->txd.tci = skb_vlan_tag_get(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Ensure that the write to (&gdesc->txd)->gen will be observed after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * all other writes to &gdesc->txd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* finally flips the GEN bit of the SOP desc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) VMXNET3_TXD_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Finished updating in bitfields of Tx Desc, so write them in original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) (struct Vmxnet3_TxDesc *)ctx.sop_txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) gdesc = ctx.sop_txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) netdev_dbg(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) (u32)(ctx.sop_txd -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) spin_unlock_irqrestore(&tq->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) tq->shared->txNumDeferred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) VMXNET3_WRITE_BAR0_REG(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) VMXNET3_REG_TXPROD + tq->qid * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) tq->tx_ring.next2fill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) unlock_drop_pkt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) spin_unlock_irqrestore(&tq->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) drop_pkt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) tq->stats.drop_total++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static netdev_tx_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return vmxnet3_tq_xmit(skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) &adapter->tx_queue[skb->queue_mapping],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) adapter, netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) union Vmxnet3_GenericDesc *gdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (gdesc->rcd.v4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) (le32_to_cpu(gdesc->dword[3]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) skb->ip_summed = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) !(le32_to_cpu(gdesc->dword[0]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) WARN_ON_ONCE(gdesc->rcd.frg &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) !(le32_to_cpu(gdesc->dword[0]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) (1 << VMXNET3_RCD_TUC_SHIFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) skb->ip_summed = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) !(le32_to_cpu(gdesc->dword[0]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) WARN_ON_ONCE(gdesc->rcd.frg &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) !(le32_to_cpu(gdesc->dword[0]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (gdesc->rcd.csum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) skb->csum = htons(gdesc->rcd.csum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) skb->ip_summed = CHECKSUM_PARTIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) skb_checksum_none_assert(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) skb_checksum_none_assert(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) rq->stats.drop_err++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (!rcd->fcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) rq->stats.drop_fcs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) rq->stats.drop_total++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * We do not unmap and chain the rx buffer to the skb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * We basically pretend this buffer is not used and will be recycled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * by vmxnet3_rq_alloc_rx_buf()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * ctx->skb may be NULL if this is the first and the only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * desc for the pkt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (ctx->skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dev_kfree_skb_irq(ctx->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ctx->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) union Vmxnet3_GenericDesc *gdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) u32 hlen, maplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct ethhdr *eth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct vlan_ethhdr *veth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct iphdr *ipv4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct ipv6hdr *ipv6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct tcphdr *tcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) } hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) BUG_ON(gdesc->rcd.tcp == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) maplen = skb_headlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (skb->protocol == cpu_to_be16(ETH_P_8021Q) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) skb->protocol == cpu_to_be16(ETH_P_8021AD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) hlen = sizeof(struct vlan_ethhdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) hlen = sizeof(struct ethhdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) hdr.eth = eth_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (gdesc->rcd.v4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) hdr.ptr += hlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) hlen = hdr.ipv4->ihl << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) hdr.ptr += hdr.ipv4->ihl << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) } else if (gdesc->rcd.v6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) hdr.ptr += hlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Use an estimated value, since we also need to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * TSO case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (hdr.ipv6->nexthdr != IPPROTO_TCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) hlen = sizeof(struct ipv6hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) hdr.ptr += sizeof(struct ipv6hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* Non-IP pkt, dont estimate header length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (hlen + sizeof(struct tcphdr) > maplen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return (hlen + (hdr.tcp->doff << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct vmxnet3_adapter *adapter, int quota)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static const u32 rxprod_reg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) u32 num_pkts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) bool skip_page_frags = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct Vmxnet3_RxCompDesc *rcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) u16 segCnt = 0, mss = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct Vmxnet3_RxDesc rxCmdDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct Vmxnet3_RxCompDesc rxComp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) &rxComp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) while (rcd->gen == rq->comp_ring.gen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct vmxnet3_rx_buf_info *rbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct sk_buff *skb, *new_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) struct page *new_page = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dma_addr_t new_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) int num_to_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct Vmxnet3_RxDesc *rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) u32 idx, ring_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct vmxnet3_cmd_ring *ring = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (num_pkts >= quota) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* we may stop even before we see the EOP desc of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * the current pkt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* Prevent any rcd field from being (speculatively) read before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * rcd->gen is read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dma_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) rcd->rqID != rq->dataRingQid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) idx = rcd->rxdIdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ring = rq->rx_ring + ring_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) &rxCmdDesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) rbi = rq->buf_info[ring_idx] + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) BUG_ON(rxd->addr != rbi->dma_addr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) rxd->len != rbi->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (unlikely(rcd->eop && rcd->err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) vmxnet3_rx_error(rq, rcd, ctx, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) goto rcd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (rcd->sop) { /* first buf of the pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) bool rxDataRingUsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) (rcd->rqID != rq->qid &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) rcd->rqID != rq->dataRingQid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (unlikely(rcd->len == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* Pretend the rx buffer is skipped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) BUG_ON(!(rcd->sop && rcd->eop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) netdev_dbg(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) "rxRing[%u][%u] 0 length\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ring_idx, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) goto rcd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) skip_page_frags = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ctx->skb = rbi->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) rxDataRingUsed =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) len = rxDataRingUsed ? rcd->len : rbi->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (new_skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* Skb allocation failed, do not handover this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * skb to stack. Reuse it. Drop the existing pkt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) rq->stats.rx_buf_alloc_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ctx->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) rq->stats.drop_total++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) skip_page_frags = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) goto rcd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (rxDataRingUsed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) size_t sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) BUG_ON(rcd->len > rq->data_ring.desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ctx->skb = new_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) sz = rcd->rxdIdx * rq->data_ring.desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) memcpy(new_skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) &rq->data_ring.base[sz], rcd->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ctx->skb = rbi->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) new_dma_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) dma_map_single(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) new_skb->data, rbi->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (dma_mapping_error(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) new_dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev_kfree_skb(new_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /* Skb allocation failed, do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * handover this skb to stack. Reuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * it. Drop the existing pkt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) rq->stats.rx_buf_alloc_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ctx->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) rq->stats.drop_total++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) skip_page_frags = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) goto rcd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) dma_unmap_single(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) rbi->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) rbi->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* Immediate refill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) rbi->skb = new_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) rbi->dma_addr = new_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) rxd->addr = cpu_to_le64(rbi->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) rxd->len = rbi->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #ifdef VMXNET3_RSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) (adapter->netdev->features & NETIF_F_RXHASH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) skb_set_hash(ctx->skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) le32_to_cpu(rcd->rssHash),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PKT_HASH_TYPE_L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) skb_put(ctx->skb, rcd->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (VMXNET3_VERSION_GE_2(adapter) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct Vmxnet3_RxCompDescExt *rcdlro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) segCnt = rcdlro->segCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) WARN_ON_ONCE(segCnt == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) mss = rcdlro->mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (unlikely(segCnt <= 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) segCnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) segCnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) BUG_ON(ctx->skb == NULL && !skip_page_frags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* non SOP buffer must be type 1 in most cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* If an sop buffer was dropped, skip all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * following non-sop fragments. They will be reused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (skip_page_frags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) goto rcd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (rcd->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) new_page = alloc_page(GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* Replacement page frag could not be allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * Reuse this page. Drop the pkt and free the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * skb which contained this page as a frag. Skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * processing all the following non-sop frags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (unlikely(!new_page)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) rq->stats.rx_buf_alloc_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dev_kfree_skb(ctx->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ctx->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) skip_page_frags = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) goto rcd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) new_dma_addr = dma_map_page(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) new_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) 0, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (dma_mapping_error(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) new_dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) put_page(new_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) rq->stats.rx_buf_alloc_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dev_kfree_skb(ctx->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ctx->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) skip_page_frags = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) goto rcd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) dma_unmap_page(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) rbi->dma_addr, rbi->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) vmxnet3_append_frag(ctx->skb, rcd, rbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /* Immediate refill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) rbi->page = new_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) rbi->dma_addr = new_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) rxd->addr = cpu_to_le64(rbi->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) rxd->len = rbi->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) skb = ctx->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (rcd->eop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) u32 mtu = adapter->netdev->mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) skb->len += skb->data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) vmxnet3_rx_csum(adapter, skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) (union Vmxnet3_GenericDesc *)rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) skb->protocol = eth_type_trans(skb, adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (!rcd->tcp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) !(adapter->netdev->features & NETIF_F_LRO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) goto not_lro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (segCnt != 0 && mss != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) skb_shinfo(skb)->gso_type = rcd->v4 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) skb_shinfo(skb)->gso_size = mss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) skb_shinfo(skb)->gso_segs = segCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) } else if (segCnt != 0 || skb->len > mtu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) u32 hlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) hlen = vmxnet3_get_hdr_len(adapter, skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) (union Vmxnet3_GenericDesc *)rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (hlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) goto not_lro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) skb_shinfo(skb)->gso_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (segCnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) skb_shinfo(skb)->gso_segs = segCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) skb_shinfo(skb)->gso_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) DIV_ROUND_UP(skb->len -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) hlen, segCnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) skb_shinfo(skb)->gso_size = mtu - hlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) not_lro:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (unlikely(rcd->ts))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (adapter->netdev->features & NETIF_F_LRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) napi_gro_receive(&rq->napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ctx->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) num_pkts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) rcd_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* device may have skipped some rx descs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ring->next2comp = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) ring = rq->rx_ring + ring_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* Ensure that the writes to rxd->gen bits will be observed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * after all other writes to rxd objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) while (num_to_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) &rxCmdDesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) BUG_ON(!rxd->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* Recv desc is ready to be used by the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) rxd->gen = ring->gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) vmxnet3_cmd_ring_adv_next2fill(ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) num_to_alloc--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* if needed, update the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (unlikely(rq->shared->updateRxProd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) VMXNET3_WRITE_BAR0_REG(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) rxprod_reg[ring_idx] + rq->qid * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ring->next2fill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) vmxnet3_getRxComp(rcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return num_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u32 i, ring_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct Vmxnet3_RxDesc *rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) for (ring_idx = 0; ring_idx < 2; ring_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) struct Vmxnet3_RxDesc rxDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) vmxnet3_getRxDesc(rxd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) rq->buf_info[ring_idx][i].skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dma_unmap_single(&adapter->pdev->dev, rxd->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) rxd->len, PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) rq->buf_info[ring_idx][i].skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) rq->buf_info[ring_idx][i].page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dma_unmap_page(&adapter->pdev->dev, rxd->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) rxd->len, PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) put_page(rq->buf_info[ring_idx][i].page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) rq->buf_info[ring_idx][i].page = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) rq->rx_ring[ring_idx].next2fill =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) rq->rx_ring[ring_idx].next2comp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) rq->comp_ring.gen = VMXNET3_INIT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) rq->comp_ring.next2proc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* all rx buffers must have already been freed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (rq->buf_info[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) for (j = 0; j < rq->rx_ring[i].size; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) BUG_ON(rq->buf_info[i][j].page != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (rq->rx_ring[i].base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) rq->rx_ring[i].size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * sizeof(struct Vmxnet3_RxDesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) rq->rx_ring[i].base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) rq->rx_ring[i].basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) rq->rx_ring[i].base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (rq->data_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) rq->rx_ring[0].size * rq->data_ring.desc_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) rq->data_ring.base, rq->data_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) rq->data_ring.base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (rq->comp_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * sizeof(struct Vmxnet3_RxCompDesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) rq->comp_ring.base, rq->comp_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) rq->comp_ring.base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (rq->buf_info[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) size_t sz = sizeof(struct vmxnet3_rx_buf_info) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) (rq->rx_ring[0].size + rq->rx_ring[1].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) rq->buf_info_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) rq->buf_info[0] = rq->buf_info[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (rq->data_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) (rq->rx_ring[0].size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) rq->data_ring.desc_size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) rq->data_ring.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) rq->data_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) rq->data_ring.base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) rq->data_ring.desc_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /* initialize buf_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) for (i = 0; i < rq->rx_ring[0].size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /* 1st buf for a pkt is skbuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (i % adapter->rx_buf_per_pkt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) rq->buf_info[0][i].len = adapter->skb_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) } else { /* subsequent bufs for a pkt is frag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) rq->buf_info[0][i].len = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) for (i = 0; i < rq->rx_ring[1].size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) rq->buf_info[1][i].len = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /* reset internal state and allocate buffers for both rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) sizeof(struct Vmxnet3_RxDesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) adapter) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* at least has 1 rx buffer for the 1st ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* reset the comp ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) rq->comp_ring.next2proc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) memset(rq->comp_ring.base, 0, rq->comp_ring.size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) sizeof(struct Vmxnet3_RxCompDesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) rq->comp_ring.gen = VMXNET3_INIT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /* reset rxctx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) rq->rx_ctx.skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* stats are not reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (unlikely(err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) dev_err(&adapter->netdev->dev, "%s: failed to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) "initialize rx queue%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) adapter->netdev->name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) size_t sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct vmxnet3_rx_buf_info *bi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) rq->rx_ring[i].base = dma_alloc_coherent(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) &adapter->pdev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) &rq->rx_ring[i].basePA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (!rq->rx_ring[i].base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) "failed to allocate rx ring %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) rq->data_ring.base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) dma_alloc_coherent(&adapter->pdev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) &rq->data_ring.basePA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (!rq->data_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) "rx data ring will be disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) adapter->rxdataring_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) rq->data_ring.base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) rq->data_ring.desc_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) &rq->comp_ring.basePA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (!rq->comp_ring.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) rq->rx_ring[1].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) bi = dma_alloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (!bi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) rq->buf_info[0] = bi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) rq->buf_info[1] = bi + rq->rx_ring[0].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) vmxnet3_rq_destroy(rq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (unlikely(err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) dev_err(&adapter->netdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) "%s: failed to create rx queue%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) adapter->netdev->name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (!adapter->rxdataring_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) vmxnet3_rq_destroy_all_rxdataring(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) vmxnet3_rq_destroy_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* Multiple queue aware polling function for tx and rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) int rcd_done = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (unlikely(adapter->shared->ecr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) vmxnet3_process_events(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) adapter, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return rcd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) vmxnet3_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) struct vmxnet3_rx_queue *rx_queue = container_of(napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct vmxnet3_rx_queue, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) int rxd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (rxd_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) napi_complete_done(napi, rxd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) vmxnet3_enable_all_intrs(rx_queue->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) return rxd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) * NAPI polling function for MSI-X mode with multiple Rx queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) struct vmxnet3_rx_queue *rq = container_of(napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) struct vmxnet3_rx_queue, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct vmxnet3_adapter *adapter = rq->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) int rxd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /* When sharing interrupt with corresponding tx queue, process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) * tx completions in that queue as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) struct vmxnet3_tx_queue *tq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) &adapter->tx_queue[rq - adapter->rx_queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) vmxnet3_tq_tx_complete(tq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (rxd_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) napi_complete_done(napi, rxd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) return rxd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) * Handle completion interrupts on tx queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * Returns whether or not the intr is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) vmxnet3_msix_tx(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) struct vmxnet3_tx_queue *tq = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) struct vmxnet3_adapter *adapter = tq->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /* Handle the case where only one irq is allocate for all tx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) for (i = 0; i < adapter->num_tx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) vmxnet3_tq_tx_complete(txq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) vmxnet3_tq_tx_complete(tq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * Handle completion interrupts on rx queues. Returns whether or not the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * intr is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) vmxnet3_msix_rx(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) struct vmxnet3_rx_queue *rq = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) struct vmxnet3_adapter *adapter = rq->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* disable intr if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) napi_schedule(&rq->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) *----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * vmxnet3_msix_event --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) * vmxnet3 msix event intr handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) * Result:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) * whether or not the intr is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) *----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) vmxnet3_msix_event(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) struct net_device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) struct vmxnet3_adapter *adapter = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) /* disable intr if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (adapter->shared->ecr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) vmxnet3_process_events(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #endif /* CONFIG_PCI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /* Interrupt handler for vmxnet3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) vmxnet3_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct vmxnet3_adapter *adapter = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (adapter->intr.type == VMXNET3_IT_INTX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if (unlikely(icr == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /* not ours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /* disable intr if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) vmxnet3_disable_all_intrs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) napi_schedule(&adapter->rx_queue[0].napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /* netpoll callback. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) vmxnet3_netpoll(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) switch (adapter->intr.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) case VMXNET3_IT_MSIX: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) case VMXNET3_IT_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) vmxnet3_intr(0, adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #endif /* CONFIG_NET_POLL_CONTROLLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct vmxnet3_intr *intr = &adapter->intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) int err = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) int vector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (adapter->intr.type == VMXNET3_IT_MSIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) for (i = 0; i < adapter->num_tx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) adapter->netdev->name, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) err = request_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) intr->msix_entries[vector].vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) vmxnet3_msix_tx, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) adapter->tx_queue[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) &adapter->tx_queue[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) adapter->netdev->name, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) dev_err(&adapter->netdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) "Failed to request irq for MSIX, %s, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) "error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) adapter->tx_queue[i].name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /* Handle the case where only 1 MSIx was allocated for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) * all tx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) for (; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) adapter->tx_queue[i].comp_ring.intr_idx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) = vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) vector++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) adapter->tx_queue[i].comp_ring.intr_idx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) = vector++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) vector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) adapter->netdev->name, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) adapter->netdev->name, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) err = request_irq(intr->msix_entries[vector].vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) vmxnet3_msix_rx, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) adapter->rx_queue[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) &(adapter->rx_queue[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) "Failed to request irq for MSIX, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) "%s, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) adapter->rx_queue[i].name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) adapter->rx_queue[i].comp_ring.intr_idx = vector++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) sprintf(intr->event_msi_vector_name, "%s-event-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) adapter->netdev->name, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) err = request_irq(intr->msix_entries[vector].vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) vmxnet3_msix_event, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) intr->event_msi_vector_name, adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) intr->event_intr_idx = vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) } else if (intr->type == VMXNET3_IT_MSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) adapter->num_rx_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) adapter->netdev->name, adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) adapter->num_rx_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) err = request_irq(adapter->pdev->irq, vmxnet3_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) IRQF_SHARED, adapter->netdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) intr->num_intrs = vector + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) "Failed to request irq (intr type:%d), error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) intr->type, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) /* Number of rx queues will not change after this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) rq->qid = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) rq->qid2 = i + adapter->num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) rq->dataRingQid = i + 2 * adapter->num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* init our intr settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) for (i = 0; i < intr->num_intrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (adapter->intr.type != VMXNET3_IT_MSIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) adapter->intr.event_intr_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) adapter->tx_queue[i].comp_ring.intr_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) adapter->rx_queue[0].comp_ring.intr_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) netdev_info(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) "intr type %u, mode %u, %u vectors allocated\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) intr->type, intr->mask_mode, intr->num_intrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) struct vmxnet3_intr *intr = &adapter->intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) switch (intr->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) case VMXNET3_IT_MSIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) int i, vector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) for (i = 0; i < adapter->num_tx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) free_irq(intr->msix_entries[vector++].vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) &(adapter->tx_queue[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) free_irq(intr->msix_entries[vector++].vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) &(adapter->rx_queue[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) free_irq(intr->msix_entries[vector].vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) BUG_ON(vector >= intr->num_intrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) case VMXNET3_IT_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) free_irq(adapter->pdev->irq, adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) case VMXNET3_IT_INTX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) free_irq(adapter->pdev->irq, adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* allow untagged pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) if (!(netdev->flags & IFF_PROMISC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) VMXNET3_CMD_UPDATE_VLAN_FILTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) set_bit(vid, adapter->active_vlans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (!(netdev->flags & IFF_PROMISC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) VMXNET3_CMD_UPDATE_VLAN_FILTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) clear_bit(vid, adapter->active_vlans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) static u8 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) vmxnet3_copy_mc(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) u8 *buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) if (sz <= 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) /* We may be called with BH disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) buf = kmalloc(sz, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) netdev_for_each_mc_addr(ha, netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) memcpy(buf + i++ * ETH_ALEN, ha->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) vmxnet3_set_mc(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) struct Vmxnet3_RxFilterConf *rxConf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) &adapter->shared->devRead.rxFilterConf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) u8 *new_table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) dma_addr_t new_table_pa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) bool new_table_pa_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) u32 new_mode = VMXNET3_RXM_UCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) if (netdev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) new_mode |= VMXNET3_RXM_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) vmxnet3_restore_vlan(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (netdev->flags & IFF_BROADCAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) new_mode |= VMXNET3_RXM_BCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (netdev->flags & IFF_ALLMULTI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) new_mode |= VMXNET3_RXM_ALL_MULTI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) if (!netdev_mc_empty(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) new_table = vmxnet3_copy_mc(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (new_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) rxConf->mfTableLen = cpu_to_le16(sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) new_table_pa = dma_map_single(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) &adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) new_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) PCI_DMA_TODEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (!dma_mapping_error(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) new_table_pa)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) new_mode |= VMXNET3_RXM_MCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) new_table_pa_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) rxConf->mfTablePA = cpu_to_le64(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) new_table_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) if (!new_table_pa_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) netdev_info(netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) "failed to copy mcast list, setting ALL_MULTI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) new_mode |= VMXNET3_RXM_ALL_MULTI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) if (!(new_mode & VMXNET3_RXM_MCAST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) rxConf->mfTableLen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) rxConf->mfTablePA = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (new_mode != rxConf->rxMode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) rxConf->rxMode = cpu_to_le32(new_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) VMXNET3_CMD_UPDATE_RX_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) VMXNET3_CMD_UPDATE_VLAN_FILTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) VMXNET3_CMD_UPDATE_MAC_FILTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) if (new_table_pa_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) dma_unmap_single(&adapter->pdev->dev, new_table_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) rxConf->mfTableLen, PCI_DMA_TODEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) kfree(new_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) * Set up driver_shared based on settings in adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) struct Vmxnet3_DriverShared *shared = adapter->shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) struct Vmxnet3_TxQueueConf *tqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) struct Vmxnet3_RxQueueConf *rqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) memset(shared, 0, sizeof(*shared));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) /* driver settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) devRead->misc.driverInfo.version = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) VMXNET3_DRIVER_VERSION_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) *((u32 *)&devRead->misc.driverInfo.gos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /* set up feature flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) if (adapter->netdev->features & NETIF_F_RXCSUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (adapter->netdev->features & NETIF_F_LRO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) devRead->misc.uptFeatures |= UPT1_F_LRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) NETIF_F_GSO_UDP_TUNNEL_CSUM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) devRead->misc.queueDescLen = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* tx queue settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) devRead->misc.numTxQueues = adapter->num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) for (i = 0; i < adapter->num_tx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) tqc = &adapter->tqd_start[i].conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) tqc->ddPA = cpu_to_le64(tq->buf_info_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) tqc->ddLen = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) sizeof(struct vmxnet3_tx_buf_info) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) tqc->txRingSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) tqc->intrIdx = tq->comp_ring.intr_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* rx queue settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) devRead->misc.numRxQueues = adapter->num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) rqc = &adapter->rqd_start[i].conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) rqc->ddPA = cpu_to_le64(rq->buf_info_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) rqc->ddLen = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) sizeof(struct vmxnet3_rx_buf_info) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) (rqc->rxRingSize[0] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) rqc->rxRingSize[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) rqc->intrIdx = rq->comp_ring.intr_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if (VMXNET3_VERSION_GE_3(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) rqc->rxDataRingBasePA =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) cpu_to_le64(rq->data_ring.basePA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) rqc->rxDataRingDescSize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) cpu_to_le16(rq->data_ring.desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) #ifdef VMXNET3_RSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (adapter->rss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) struct UPT1_RSSConf *rssConf = adapter->rss_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) devRead->misc.uptFeatures |= UPT1_F_RSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) devRead->misc.numRxQueues = adapter->num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) UPT1_RSS_HASH_TYPE_IPV4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) UPT1_RSS_HASH_TYPE_TCP_IPV6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) UPT1_RSS_HASH_TYPE_IPV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) for (i = 0; i < rssConf->indTableSize; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) rssConf->indTable[i] = ethtool_rxfh_indir_default(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) i, adapter->num_rx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) devRead->rssConfDesc.confVer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) devRead->rssConfDesc.confPA =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) cpu_to_le64(adapter->rss_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) #endif /* VMXNET3_RSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) /* intr settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) devRead->intrConf.autoMask = adapter->intr.mask_mode ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) VMXNET3_IMM_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) devRead->intrConf.numIntrs = adapter->intr.num_intrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) for (i = 0; i < adapter->intr.num_intrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) /* rx filter settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) devRead->rxFilterConf.rxMode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) vmxnet3_restore_vlan(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) /* the rest are already zeroed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) struct Vmxnet3_DriverShared *shared = adapter->shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) if (!VMXNET3_VERSION_GE_3(adapter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) cmdInfo->varConf.confVer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) cmdInfo->varConf.confLen =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) cpu_to_le32(sizeof(*adapter->coal_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (adapter->default_coal_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) VMXNET3_CMD_GET_COALESCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) VMXNET3_CMD_SET_COALESCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) struct Vmxnet3_DriverShared *shared = adapter->shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if (!VMXNET3_VERSION_GE_4(adapter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (adapter->default_rss_fields) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) VMXNET3_CMD_GET_RSS_FIELDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) adapter->rss_fields =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) cmdInfo->setRssFields = adapter->rss_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) VMXNET3_CMD_SET_RSS_FIELDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) /* Not all requested RSS may get applied, so get and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) * cache what was actually applied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) VMXNET3_CMD_GET_RSS_FIELDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) adapter->rss_fields =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) " ring sizes %u %u %u\n", adapter->netdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) adapter->skb_buf_size, adapter->rx_buf_per_pkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) adapter->tx_queue[0].tx_ring.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) adapter->rx_queue[0].rx_ring[0].size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) adapter->rx_queue[0].rx_ring[1].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) vmxnet3_tq_init_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) err = vmxnet3_rq_init_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) "Failed to init rx queue error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) goto rq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) err = vmxnet3_request_irqs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) "Failed to setup irq for error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) goto irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) vmxnet3_setup_driver_shared(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) adapter->shared_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) adapter->shared_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) VMXNET3_CMD_ACTIVATE_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) "Failed to activate dev: error %u\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) goto activate_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) vmxnet3_init_coalesce(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) vmxnet3_init_rssfields(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) VMXNET3_WRITE_BAR0_REG(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) adapter->rx_queue[i].rx_ring[0].next2fill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) (i * VMXNET3_REG_ALIGN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) adapter->rx_queue[i].rx_ring[1].next2fill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) /* Apply the rx filter settins last. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) vmxnet3_set_mc(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) * Check link state when first activating device. It will start the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) * tx queue if the link is up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) vmxnet3_check_link(adapter, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) napi_enable(&adapter->rx_queue[i].napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) vmxnet3_enable_all_intrs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) activate_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) vmxnet3_free_irqs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) irq_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) rq_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) /* free up buffers we allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) vmxnet3_rq_cleanup_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) VMXNET3_CMD_QUIESCE_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) vmxnet3_disable_all_intrs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) napi_disable(&adapter->rx_queue[i].napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) netif_tx_disable(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) adapter->link_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) netif_carrier_off(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) vmxnet3_tq_cleanup_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) vmxnet3_rq_cleanup_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) vmxnet3_free_irqs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) tmp = *(u32 *)mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) tmp = (mac[5] << 8) | mac[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) struct sockaddr *addr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) vmxnet3_write_mac_addr(adapter, addr->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) /* ==================== initialization and cleanup routines ============ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) unsigned long mmio_start, mmio_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) struct pci_dev *pdev = adapter->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) err = pci_request_selected_regions(pdev, (1 << 2) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) vmxnet3_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) "Failed to request region for adapter: error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) goto err_enable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) mmio_start = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) mmio_len = pci_resource_len(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) if (!adapter->hw_addr0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) dev_err(&pdev->dev, "Failed to map bar0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) mmio_start = pci_resource_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) mmio_len = pci_resource_len(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) if (!adapter->hw_addr1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) dev_err(&pdev->dev, "Failed to map bar1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) goto err_bar1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) err_bar1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) iounmap(adapter->hw_addr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) pci_release_selected_regions(pdev, (1 << 2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) err_enable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) BUG_ON(!adapter->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) iounmap(adapter->hw_addr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) iounmap(adapter->hw_addr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) pci_disable_device(adapter->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) size_t sz, i, ring0_size, ring1_size, comp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) VMXNET3_MAX_ETH_HDR_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) adapter->skb_buf_size = adapter->netdev->mtu +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) VMXNET3_MAX_ETH_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) adapter->rx_buf_per_pkt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) VMXNET3_MAX_ETH_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) * for simplicity, force the ring0 size to be a multiple of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) ring0_size = adapter->rx_queue[0].rx_ring[0].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) ring0_size = (ring0_size + sz - 1) / sz * sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) sz * sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) ring1_size = adapter->rx_queue[0].rx_ring[1].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) ring1_size = (ring1_size + sz - 1) / sz * sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) sz * sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) comp_size = ring0_size + ring1_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) rq->rx_ring[0].size = ring0_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) rq->rx_ring[1].size = ring1_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) rq->comp_ring.size = comp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) u32 rx_ring_size, u32 rx_ring2_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) u16 txdata_desc_size, u16 rxdata_desc_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) int err = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) for (i = 0; i < adapter->num_tx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) tq->tx_ring.size = tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) tq->data_ring.size = tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) tq->comp_ring.size = tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) tq->txdata_desc_size = txdata_desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) tq->shared = &adapter->tqd_start[i].ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) tq->stopped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) tq->adapter = adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) tq->qid = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) err = vmxnet3_tq_create(tq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) * Too late to change num_tx_queues. We cannot do away with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) * lesser number of queues than what we asked for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) goto queue_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) vmxnet3_adjust_rx_ring_size(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) /* qid and qid2 for rx queues will be assigned later when num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) * of rx queues is finalized after allocating intrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) rq->shared = &adapter->rqd_start[i].ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) rq->adapter = adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) rq->data_ring.desc_size = rxdata_desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) err = vmxnet3_rq_create(rq, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) "Could not allocate any rx queues. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) "Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) goto queue_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) netdev_info(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) "Number of rx queues changed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) "to : %d.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) adapter->num_rx_queues = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) if (!adapter->rxdataring_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) vmxnet3_rq_destroy_all_rxdataring(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) queue_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) vmxnet3_tq_destroy_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) vmxnet3_open(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) struct vmxnet3_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) for (i = 0; i < adapter->num_tx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) spin_lock_init(&adapter->tx_queue[i].tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) if (VMXNET3_VERSION_GE_3(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) u16 txdata_desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) VMXNET3_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) adapter->txdata_desc_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) sizeof(struct Vmxnet3_TxDataDesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) adapter->txdata_desc_size = txdata_desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) err = vmxnet3_create_queues(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) adapter->tx_ring_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) adapter->rx_ring_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) adapter->rx_ring2_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) adapter->txdata_desc_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) adapter->rxdata_desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) goto queue_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) err = vmxnet3_activate_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) goto activate_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) activate_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) vmxnet3_rq_destroy_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) vmxnet3_tq_destroy_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) queue_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) vmxnet3_close(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) * Reset_work may be in the middle of resetting the device, wait for its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) * completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) vmxnet3_quiesce_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) vmxnet3_rq_destroy_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) vmxnet3_tq_destroy_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) vmxnet3_force_close(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) * vmxnet3_close() will deadlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) /* we need to enable NAPI, otherwise dev_close will deadlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) napi_enable(&adapter->rx_queue[i].napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) * Need to clear the quiesce bit to ensure that vmxnet3_close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) * can quiesce the device properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) dev_close(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) netdev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) * Reset_work may be in the middle of resetting the device, wait for its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) * completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) if (netif_running(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) vmxnet3_quiesce_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) vmxnet3_reset_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) /* we need to re-create the rx queue based on the new mtu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) vmxnet3_rq_destroy_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) vmxnet3_adjust_rx_ring_size(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) err = vmxnet3_rq_create_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) netdev_err(netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) "failed to re-create rx queues, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) " error %d. Closing it.\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) err = vmxnet3_activate_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) netdev_err(netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) "failed to re-activate, error %d. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) "Closing it\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) vmxnet3_force_close(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) struct net_device *netdev = adapter->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) NETIF_F_LRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) if (VMXNET3_VERSION_GE_4(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) NETIF_F_GSO_UDP_TUNNEL_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) NETIF_F_GSO_UDP_TUNNEL_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) if (dma64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) netdev->hw_features |= NETIF_F_HIGHDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) netdev->vlan_features = netdev->hw_features &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) ~(NETIF_F_HW_VLAN_CTAG_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) NETIF_F_HW_VLAN_CTAG_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) *(u32 *)mac = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) mac[4] = tmp & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) mac[5] = (tmp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) * Enable MSIx vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) * Returns :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) * were enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) * number of vectors which were enabled otherwise (this number is greater
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) * than VMXNET3_LINUX_MIN_MSIX_VECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) int ret = pci_enable_msix_range(adapter->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) adapter->intr.msix_entries, nvec, nvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) dev_err(&adapter->netdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) "Failed to enable %d MSI-X, trying %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) ret = pci_enable_msix_range(adapter->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) adapter->intr.msix_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) VMXNET3_LINUX_MIN_MSIX_VECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) VMXNET3_LINUX_MIN_MSIX_VECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) dev_err(&adapter->netdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) "Failed to enable MSI-X, error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) #endif /* CONFIG_PCI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) /* intr settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) VMXNET3_CMD_GET_CONF_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) adapter->intr.type = cfg & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) adapter->intr.mask_mode = (cfg >> 2) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) if (adapter->intr.type == VMXNET3_IT_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) adapter->intr.type = VMXNET3_IT_MSIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) if (adapter->intr.type == VMXNET3_IT_MSIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) int i, nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) 1 : adapter->num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) 0 : adapter->num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) nvec += 1; /* for link event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) for (i = 0; i < nvec; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) adapter->intr.msix_entries[i].entry = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) if (nvec < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) goto msix_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) /* If we cannot allocate one MSIx vector per queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) * then limit the number of rx queues to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) || adapter->num_rx_queues != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) adapter->share_intr = VMXNET3_INTR_TXSHARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) netdev_err(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) "Number of rx queues : 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) adapter->num_rx_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) adapter->intr.num_intrs = nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) msix_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) /* If we cannot allocate MSIx vectors use only one rx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) dev_info(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) "Failed to enable MSI-X, error %d. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) "Limiting #rx queues to 1, try MSI.\n", nvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) adapter->intr.type = VMXNET3_IT_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) if (adapter->intr.type == VMXNET3_IT_MSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) if (!pci_enable_msi(adapter->pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) adapter->num_rx_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) adapter->intr.num_intrs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) #endif /* CONFIG_PCI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) adapter->num_rx_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) dev_info(&adapter->netdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) "Using INTx interrupt, #Rx queues: 1.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) adapter->intr.type = VMXNET3_IT_INTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) /* INT-X related setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) adapter->intr.num_intrs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) if (adapter->intr.type == VMXNET3_IT_MSIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) pci_disable_msix(adapter->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) else if (adapter->intr.type == VMXNET3_IT_MSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) pci_disable_msi(adapter->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) adapter->tx_timeout_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) netdev_err(adapter->netdev, "tx hang\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) schedule_work(&adapter->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) vmxnet3_reset_work(struct work_struct *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) struct vmxnet3_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) adapter = container_of(data, struct vmxnet3_adapter, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) /* if another thread is resetting the device, no need to proceed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) /* if the device is closed, we must leave it alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) if (netif_running(adapter->netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) netdev_notice(adapter->netdev, "resetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) vmxnet3_quiesce_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) vmxnet3_reset_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) vmxnet3_activate_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) netdev_info(adapter->netdev, "already closed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) netif_wake_queue(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) vmxnet3_probe_device(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) static const struct net_device_ops vmxnet3_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) .ndo_open = vmxnet3_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) .ndo_stop = vmxnet3_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .ndo_start_xmit = vmxnet3_xmit_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) .ndo_set_mac_address = vmxnet3_set_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) .ndo_change_mtu = vmxnet3_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) .ndo_fix_features = vmxnet3_fix_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) .ndo_set_features = vmxnet3_set_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) .ndo_features_check = vmxnet3_features_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) .ndo_get_stats64 = vmxnet3_get_stats64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) .ndo_tx_timeout = vmxnet3_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) .ndo_set_rx_mode = vmxnet3_set_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) .ndo_poll_controller = vmxnet3_netpoll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) bool dma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) u32 ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) struct vmxnet3_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) u8 mac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) int num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) int num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) if (!pci_msi_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) enable_mq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) #ifdef VMXNET3_RSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) if (enable_mq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) (int)num_online_cpus());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) num_rx_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) num_rx_queues = rounddown_pow_of_two(num_rx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) if (enable_mq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) (int)num_online_cpus());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) num_tx_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) num_tx_queues = rounddown_pow_of_two(num_tx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) max(num_tx_queues, num_rx_queues));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) "# of Tx queues : %d, # of Rx queues : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) num_tx_queues, num_rx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) if (!netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) pci_set_drvdata(pdev, netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) adapter->netdev = netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) adapter->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) "pci_set_consistent_dma_mask failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) goto err_set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) dma64 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) "pci_set_dma_mask failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) goto err_set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) dma64 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) spin_lock_init(&adapter->cmd_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) sizeof(struct vmxnet3_adapter),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) PCI_DMA_TODEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) dev_err(&pdev->dev, "Failed to map dma\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) goto err_set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) adapter->shared = dma_alloc_coherent(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) &adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) sizeof(struct Vmxnet3_DriverShared),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) &adapter->shared_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) if (!adapter->shared) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) dev_err(&pdev->dev, "Failed to allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) goto err_alloc_shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) adapter->num_rx_queues = num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) adapter->num_tx_queues = num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) adapter->rx_buf_per_pkt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) &adapter->queue_desc_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) if (!adapter->tqd_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) dev_err(&pdev->dev, "Failed to allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) goto err_alloc_queue_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) adapter->num_tx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) sizeof(struct Vmxnet3_PMConf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) &adapter->pm_conf_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) if (adapter->pm_conf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) goto err_alloc_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) #ifdef VMXNET3_RSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) sizeof(struct UPT1_RSSConf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) &adapter->rss_conf_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) if (adapter->rss_conf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) goto err_alloc_rss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) #endif /* VMXNET3_RSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) err = vmxnet3_alloc_pci_resources(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) goto err_alloc_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) if (ver & (1 << VMXNET3_REV_4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) VMXNET3_WRITE_BAR1_REG(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) VMXNET3_REG_VRRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) 1 << VMXNET3_REV_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) adapter->version = VMXNET3_REV_4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) } else if (ver & (1 << VMXNET3_REV_3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) VMXNET3_WRITE_BAR1_REG(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) VMXNET3_REG_VRRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) 1 << VMXNET3_REV_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) adapter->version = VMXNET3_REV_3 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) } else if (ver & (1 << VMXNET3_REV_2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) VMXNET3_WRITE_BAR1_REG(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) VMXNET3_REG_VRRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) 1 << VMXNET3_REV_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) adapter->version = VMXNET3_REV_2 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) } else if (ver & (1 << VMXNET3_REV_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) VMXNET3_WRITE_BAR1_REG(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) VMXNET3_REG_VRRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) 1 << VMXNET3_REV_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) adapter->version = VMXNET3_REV_1 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) "Incompatible h/w version (0x%x) for adapter\n", ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) goto err_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) if (ver & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) "Incompatible upt version (0x%x) for adapter\n", ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) goto err_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) if (VMXNET3_VERSION_GE_3(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) adapter->coal_conf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) sizeof(struct Vmxnet3_CoalesceScheme)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) &adapter->coal_conf_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) if (!adapter->coal_conf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) goto err_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) adapter->default_coal_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) if (VMXNET3_VERSION_GE_4(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) adapter->default_rss_fields = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) SET_NETDEV_DEV(netdev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) vmxnet3_declare_features(adapter, dma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) if (adapter->num_tx_queues == adapter->num_rx_queues)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) adapter->share_intr = VMXNET3_INTR_DONTSHARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) vmxnet3_alloc_intr_resources(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) #ifdef VMXNET3_RSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) if (adapter->num_rx_queues > 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) adapter->intr.type == VMXNET3_IT_MSIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) adapter->rss = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) netdev->hw_features |= NETIF_F_RXHASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) netdev->features |= NETIF_F_RXHASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) dev_dbg(&pdev->dev, "RSS is enabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) adapter->rss = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) vmxnet3_read_mac_addr(adapter, mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) memcpy(netdev->dev_addr, mac, netdev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) netdev->netdev_ops = &vmxnet3_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) vmxnet3_set_ethtool_ops(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) netdev->watchdog_timeo = 5 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) /* MTU range: 60 - 9000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) netdev->min_mtu = VMXNET3_MIN_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) netdev->max_mtu = VMXNET3_MAX_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) INIT_WORK(&adapter->work, vmxnet3_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) if (adapter->intr.type == VMXNET3_IT_MSIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) for (i = 0; i < adapter->num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) netif_napi_add(adapter->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) &adapter->rx_queue[i].napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) vmxnet3_poll_rx_only, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) vmxnet3_poll, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) netif_carrier_off(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) err = register_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) dev_err(&pdev->dev, "Failed to register adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) vmxnet3_check_link(adapter, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) if (VMXNET3_VERSION_GE_3(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) sizeof(struct Vmxnet3_CoalesceScheme),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) adapter->coal_conf, adapter->coal_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) vmxnet3_free_intr_resources(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) err_ver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) vmxnet3_free_pci_resources(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) err_alloc_pci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) #ifdef VMXNET3_RSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) adapter->rss_conf, adapter->rss_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) err_alloc_rss:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) adapter->pm_conf, adapter->pm_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) err_alloc_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) adapter->queue_desc_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) err_alloc_queue_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) sizeof(struct Vmxnet3_DriverShared),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) adapter->shared, adapter->shared_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) err_alloc_shared:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) err_set_mask:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) free_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) vmxnet3_remove_device(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) struct net_device *netdev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) int size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) int num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) #ifdef VMXNET3_RSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) if (enable_mq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) (int)num_online_cpus());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) num_rx_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) num_rx_queues = rounddown_pow_of_two(num_rx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) cancel_work_sync(&adapter->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) unregister_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) vmxnet3_free_intr_resources(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) vmxnet3_free_pci_resources(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) if (VMXNET3_VERSION_GE_3(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) sizeof(struct Vmxnet3_CoalesceScheme),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) adapter->coal_conf, adapter->coal_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) #ifdef VMXNET3_RSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) adapter->rss_conf, adapter->rss_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) adapter->pm_conf, adapter->pm_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) adapter->queue_desc_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) sizeof(struct Vmxnet3_DriverShared),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) adapter->shared, adapter->shared_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) free_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) static void vmxnet3_shutdown_device(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) struct net_device *netdev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) /* Reset_work may be in the middle of resetting the device, wait for its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) * completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) &adapter->state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) VMXNET3_CMD_QUIESCE_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) vmxnet3_disable_all_intrs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) vmxnet3_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) struct pci_dev *pdev = to_pci_dev(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) struct net_device *netdev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) struct Vmxnet3_PMConf *pmConf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) struct ethhdr *ehdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) struct arphdr *ahdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) u8 *arpreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) struct in_device *in_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) struct in_ifaddr *ifa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) if (!netif_running(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) for (i = 0; i < adapter->num_rx_queues; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) napi_disable(&adapter->rx_queue[i].napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) vmxnet3_disable_all_intrs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) vmxnet3_free_irqs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) vmxnet3_free_intr_resources(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) netif_device_detach(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) /* Create wake-up filters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) pmConf = adapter->pm_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) memset(pmConf, 0, sizeof(*pmConf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) if (adapter->wol & WAKE_UCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) pmConf->filters[i].patternSize = ETH_ALEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) pmConf->filters[i].maskSize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) if (adapter->wol & WAKE_ARP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) in_dev = __in_dev_get_rcu(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) if (!in_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) goto skip_arp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) ifa = rcu_dereference(in_dev->ifa_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) if (!ifa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) goto skip_arp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) sizeof(struct arphdr) + /* ARP header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) 2 * ETH_ALEN + /* 2 Ethernet addresses*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) 2 * sizeof(u32); /*2 IPv4 addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) pmConf->filters[i].maskSize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) (pmConf->filters[i].patternSize - 1) / 8 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) /* ETH_P_ARP in Ethernet header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) ehdr->h_proto = htons(ETH_P_ARP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) /* ARPOP_REQUEST in ARP header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) ahdr->ar_op = htons(ARPOP_REQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) arpreq = (u8 *)(ahdr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) /* The Unicast IPv4 address in 'tip' field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) arpreq += 2 * ETH_ALEN + sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) *(__be32 *)arpreq = ifa->ifa_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) /* The mask for the relevant bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) pmConf->filters[i].mask[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) pmConf->filters[i].mask[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) skip_arp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) if (adapter->wol & WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) pmConf->numFilters = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) *pmConf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) adapter->shared->devRead.pmConfDesc.confPA =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) cpu_to_le64(adapter->pm_conf_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) VMXNET3_CMD_UPDATE_PMCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) adapter->wol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) vmxnet3_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) struct pci_dev *pdev = to_pci_dev(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) struct net_device *netdev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) struct vmxnet3_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) if (!netif_running(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) err = pci_enable_device_mem(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) if (err != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) pci_enable_wake(pdev, PCI_D0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) vmxnet3_alloc_intr_resources(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) /* During hibernate and suspend, device has to be reinitialized as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) * device state need not be preserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) /* Need not check adapter state as other reset tasks cannot run during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) * device resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) spin_lock_irqsave(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) VMXNET3_CMD_QUIESCE_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) spin_unlock_irqrestore(&adapter->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) vmxnet3_tq_cleanup_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) vmxnet3_rq_cleanup_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) vmxnet3_reset_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) err = vmxnet3_activate_dev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) netdev_err(netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) "failed to re-activate on resume, error: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) vmxnet3_force_close(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) netif_device_attach(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) static const struct dev_pm_ops vmxnet3_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) .suspend = vmxnet3_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) .resume = vmxnet3_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) .freeze = vmxnet3_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) .restore = vmxnet3_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) static struct pci_driver vmxnet3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) .name = vmxnet3_driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) .id_table = vmxnet3_pciid_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) .probe = vmxnet3_probe_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) .remove = vmxnet3_remove_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) .shutdown = vmxnet3_shutdown_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) .driver.pm = &vmxnet3_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) vmxnet3_init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) VMXNET3_DRIVER_VERSION_REPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) return pci_register_driver(&vmxnet3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) module_init(vmxnet3_init_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) vmxnet3_exit_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) pci_unregister_driver(&vmxnet3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) module_exit(vmxnet3_exit_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) MODULE_AUTHOR("VMware, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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