^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Linux driver for VMware's vmxnet3 ethernet NIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Free Software Foundation; version 2 of the License and no later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * NON INFRINGEMENT. See the GNU General Public License for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * The full GNU General Public License is included in this distribution in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * the file called "COPYING".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Maintained by: pv-drivers@vmware.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef _VMXNET3_DEFS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define _VMXNET3_DEFS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "upt1_defs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* all registers are 32 bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* BAR 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) VMXNET3_REG_CMD = 0x20, /* Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) VMXNET3_REG_MACH = 0x30, /* MAC Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) VMXNET3_REG_ECR = 0x40 /* Event Cause Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* BAR 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VMXNET3_REG_ALIGN_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* I/O Mapped access to registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VMXNET3_IO_TYPE_PT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VMXNET3_IO_TYPE_VD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) VMXNET3_CMD_QUIESCE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) VMXNET3_CMD_RESET_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) VMXNET3_CMD_UPDATE_RX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) VMXNET3_CMD_UPDATE_MAC_FILTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) VMXNET3_CMD_UPDATE_VLAN_FILTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) VMXNET3_CMD_UPDATE_RSSIDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) VMXNET3_CMD_UPDATE_IML,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) VMXNET3_CMD_UPDATE_PMCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) VMXNET3_CMD_UPDATE_FEATURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) VMXNET3_CMD_RESERVED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) VMXNET3_CMD_LOAD_PLUGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) VMXNET3_CMD_RESERVED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) VMXNET3_CMD_RESERVED3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) VMXNET3_CMD_SET_COALESCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) VMXNET3_CMD_REGISTER_MEMREGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) VMXNET3_CMD_SET_RSS_FIELDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) VMXNET3_CMD_FIRST_GET = 0xF00D0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) VMXNET3_CMD_GET_STATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) VMXNET3_CMD_GET_LINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) VMXNET3_CMD_GET_PERM_MAC_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) VMXNET3_CMD_GET_PERM_MAC_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) VMXNET3_CMD_GET_DID_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) VMXNET3_CMD_GET_DID_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) VMXNET3_CMD_GET_DEV_EXTRA_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) VMXNET3_CMD_GET_CONF_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) VMXNET3_CMD_GET_RESERVED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) VMXNET3_CMD_GET_COALESCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) VMXNET3_CMD_GET_RSS_FIELDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Little Endian layout of bitfields -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Byte 0 : 7.....len.....0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Byte 1 : oco gen 13.len.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Byte 2 : 5.msscof.0 ext1 dtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Byte 3 : 13...msscof...6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Big Endian layout of bitfields -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Byte 0: 13...msscof...6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Byte 1 : 5.msscof.0 ext1 dtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Byte 2 : oco gen 13.len.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Byte 3 : 7.....len.....0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Thus, le32_to_cpu on the dword will allow the big endian driver to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * the bit fields correctly. And cpu_to_le32 will convert bitfields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * bit fields written by big endian driver to format required by device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct Vmxnet3_TxDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 msscof:14; /* MSS, checksum offset, flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 ext1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 dtype:1; /* descriptor type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 oco:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 gen:1; /* generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 len:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 len:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 gen:1; /* generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 oco:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 dtype:1; /* descriptor type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 ext1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 msscof:14; /* MSS, checksum offset, flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 tci:16; /* Tag to Insert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 ti:1; /* VLAN Tag Insertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 ext2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cq:1; /* completion request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 eop:1; /* End Of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 om:2; /* offload mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 hlen:10; /* header len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 hlen:10; /* header len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 om:2; /* offload mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 eop:1; /* End Of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 cq:1; /* completion request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 ext2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 ti:1; /* VLAN Tag Insertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 tci:16; /* Tag to Insert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* TxDesc.OM values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VMXNET3_OM_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VMXNET3_OM_ENCAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VMXNET3_OM_CSUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VMXNET3_OM_TSO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* fields in TxDesc we access w/o using bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VMXNET3_TXD_EOP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VMXNET3_TXD_CQ_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VMXNET3_TXD_GEN_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VMXNET3_HDR_COPY_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct Vmxnet3_TxDataDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 data[VMXNET3_HDR_COPY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) typedef u8 Vmxnet3_RxDataDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define VMXNET3_TCD_GEN_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define VMXNET3_TCD_GEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define VMXNET3_TCD_TXIDX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define VMXNET3_TCD_TXIDX_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define VMXNET3_TCD_GEN_DWORD_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct Vmxnet3_TxCompDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 txdIdx:12; /* Index of the EOP TxDesc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 ext1:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __le32 ext2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __le32 ext3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 rsvd:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 type:7; /* completion type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 gen:1; /* generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct Vmxnet3_RxDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 gen:1; /* Generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 rsvd:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 dtype:1; /* Descriptor type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 btype:1; /* Buffer Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 len:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 len:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 btype:1; /* Buffer Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 dtype:1; /* Descriptor type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 rsvd:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 gen:1; /* Generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 ext1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* values of RXD.BTYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* fields in RxDesc we access w/o using bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define VMXNET3_RXD_BTYPE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define VMXNET3_RXD_GEN_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define VMXNET3_RCD_HDR_INNER_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct Vmxnet3_RxCompDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 ext2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 cnc:1; /* Checksum Not Calculated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 rssType:4; /* RSS hash type used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 rqID:10; /* rx queue/ring ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 sop:1; /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 eop:1; /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 ext1:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 rxdIdx:12; /* Index of the RxDesc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 rxdIdx:12; /* Index of the RxDesc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 ext1:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 eop:1; /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 sop:1; /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 rqID:10; /* rx queue/ring ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 rssType:4; /* RSS hash type used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 cnc:1; /* Checksum Not Calculated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 ext2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __le32 rssHash; /* RSS hash value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 tci:16; /* Tag stripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 ts:1; /* Tag is stripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 err:1; /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 len:14; /* data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 len:14; /* data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 err:1; /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 ts:1; /* Tag is stripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 tci:16; /* Tag stripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 gen:1; /* generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 type:7; /* completion type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 fcs:1; /* Frame CRC correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 frg:1; /* IP Fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 v4:1; /* IPv4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 v6:1; /* IPv6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 ipc:1; /* IP Checksum Correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 tcp:1; /* TCP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 udp:1; /* UDP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 tuc:1; /* TCP/UDP Checksum Correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 csum:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 csum:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 tuc:1; /* TCP/UDP Checksum Correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 udp:1; /* UDP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 tcp:1; /* TCP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 ipc:1; /* IP Checksum Correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 v6:1; /* IPv6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 v4:1; /* IPv4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 frg:1; /* IP Fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 fcs:1; /* Frame CRC correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 type:7; /* completion type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 gen:1; /* generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct Vmxnet3_RxCompDescExt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __le32 dword1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 segCnt; /* Number of aggregated packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 dupAckCnt; /* Number of duplicate Acks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) __le16 tsDelta; /* TCP timestamp difference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __le32 dword2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 gen:1; /* generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 type:7; /* completion type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 fcs:1; /* Frame CRC correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 frg:1; /* IP Fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 v4:1; /* IPv4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 v6:1; /* IPv6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 ipc:1; /* IP Checksum Correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 tcp:1; /* TCP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 udp:1; /* UDP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 tuc:1; /* TCP/UDP Checksum Correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 mss:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 mss:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 tuc:1; /* TCP/UDP Checksum Correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 udp:1; /* UDP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 tcp:1; /* TCP packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 ipc:1; /* IP Checksum Correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 v6:1; /* IPv6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 v4:1; /* IPv4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 frg:1; /* IP Fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 fcs:1; /* Frame CRC correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 type:7; /* completion type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 gen:1; /* generation bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define VMXNET3_RCD_TUC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define VMXNET3_RCD_IPC_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define VMXNET3_RCD_TYPE_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define VMXNET3_RCD_GEN_SHIFT 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* csum OK for TCP/UDP pkts over IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 1 << VMXNET3_RCD_IPC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define VMXNET3_TXD_GEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define VMXNET3_TXD_EOP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* value of RxCompDesc.rssType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) VMXNET3_RCD_RSS_TYPE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* a union for accessing all cmd/completion descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) union Vmxnet3_GenericDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __le64 qword[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __le32 dword[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) __le16 word[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct Vmxnet3_TxDesc txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct Vmxnet3_RxDesc rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct Vmxnet3_TxCompDesc tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct Vmxnet3_RxCompDesc rcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct Vmxnet3_RxCompDescExt rcdExt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define VMXNET3_INIT_GEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Max size of a single tx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* # of tx desc needed for a tx buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) VMXNET3_MAX_TX_BUF_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* max # of tx descs for a non-tso pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define VMXNET3_MAX_TXD_PER_PKT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Max size of a single rx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Minimum size of a type 0 buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define VMXNET3_MIN_T0_BUF_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define VMXNET3_MAX_CSUM_OFFSET 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Ring base address alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define VMXNET3_RING_BA_ALIGN 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Ring size must be a multiple of 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define VMXNET3_RING_SIZE_ALIGN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Tx Data Ring buffer size must be a multiple of 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Rx Data Ring buffer size must be a multiple of 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Max ring size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define VMXNET3_TX_RING_MAX_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define VMXNET3_TC_RING_MAX_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define VMXNET3_RX_RING_MAX_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define VMXNET3_RX_RING2_MAX_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define VMXNET3_RC_RING_MAX_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define VMXNET3_TXDATA_DESC_MIN_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* a list of reasons for queue stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* completion descriptor types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) VMXNET3_GOS_BITS_UNK = 0, /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) VMXNET3_GOS_BITS_32 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) VMXNET3_GOS_BITS_64 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define VMXNET3_GOS_TYPE_LINUX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct Vmxnet3_GOSInfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 gosMisc:10; /* other info about gos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 gosVer:16; /* gos version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 gosType:4; /* which guest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 gosBits:2; /* 32-bit or 64-bit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 gosBits:2; /* 32-bit or 64-bit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 gosType:4; /* which guest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 gosVer:16; /* gos version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 gosMisc:10; /* other info about gos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #endif /* __BIG_ENDIAN_BITFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct Vmxnet3_DriverInfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) __le32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct Vmxnet3_GOSInfo gos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) __le32 vmxnet3RevSpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __le32 uptVerSpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define VMXNET3_REV1_MAGIC 3133079265u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * QueueDescPA must be 128 bytes aligned. It points to an array of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define VMXNET3_QUEUE_DESC_ALIGN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct Vmxnet3_MiscConf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct Vmxnet3_DriverInfo driverInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __le64 uptFeatures;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) __le64 ddPA; /* driver data PA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) __le64 queueDescPA; /* queue descriptor table PA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) __le32 ddLen; /* driver data len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __le32 queueDescLen; /* queue desc. table len in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) __le32 mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __le16 maxNumRxSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u8 numTxQueues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 numRxQueues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) __le32 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct Vmxnet3_TxQueueConf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __le64 txRingBasePA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __le64 dataRingBasePA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __le64 compRingBasePA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __le64 ddPA; /* driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __le64 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __le32 txRingSize; /* # of tx desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __le32 dataRingSize; /* # of data desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __le32 compRingSize; /* # of comp desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) __le32 ddLen; /* size of driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 intrIdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 _pad1[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) __le16 txDataRingDescSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 _pad2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct Vmxnet3_RxQueueConf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) __le64 rxRingBasePA[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) __le64 compRingBasePA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) __le64 ddPA; /* driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __le64 rxDataRingBasePA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __le32 rxRingSize[2]; /* # of rx desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __le32 compRingSize; /* # of rx comp desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __le32 ddLen; /* size of driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 intrIdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 _pad1[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) __le16 rxDataRingDescSize; /* size of rx data ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 _pad2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) enum vmxnet3_intr_mask_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) VMXNET3_IMM_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) VMXNET3_IMM_ACTIVE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) VMXNET3_IMM_LAZY = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) enum vmxnet3_intr_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) VMXNET3_IT_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) VMXNET3_IT_INTX = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) VMXNET3_IT_MSI = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) VMXNET3_IT_MSIX = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define VMXNET3_MAX_TX_QUEUES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define VMXNET3_MAX_RX_QUEUES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* addition 1 for events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define VMXNET3_MAX_INTRS 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* value of intrCtrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct Vmxnet3_IntrConf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) bool autoMask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u8 numIntrs; /* # of interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 eventIntrIdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * each intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __le32 intrCtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __le32 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* one bit per VLAN ID, the size is in the units of u32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct Vmxnet3_QueueStatus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) bool stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 _pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) __le32 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct Vmxnet3_TxQueueCtrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) __le32 txNumDeferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) __le32 txThreshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) __le64 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct Vmxnet3_RxQueueCtrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) bool updateRxProd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u8 _pad[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) __le64 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) VMXNET3_RXM_UCAST = 0x01, /* unicast only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct Vmxnet3_RxFilterConf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __le32 rxMode; /* VMXNET3_RXM_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) __le16 mfTableLen; /* size of the multicast filter table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) __le16 _pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __le64 mfTablePA; /* PA of the multicast filters table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define VMXNET3_PM_MAX_FILTERS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define VMXNET3_PM_MAX_PATTERN_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct Vmxnet3_PM_PktFilter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 maskSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u8 patternSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u8 pad[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct Vmxnet3_PMConf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u8 numFilters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u8 pad[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct Vmxnet3_VariableLenConfDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __le32 confVer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) __le32 confLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __le64 confPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct Vmxnet3_TxQueueDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct Vmxnet3_TxQueueCtrl ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct Vmxnet3_TxQueueConf conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Driver read after a GET command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct Vmxnet3_QueueStatus status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct UPT1_TxStats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 _pad[88]; /* 128 aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct Vmxnet3_RxQueueDesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct Vmxnet3_RxQueueCtrl ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct Vmxnet3_RxQueueConf conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Driver read after a GET commad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct Vmxnet3_QueueStatus status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct UPT1_RxStats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u8 __pad[88]; /* 128 aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct Vmxnet3_SetPolling {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u8 enablePolling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define VMXNET3_COAL_STATIC_MAX_DEPTH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define VMXNET3_COAL_RBC_MIN_RATE 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define VMXNET3_COAL_RBC_MAX_RATE 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) enum Vmxnet3_CoalesceMode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) VMXNET3_COALESCE_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) VMXNET3_COALESCE_ADAPT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) VMXNET3_COALESCE_STATIC = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) VMXNET3_COALESCE_RBC = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct Vmxnet3_CoalesceRbc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 rbc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct Vmxnet3_CoalesceStatic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 tx_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 tx_comp_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 rx_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct Vmxnet3_CoalesceScheme {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) enum Vmxnet3_CoalesceMode coalMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct Vmxnet3_CoalesceRbc coalRbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct Vmxnet3_CoalesceStatic coalStatic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } coalPara;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct Vmxnet3_MemoryRegion {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) __le64 startPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) __le16 txQueueBits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) __le16 rxQueueBits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define MAX_MEMORY_REGION_PER_QUEUE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define MAX_MEMORY_REGION_PER_DEVICE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct Vmxnet3_MemRegs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) __le16 numRegs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __le16 pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct Vmxnet3_MemoryRegion memRegs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) enum Vmxnet3_RSSField {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* If the command data <= 16 bytes, use the shared memory directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * otherwise, use variable length configuration descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) union Vmxnet3_CmdInfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct Vmxnet3_VariableLenConfDesc varConf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct Vmxnet3_SetPolling setPolling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) enum Vmxnet3_RSSField setRssFields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __le64 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct Vmxnet3_DSDevRead {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* read-only region for device, read by dev in response to a SET cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct Vmxnet3_MiscConf misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct Vmxnet3_IntrConf intrConf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct Vmxnet3_RxFilterConf rxFilterConf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct Vmxnet3_VariableLenConfDesc rssConfDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct Vmxnet3_VariableLenConfDesc pmConfDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* All structures in DriverShared are padded to multiples of 8 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct Vmxnet3_DriverShared {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __le32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* make devRead start at 64bit boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) __le32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct Vmxnet3_DSDevRead devRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __le32 ecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) __le32 reserved1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) union Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * executing the relevant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } cu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define VMXNET3_ECR_RQERR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define VMXNET3_ECR_TQERR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define VMXNET3_ECR_LINK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define VMXNET3_ECR_DIC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define VMXNET3_ECR_DEBUG (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* flip the gen bit of a ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* only use this if moving the idx won't affect the gen bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) do {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) (idx)++;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (unlikely((idx) == (ring_size))) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (idx) = 0;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) (vfTable[vid >> 5] |= (1 << (vid & 31)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define VMXNET3_MAX_MTU 9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define VMXNET3_MIN_MTU 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define VMXNET3_LINK_DOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #endif /* _VMXNET3_DEFS_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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