^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* CoreChip-sz SR9800 one chip USB 2.0 Ethernet Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Author : Liu Junliang <liujunliang_ljl@163.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _SR9800_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _SR9800_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* SR9800 spec. command table on Linux Platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* command : Software Station Management Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SR_CMD_SET_SW_MII 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* command : PHY Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SR_CMD_READ_MII_REG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* command : PHY Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SR_CMD_WRITE_MII_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* command : Hardware Station Management Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SR_CMD_SET_HW_MII 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* command : SROM Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SR_CMD_READ_EEPROM 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* command : SROM Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SR_CMD_WRITE_EEPROM 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* command : SROM Write Enable Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SR_CMD_WRITE_ENABLE 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* command : SROM Write Disable Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SR_CMD_WRITE_DISABLE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* command : RX Control Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SR_CMD_READ_RX_CTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SR_RX_CTL_PRO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SR_RX_CTL_AMALL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SR_RX_CTL_SEP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SR_RX_CTL_AB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SR_RX_CTL_AM (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SR_RX_CTL_AP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SR_RX_CTL_ARP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SR_RX_CTL_SO (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SR_RX_CTL_RH1M (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SR_RX_CTL_RH2M (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SR_RX_CTL_RH3M (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* command : RX Control Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SR_CMD_WRITE_RX_CTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* command : IPG0/IPG1/IPG2 Control Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SR_CMD_READ_IPG012 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* command : IPG0/IPG1/IPG2 Control Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SR_CMD_WRITE_IPG012 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* command : Node ID Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SR_CMD_READ_NODE_ID 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* command : Node ID Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SR_CMD_WRITE_NODE_ID 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* command : Multicast Filter Array Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SR_CMD_READ_MULTI_FILTER 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* command : Multicast Filter Array Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SR_CMD_WRITE_MULTI_FILTER 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* command : Eth/HomePNA PHY Address Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SR_CMD_READ_PHY_ID 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* command : Medium Status Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SR_CMD_READ_MEDIUM_STATUS 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SR_MONITOR_LINK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SR_MONITOR_MAGIC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SR_MONITOR_HSFS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* command : Medium Status Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SR_CMD_WRITE_MEDIUM_MODE 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SR_MEDIUM_GM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SR_MEDIUM_FD (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SR_MEDIUM_AC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SR_MEDIUM_ENCK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SR_MEDIUM_RFC (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SR_MEDIUM_TFC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SR_MEDIUM_JFE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SR_MEDIUM_PF (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SR_MEDIUM_RE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SR_MEDIUM_PS (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SR_MEDIUM_RSV (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SR_MEDIUM_SBP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SR_MEDIUM_SM (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* command : Monitor Mode Status Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SR_CMD_READ_MONITOR_MODE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* command : Monitor Mode Status Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SR_CMD_WRITE_MONITOR_MODE 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* command : GPIO Status Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SR_CMD_READ_GPIOS 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SR_GPIO_GPO0EN (1 << 0) /* GPIO0 Output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SR_GPIO_GPO_0 (1 << 1) /* GPIO0 Output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SR_GPIO_GPO1EN (1 << 2) /* GPIO1 Output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SR_GPIO_GPO_1 (1 << 3) /* GPIO1 Output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SR_GPIO_GPO2EN (1 << 4) /* GPIO2 Output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SR_GPIO_GPO_2 (1 << 5) /* GPIO2 Output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SR_GPIO_RESERVED (1 << 6) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SR_GPIO_RSE (1 << 7) /* Reload serial EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* command : GPIO Status Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SR_CMD_WRITE_GPIOS 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* command : Eth PHY Power and Reset Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SR_CMD_SW_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SR_SWRESET_CLEAR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SR_SWRESET_RR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SR_SWRESET_RT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SR_SWRESET_PRTE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SR_SWRESET_PRL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SR_SWRESET_BZ (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SR_SWRESET_IPRL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SR_SWRESET_IPPD (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* command : Software Interface Selection Status Read Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SR_CMD_SW_PHY_STATUS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* command : Software Interface Selection Status Write Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SR_CMD_SW_PHY_SELECT 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* command : BULK in Buffer Size Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SR_CMD_BULKIN_SIZE 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* command : LED_MUX Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SR_CMD_LED_MUX 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SR_LED_MUX_TX_ACTIVE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SR_LED_MUX_RX_ACTIVE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SR_LED_MUX_COLLISION (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SR_LED_MUX_DUP_COL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SR_LED_MUX_DUP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SR_LED_MUX_SPEED (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SR_LED_MUX_LINK_ACTIVE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SR_LED_MUX_LINK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Register Access Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Multicast Filter Array size & Max Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SR_MCAST_FILTER_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SR_MAX_MCAST 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* IPG0/1/2 Default Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SR9800_IPG0_DEFAULT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SR9800_IPG1_DEFAULT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SR9800_IPG2_DEFAULT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Medium Status Default Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SR9800_MEDIUM_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (SR_MEDIUM_FD | SR_MEDIUM_RFC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SR_MEDIUM_TFC | SR_MEDIUM_PS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SR_MEDIUM_AC | SR_MEDIUM_RE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* RX Control Default Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SR_DEFAULT_RX_CTL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (SR_RX_CTL_SO | SR_RX_CTL_AB | SR_RX_CTL_RH1M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* EEPROM Magic Number & EEPROM Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SR_EEPROM_MAGIC 0xdeadbeef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SR9800_EEPROM_LEN 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* SR9800 Driver Version and Driver Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DRIVER_VERSION "11-Nov-2013"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRIVER_NAME "CoreChips"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DRIVER_FLAG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* SR9800 BULKIN Buffer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SR9800_MAX_BULKIN_2K 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SR9800_MAX_BULKIN_4K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SR9800_MAX_BULKIN_6K 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SR9800_MAX_BULKIN_8K 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SR9800_MAX_BULKIN_16K 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SR9800_MAX_BULKIN_20K 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SR9800_MAX_BULKIN_24K 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SR9800_MAX_BULKIN_32K 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct {unsigned short size, byte_cnt, threshold; } SR9800_BULKIN_SIZE[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* 2k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {2048, 0x8000, 0x8001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {4096, 0x8100, 0x8147},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* 6k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {6144, 0x8200, 0x81EB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {8192, 0x8300, 0x83D7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {16384, 0x8400, 0x851E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* 20k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {20480, 0x8500, 0x8666},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* 24k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {24576, 0x8600, 0x87AE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* 32k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {32768, 0x8700, 0x8A3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct sr_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 multi_filter[SR_MCAST_FILTER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 phymode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 ledmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 eeprom_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct sr9800_int_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __le16 res1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le16 res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __le16 res3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif /* _SR9800_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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