Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author : Liu Junliang <liujunliang_ljl@163.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _SR9700_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define	_SR9700_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* sr9700 spec. register table on Linux platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* Network Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define	SR_NCR			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define		NCR_RST			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define		NCR_LBK			(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define		NCR_FDX			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define		NCR_WAKEEN		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* Network Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define	SR_NSR			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define		NSR_RXRDY		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define		NSR_RXOV		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define		NSR_TX1END		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define		NSR_TX2END		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define		NSR_TXFULL		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define		NSR_WAKEST		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define		NSR_LINKST		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define		NSR_SPEED		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Tx Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	SR_TCR			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define		TCR_CRC_DIS		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define		TCR_PAD_DIS		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define		TCR_LC_CARE		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define		TCR_CRS_CARE	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define		TCR_EXCECM		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define		TCR_LF_EN		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* Tx Status Reg for Packet Index 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	SR_TSR1		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define		TSR1_EC			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define		TSR1_COL		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define		TSR1_LC			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define		TSR1_NC			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define		TSR1_LOC		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define		TSR1_TLF		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Tx Status Reg for Packet Index 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	SR_TSR2		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define		TSR2_EC			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define		TSR2_COL		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define		TSR2_LC			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define		TSR2_NC			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define		TSR2_LOC		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define		TSR2_TLF		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Rx Control Reg*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	SR_RCR			0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define		RCR_RXEN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define		RCR_PRMSC		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define		RCR_RUNT		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define		RCR_ALL			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define		RCR_DIS_CRC		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define		RCR_DIS_LONG	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Rx Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define	SR_RSR			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define		RSR_AE			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define		RSR_MF			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define		RSR_RF			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Rx Overflow Counter Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	SR_ROCR		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define		ROCR_ROC		(0x7F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define		ROCR_RXFU		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Back Pressure Threshold Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define	SR_BPTR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define		BPTR_JPT		(0x0F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define		BPTR_BPHW		(0x0F << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Flow Control Threshold Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define	SR_FCTR		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define		FCTR_LWOT		(0x0F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define		FCTR_HWOT		(0x0F << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* rx/tx Flow Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define	SR_FCR			0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define		FCR_FLCE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define		FCR_BKPA		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define		FCR_TXPEN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define		FCR_TXPF		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define		FCR_TXP0		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Eeprom & Phy Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define	SR_EPCR		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define		EPCR_ERRE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define		EPCR_ERPRW		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define		EPCR_ERPRR		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define		EPCR_EPOS		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define		EPCR_WEP		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* Eeprom & Phy Address Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	SR_EPAR		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define		EPAR_EROA		(0x3F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define		EPAR_PHY_ADR_MASK	(0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define		EPAR_PHY_ADR		(0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* Eeprom &	Phy Data Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	SR_EPDR		0x0D	/* 0x0D ~ 0x0E for Data Reg Low & High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* Wakeup Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	SR_WCR			0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define		WCR_MAGICST		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define		WCR_LINKST		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define		WCR_MAGICEN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define		WCR_LINKEN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Physical Address Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define	SR_PAR			0x10	/* 0x10 ~ 0x15 6 bytes for PAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Multicast Address Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define	SR_MAR			0x16	/* 0x16 ~ 0x1D 8 bytes for MAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* 0x1e unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Phy Reset Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define	SR_PRR			0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define		PRR_PHY_RST		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Tx sdram Write Pointer Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define	SR_TWPAL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Tx sdram Write Pointer Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define	SR_TWPAH		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Tx sdram Read Pointer Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	SR_TRPAL		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Tx sdram Read Pointer Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define	SR_TRPAH		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Rx sdram Write Pointer Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define	SR_RWPAL		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Rx sdram Write Pointer Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define	SR_RWPAH		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Rx sdram Read Pointer Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define	SR_RRPAL		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Rx sdram Read Pointer Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define	SR_RRPAH		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Vendor ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define	SR_VID			0x28	/* 0x28 ~ 0x29 2 bytes for VID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Product ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define	SR_PID			0x2A	/* 0x2A ~ 0x2B 2 bytes for PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* CHIP Revision register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define	SR_CHIPR		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 0x2D --> 0xEF unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* USB Device Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define	SR_USBDA		0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define		USBDA_USBFA		(0x7F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* RX packet Counter Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define	SR_RXC			0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Tx packet Counter & USB Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define	SR_TXC_USBS		0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define		TXC_USBS_TXC0		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define		TXC_USBS_TXC1		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define		TXC_USBS_TXC2		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define		TXC_USBS_EP1RDY		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define		TXC_USBS_SUSFLAG	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define		TXC_USBS_RXFAULT	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* USB Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define	SR_USBC			0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define		USBC_EP3NAK		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define		USBC_EP3ACK		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Register access commands and flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define	SR_RD_REGS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define	SR_WR_REGS		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define	SR_WR_REG		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define	SR_REQ_RD_REG	(USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define	SR_REQ_WR_REG	(USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define	SR_SHARE_TIMEOUT	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define	SR_EEPROM_LEN		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define	SR_MCAST_SIZE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define	SR_MCAST_ADDR_FLAG	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define	SR_MCAST_MAX		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define	SR_TX_OVERHEAD		2	/* 2bytes header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define	SR_RX_OVERHEAD		7	/* 3bytes header + 4crc tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif	/* _SR9700_H */