Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007-2008 SMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _SMSC95XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _SMSC95XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* Tx command words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define TX_CMD_A_DATA_OFFSET_	(0x001F0000)	/* Data Start Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define TX_CMD_A_FIRST_SEG_	(0x00002000)	/* First Segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TX_CMD_A_LAST_SEG_	(0x00001000)	/* Last Segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TX_CMD_A_BUF_SIZE_	(0x000007FF)	/* Buffer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TX_CMD_B_CSUM_ENABLE	(0x00004000)	/* TX Checksum Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TX_CMD_B_ADD_CRC_DIS_	(0x00002000)	/* Add CRC Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TX_CMD_B_DIS_PADDING_	(0x00001000)	/* Disable Frame Padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TX_CMD_B_FRAME_LENGTH_	(0x000007FF)	/* Frame Length (bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Rx status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RX_STS_FF_		(0x40000000)	/* Filter Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RX_STS_FL_		(0x3FFF0000)	/* Frame Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RX_STS_ES_		(0x00008000)	/* Error Summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RX_STS_BF_		(0x00002000)	/* Broadcast Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RX_STS_LE_		(0x00001000)	/* Length Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RX_STS_RF_		(0x00000800)	/* Runt Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RX_STS_MF_		(0x00000400)	/* Multicast Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RX_STS_TL_		(0x00000080)	/* Frame too long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RX_STS_CS_		(0x00000040)	/* Collision Seen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RX_STS_FT_		(0x00000020)	/* Frame Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RX_STS_RW_		(0x00000010)	/* Receive Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RX_STS_ME_		(0x00000008)	/* MII Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RX_STS_DB_		(0x00000004)	/* Dribbling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RX_STS_CRC_		(0x00000002)	/* CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* SCSRs - System Control and Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* Device ID and Revision Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ID_REV			(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ID_REV_CHIP_ID_MASK_	(0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ID_REV_CHIP_REV_MASK_	(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ID_REV_CHIP_ID_9500_	(0x9500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ID_REV_CHIP_ID_9500A_	(0x9E00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ID_REV_CHIP_ID_9512_	(0xEC00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ID_REV_CHIP_ID_9530_	(0x9530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ID_REV_CHIP_ID_89530_	(0x9E08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ID_REV_CHIP_ID_9730_	(0x9730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define INT_STS			(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define INT_STS_MAC_RTO_	(0x00040000)	/* MAC Reset Time Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define INT_STS_TX_STOP_	(0x00020000)	/* TX Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define INT_STS_RX_STOP_	(0x00010000)	/* RX Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define INT_STS_PHY_INT_	(0x00008000)	/* PHY Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define INT_STS_TXE_		(0x00004000)	/* Transmitter Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define INT_STS_TDFU_		(0x00002000)	/* TX Data FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define INT_STS_TDFO_		(0x00001000)	/* TX Data FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define INT_STS_RXDF_		(0x00000800)	/* RX Dropped Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define INT_STS_GPIOS_		(0x000007FF)	/* GPIOs Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define INT_STS_CLEAR_ALL_	(0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* Receive Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define RX_CFG			(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RX_FIFO_FLUSH_		(0x00000001)	/* Receive FIFO Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Transmit Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TX_CFG			(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TX_CFG_ON_		(0x00000004)	/* Transmitter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TX_CFG_STOP_		(0x00000002)	/* Stop Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TX_CFG_FIFO_FLUSH_	(0x00000001)	/* Transmit FIFO Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Hardware Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define HW_CFG			(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HW_CFG_BIR_		(0x00001000)	/* Bulk In Empty Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HW_CFG_LEDB_		(0x00000800)	/* Activity LED 80ms Bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HW_CFG_RXDOFF_		(0x00000600)	/* RX Data Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HW_CFG_SBP_		(0x00000100)	/* Stall Bulk Out Pipe Dis. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define HW_CFG_IME_		(0x00000080)	/* Internal MII Visi. Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define HW_CFG_DRP_		(0x00000040)	/* Discard Errored RX Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define HW_CFG_MEF_		(0x00000020)	/* Mult. ETH Frames/USB pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define HW_CFG_ETC_		(0x00000010)	/* EEPROM Timeout Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HW_CFG_LRST_		(0x00000008)	/* Soft Lite Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define HW_CFG_PSEL_		(0x00000004)	/* External PHY Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define HW_CFG_BCE_		(0x00000002)	/* Burst Cap Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HW_CFG_SRST_		(0x00000001)	/* Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* Receive FIFO Information Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define RX_FIFO_INF		(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define RX_FIFO_INF_USED_	(0x0000FFFF)	/* RX Data FIFO Used Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* Transmit FIFO Information Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TX_FIFO_INF		(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TX_FIFO_INF_FREE_	(0x0000FFFF)	/* TX Data FIFO Free Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* Power Management Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PM_CTRL			(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PM_CTL_RES_CLR_WKP_STS	(0x00000200)	/* Resume Clears Wakeup STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PM_CTL_RES_CLR_WKP_EN	(0x00000100)	/* Resume Clears Wkp Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PM_CTL_DEV_RDY_		(0x00000080)	/* Device Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PM_CTL_SUS_MODE_	(0x00000060)	/* Suspend Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PM_CTL_SUS_MODE_0	(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PM_CTL_SUS_MODE_1	(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PM_CTL_SUS_MODE_2	(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PM_CTL_SUS_MODE_3	(0x00000060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PM_CTL_PHY_RST_		(0x00000010)	/* PHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PM_CTL_WOL_EN_		(0x00000008)	/* Wake On Lan Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PM_CTL_ED_EN_		(0x00000004)	/* Energy Detect Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PM_CTL_WUPS_		(0x00000003)	/* Wake Up Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PM_CTL_WUPS_NO_		(0x00000000)	/* No Wake Up Event Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PM_CTL_WUPS_ED_		(0x00000001)	/* Energy Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PM_CTL_WUPS_WOL_	(0x00000002)	/* Wake On Lan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PM_CTL_WUPS_MULTI_	(0x00000003)	/* Multiple Events Occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* LED General Purpose IO Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LED_GPIO_CFG		(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LED_GPIO_CFG_SPD_LED	(0x01000000)	/* GPIOz as Speed LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LED_GPIO_CFG_LNK_LED	(0x00100000)	/* GPIOy as Link LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LED_GPIO_CFG_FDX_LED	(0x00010000)	/* GPIOx as Full Duplex LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* General Purpose IO Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GPIO_CFG		(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Automatic Flow Control Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AFC_CFG			(0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AFC_CFG_HI_		(0x00FF0000)	/* Auto Flow Ctrl High Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AFC_CFG_LO_		(0x0000FF00)	/* Auto Flow Ctrl Low Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AFC_CFG_BACK_DUR_	(0x000000F0)	/* Back Pressure Duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AFC_CFG_FC_MULT_	(0x00000008)	/* Flow Ctrl on Mcast Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AFC_CFG_FC_BRD_		(0x00000004)	/* Flow Ctrl on Bcast Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AFC_CFG_FC_ADD_		(0x00000002)	/* Flow Ctrl on Addr. Decode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AFC_CFG_FC_ANY_		(0x00000001)	/* Flow Ctrl on Any Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Hi watermark = 15.5Kb (~10 mtu pkts) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* low watermark = 3k (~2 mtu pkts) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* backpressure duration = ~ 350us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Apply FC on any frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AFC_CFG_DEFAULT		(0x00F830A1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* EEPROM Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define E2P_CMD			(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define E2P_CMD_BUSY_		(0x80000000)	/* E2P Controller Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define E2P_CMD_MASK_		(0x70000000)	/* Command Mask (see below) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define E2P_CMD_READ_		(0x00000000)	/* Read Location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define E2P_CMD_EWDS_		(0x10000000)	/* Erase/Write Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define E2P_CMD_EWEN_		(0x20000000)	/* Erase/Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define E2P_CMD_WRITE_		(0x30000000)	/* Write Location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define E2P_CMD_WRAL_		(0x40000000)	/* Write All */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define E2P_CMD_ERASE_		(0x50000000)	/* Erase Location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define E2P_CMD_ERAL_		(0x60000000)	/* Erase All */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define E2P_CMD_RELOAD_		(0x70000000)	/* Data Reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define E2P_CMD_TIMEOUT_	(0x00000400)	/* Set if no resp within 30ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define E2P_CMD_LOADED_		(0x00000200)	/* Valid EEPROM found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define E2P_CMD_ADDR_		(0x000001FF)	/* Byte aligned address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MAX_EEPROM_SIZE		(512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* EEPROM Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define E2P_DATA		(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define E2P_DATA_MASK_		(0x000000FF)	/* EEPROM Data Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Burst Cap Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BURST_CAP		(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BURST_CAP_MASK_		(0x000000FF)	/* Max burst sent by the UTX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Configuration Straps Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define	STRAP_STATUS			(0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define	STRAP_STATUS_PWR_SEL_		(0x00000020) /* Device self-powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define	STRAP_STATUS_AMDIX_EN_		(0x00000010) /* Auto-MDIX Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define	STRAP_STATUS_PORT_SWAP_		(0x00000008) /* USBD+/USBD- Swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define	STRAP_STATUS_EEP_SIZE_		(0x00000004) /* EEPROM Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define	STRAP_STATUS_RMT_WKP_		(0x00000002) /* Remote Wkp supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define	STRAP_STATUS_EEP_DISABLE_	(0x00000001) /* EEPROM Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Data Port Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DP_SEL			(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Data Port Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DP_CMD			(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Data Port Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DP_ADDR			(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Data Port Data 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DP_DATA0		(0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Data Port Data 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DP_DATA1		(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* General Purpose IO Wake Enable and Polarity Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GPIO_WAKE		(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Interrupt Endpoint Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define INT_EP_CTL		(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define INT_EP_CTL_INTEP_	(0x80000000)	/* Always TX Interrupt PKT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define INT_EP_CTL_MAC_RTO_	(0x00080000)	/* MAC Reset Time Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define INT_EP_CTL_RX_FIFO_	(0x00040000)	/* RX FIFO Has Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define INT_EP_CTL_TX_STOP_	(0x00020000)	/* TX Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define INT_EP_CTL_RX_STOP_	(0x00010000)	/* RX Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define INT_EP_CTL_PHY_INT_	(0x00008000)	/* PHY Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define INT_EP_CTL_TXE_		(0x00004000)	/* TX Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define INT_EP_CTL_TDFU_	(0x00002000)	/* TX Data FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define INT_EP_CTL_TDFO_	(0x00001000)	/* TX Data FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define INT_EP_CTL_RXDF_	(0x00000800)	/* RX Dropped Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define INT_EP_CTL_GPIOS_	(0x000007FF)	/* GPIOs Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Bulk In Delay Register (units of 16.667ns, until ~1092µs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BULK_IN_DLY		(0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* MAC CSRs - MAC Control and Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* MAC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MAC_CR			(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MAC_CR_RXALL_		(0x80000000)	/* Receive All Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MAC_CR_RCVOWN_		(0x00800000)	/* Disable Receive Own */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MAC_CR_LOOPBK_		(0x00200000)	/* Loopback Operation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MAC_CR_FDPX_		(0x00100000)	/* Full Duplex Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MAC_CR_MCPAS_		(0x00080000)	/* Pass All Multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MAC_CR_PRMS_		(0x00040000)	/* Promiscuous Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MAC_CR_INVFILT_		(0x00020000)	/* Inverse Filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MAC_CR_PASSBAD_		(0x00010000)	/* Pass Bad Frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MAC_CR_HFILT_		(0x00008000)	/* Hash Only Filtering Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MAC_CR_HPFILT_		(0x00002000)	/* Hash/Perfect Filt. Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MAC_CR_LCOLL_		(0x00001000)	/* Late Collision Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MAC_CR_BCAST_		(0x00000800)	/* Disable Broadcast Frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MAC_CR_DISRTY_		(0x00000400)	/* Disable Retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MAC_CR_PADSTR_		(0x00000100)	/* Automatic Pad Stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MAC_CR_BOLMT_MASK	(0x000000C0)	/* BackOff Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MAC_CR_DFCHK_		(0x00000020)	/* Deferral Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MAC_CR_TXEN_		(0x00000008)	/* Transmitter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MAC_CR_RXEN_		(0x00000004)	/* Receiver Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* MAC Address High Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ADDRH			(0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* MAC Address Low Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ADDRL			(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Multicast Hash Table High Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HASHH			(0x10C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Multicast Hash Table Low Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HASHL			(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* MII Access Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MII_ADDR		(0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MII_WRITE_		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MII_BUSY_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MII_READ_		(0x00) /* ~of MII Write bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* MII Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MII_DATA		(0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Flow Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define FLOW			(0x11C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define FLOW_FCPT_		(0xFFFF0000)	/* Pause Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define FLOW_FCPASS_		(0x00000004)	/* Pass Control Frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define FLOW_FCEN_		(0x00000002)	/* Flow Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define FLOW_FCBSY_		(0x00000001)	/* Flow Control Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* VLAN1 Tag Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define VLAN1			(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* VLAN2 Tag Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define VLAN2			(0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Wake Up Frame Filter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define WUFF			(0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define LAN9500_WUFF_NUM	(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define LAN9500A_WUFF_NUM	(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Wake Up Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define WUCSR			(0x12C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define WUCSR_WFF_PTR_RST_	(0x80000000)	/* WFrame Filter Pointer Rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define WUCSR_GUE_		(0x00000200)	/* Global Unicast Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define WUCSR_WUFR_		(0x00000040)	/* Wakeup Frame Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define WUCSR_MPR_		(0x00000020)	/* Magic Packet Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define WUCSR_WAKE_EN_		(0x00000004)	/* Wakeup Frame Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define WUCSR_MPEN_		(0x00000002)	/* Magic Packet Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Checksum Offload Engine Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define COE_CR			(0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define Tx_COE_EN_		(0x00010000)	/* TX Csum Offload Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define Rx_COE_MODE_		(0x00000002)	/* RX Csum Offload Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define Rx_COE_EN_		(0x00000001)	/* RX Csum Offload Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Vendor-specific PHY Definitions (via MII access) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* EDPD NLP / crossover time configuration (LAN9500A only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PHY_EDPD_CONFIG			(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PHY_EDPD_CONFIG_TX_NLP_EN_	((u16)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PHY_EDPD_CONFIG_TX_NLP_1000_	((u16)0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PHY_EDPD_CONFIG_TX_NLP_768_	((u16)0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define PHY_EDPD_CONFIG_TX_NLP_512_	((u16)0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PHY_EDPD_CONFIG_TX_NLP_256_	((u16)0x6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PHY_EDPD_CONFIG_RX_1_NLP_	((u16)0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define PHY_EDPD_CONFIG_RX_NLP_64_	((u16)0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PHY_EDPD_CONFIG_RX_NLP_256_	((u16)0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PHY_EDPD_CONFIG_RX_NLP_512_	((u16)0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PHY_EDPD_CONFIG_RX_NLP_1000_	((u16)0x0C00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PHY_EDPD_CONFIG_EXT_CROSSOVER_	((u16)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PHY_EDPD_CONFIG_DEFAULT		(PHY_EDPD_CONFIG_TX_NLP_EN_ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 					 PHY_EDPD_CONFIG_TX_NLP_768_ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 					 PHY_EDPD_CONFIG_RX_1_NLP_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Mode Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define PHY_MODE_CTRL_STS		(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MODE_CTRL_STS_EDPWRDOWN_	((u16)0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MODE_CTRL_STS_ENERGYON_		((u16)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Control/Status Indication Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SPECIAL_CTRL_STS		(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SPECIAL_CTRL_STS_OVRRD_AMDIX_	((u16)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SPECIAL_CTRL_STS_AMDIX_ENABLE_	((u16)0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SPECIAL_CTRL_STS_AMDIX_STATE_	((u16)0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Interrupt Source Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PHY_INT_SRC			(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PHY_INT_SRC_ENERGY_ON_		((u16)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define PHY_INT_SRC_ANEG_COMP_		((u16)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PHY_INT_SRC_REMOTE_FAULT_	((u16)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PHY_INT_SRC_LINK_DOWN_		((u16)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define PHY_INT_MASK			(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define PHY_INT_MASK_ENERGY_ON_		((u16)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PHY_INT_MASK_ANEG_COMP_		((u16)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PHY_INT_MASK_REMOTE_FAULT_	((u16)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define PHY_INT_MASK_LINK_DOWN_		((u16)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PHY_INT_MASK_DEFAULT_		(PHY_INT_MASK_ANEG_COMP_ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 					 PHY_INT_MASK_LINK_DOWN_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* PHY Special Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PHY_SPECIAL			(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PHY_SPECIAL_SPD_		((u16)0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PHY_SPECIAL_SPD_10HALF_		((u16)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PHY_SPECIAL_SPD_10FULL_		((u16)0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PHY_SPECIAL_SPD_100HALF_	((u16)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define PHY_SPECIAL_SPD_100FULL_	((u16)0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* USB Vendor Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define USB_VENDOR_REQUEST_WRITE_REGISTER	0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define USB_VENDOR_REQUEST_READ_REGISTER	0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define USB_VENDOR_REQUEST_GET_STATS		0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Interrupt Endpoint status word bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define INT_ENP_MAC_RTO_		((u32)BIT(18))	/* MAC Reset Time Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define INT_ENP_TX_STOP_		((u32)BIT(17))	/* TX Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define INT_ENP_RX_STOP_		((u32)BIT(16))	/* RX Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define INT_ENP_PHY_INT_		((u32)BIT(15))	/* PHY Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define INT_ENP_TXE_			((u32)BIT(14))	/* TX Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define INT_ENP_TDFU_			((u32)BIT(13))	/* TX FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define INT_ENP_TDFO_			((u32)BIT(12))	/* TX FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define INT_ENP_RXDF_			((u32)BIT(11))	/* RX Dropped Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #endif /* _SMSC95XX_H */