Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007-2010 SMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _SMSC75XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _SMSC75XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* Tx command words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define TX_CMD_A_LSO			(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define TX_CMD_A_IPE			(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TX_CMD_A_TPE			(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TX_CMD_A_IVTG			(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TX_CMD_A_RVTG			(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TX_CMD_A_FCS			(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TX_CMD_A_LEN			(0x000FFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TX_CMD_B_MSS			(0x3FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TX_CMD_B_MSS_SHIFT		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TX_MSS_MIN			((u16)8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TX_CMD_B_VTAG			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* Rx command words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RX_CMD_A_ICE			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RX_CMD_A_TCE			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RX_CMD_A_IPV			(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RX_CMD_A_PID			(0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RX_CMD_A_PID_NIP		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RX_CMD_A_PID_TCP		(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RX_CMD_A_PID_UDP		(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RX_CMD_A_PID_PP			(0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RX_CMD_A_PFF			(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RX_CMD_A_BAM			(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RX_CMD_A_MAM			(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RX_CMD_A_FVTG			(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RX_CMD_A_RED			(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RX_CMD_A_RWT			(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RX_CMD_A_RUNT			(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RX_CMD_A_LONG			(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RX_CMD_A_RXE			(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RX_CMD_A_DRB			(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RX_CMD_A_FCS			(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RX_CMD_A_UAM			(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RX_CMD_A_LCSM			(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RX_CMD_A_LEN			(0x00003FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RX_CMD_B_CSUM			(0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RX_CMD_B_CSUM_SHIFT		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RX_CMD_B_VTAG			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* SCSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ID_REV				(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define FPGA_REV			(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BOND_CTL			(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define INT_STS				(0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define INT_STS_RDFO_INT		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define INT_STS_TXE_INT			(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define INT_STS_MACRTO_INT		(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define INT_STS_TX_DIS_INT		(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define INT_STS_RX_DIS_INT		(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define INT_STS_PHY_INT_		(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define INT_STS_MAC_ERR_INT		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define INT_STS_TDFU			(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define INT_STS_TDFO			(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define INT_STS_GPIOS			(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define INT_STS_CLEAR_ALL		(0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define HW_CFG				(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define HW_CFG_SMDET_STS		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HW_CFG_SMDET_EN			(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HW_CFG_EEM			(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HW_CFG_RST_PROTECT		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HW_CFG_PORT_SWAP		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define HW_CFG_PHY_BOOST		(0x00000600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define HW_CFG_PHY_BOOST_NORMAL		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define HW_CFG_PHY_BOOST_4		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define HW_CFG_PHY_BOOST_8		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HW_CFG_PHY_BOOST_12		(0x00006000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define HW_CFG_LEDB			(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define HW_CFG_BIR			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HW_CFG_SBP			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define HW_CFG_IME			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define HW_CFG_MEF			(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define HW_CFG_ETC			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define HW_CFG_BCE			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define HW_CFG_LRST			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define HW_CFG_SRST			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define PMT_CTL				(0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PMT_CTL_PHY_PWRUP		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PMT_CTL_RES_CLR_WKP_EN		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PMT_CTL_DEV_RDY			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PMT_CTL_SUS_MODE		(0x00000060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PMT_CTL_SUS_MODE_0		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PMT_CTL_SUS_MODE_1		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PMT_CTL_SUS_MODE_2		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PMT_CTL_SUS_MODE_3		(0x00000060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PMT_CTL_PHY_RST			(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PMT_CTL_WOL_EN			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PMT_CTL_ED_EN			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PMT_CTL_WUPS			(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PMT_CTL_WUPS_NO			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PMT_CTL_WUPS_ED			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMT_CTL_WUPS_WOL		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMT_CTL_WUPS_MULTI		(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LED_GPIO_CFG			(0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LED_GPIO_CFG_LED2_FUN_SEL	(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LED_GPIO_CFG_LED10_FUN_SEL	(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LED_GPIO_CFG_LEDGPIO_EN		(0x0000F000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LED_GPIO_CFG_LEDGPIO_EN_0	(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LED_GPIO_CFG_LEDGPIO_EN_1	(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LED_GPIO_CFG_LEDGPIO_EN_2	(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LED_GPIO_CFG_LEDGPIO_EN_3	(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LED_GPIO_CFG_GPBUF		(0x00000F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LED_GPIO_CFG_GPBUF_0		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LED_GPIO_CFG_GPBUF_1		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LED_GPIO_CFG_GPBUF_2		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LED_GPIO_CFG_GPBUF_3		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LED_GPIO_CFG_GPDIR		(0x000000F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LED_GPIO_CFG_GPDIR_0		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LED_GPIO_CFG_GPDIR_1		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LED_GPIO_CFG_GPDIR_2		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LED_GPIO_CFG_GPDIR_3		(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LED_GPIO_CFG_GPDATA		(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LED_GPIO_CFG_GPDATA_0		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LED_GPIO_CFG_GPDATA_1		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LED_GPIO_CFG_GPDATA_2		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LED_GPIO_CFG_GPDATA_3		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GPIO_CFG			(0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPIO_CFG_SHIFT			(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GPIO_CFG_GPEN			(0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GPIO_CFG_GPBUF			(0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GPIO_CFG_GPDIR			(0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GPIO_CFG_GPDATA			(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GPIO_WAKE			(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GPIO_WAKE_PHY_LINKUP_EN		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GPIO_WAKE_POL			(0x0FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GPIO_WAKE_POL_SHIFT		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPIO_WAKE_WK			(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DP_SEL				(0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DP_SEL_DPRDY			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DP_SEL_RSEL			(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DP_SEL_URX			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DP_SEL_VHF			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DP_SEL_VHF_HASH_LEN		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DP_SEL_VHF_VLAN_LEN		(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DP_SEL_LSO_HEAD			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DP_SEL_FCT_RX			(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DP_SEL_FCT_TX			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DP_SEL_DESCRIPTOR		(0x00000005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DP_SEL_WOL			(0x00000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DP_CMD				(0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DP_CMD_WRITE			(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DP_CMD_READ			(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DP_ADDR				(0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DP_DATA				(0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BURST_CAP			(0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BURST_CAP_MASK			(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define INT_EP_CTL			(0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define INT_EP_CTL_INTEP_ON		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define INT_EP_CTL_RDFO_EN		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define INT_EP_CTL_TXE_EN		(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define INT_EP_CTL_MACROTO_EN		(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define INT_EP_CTL_TX_DIS_EN		(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define INT_EP_CTL_RX_DIS_EN		(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define INT_EP_CTL_PHY_EN_		(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define INT_EP_CTL_MAC_ERR_EN		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define INT_EP_CTL_TDFU_EN		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define INT_EP_CTL_TDFO_EN		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define INT_EP_CTL_RX_FIFO_EN		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define INT_EP_CTL_GPIOX_EN		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BULK_IN_DLY			(0x003C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BULK_IN_DLY_MASK		(0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define E2P_CMD				(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define E2P_CMD_BUSY			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define E2P_CMD_MASK			(0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define E2P_CMD_READ			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define E2P_CMD_EWDS			(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define E2P_CMD_EWEN			(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define E2P_CMD_WRITE			(0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define E2P_CMD_WRAL			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define E2P_CMD_ERASE			(0x50000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define E2P_CMD_ERAL			(0x60000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define E2P_CMD_RELOAD			(0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define E2P_CMD_TIMEOUT			(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define E2P_CMD_LOADED			(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define E2P_CMD_ADDR			(0x000001FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MAX_EEPROM_SIZE			(512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define E2P_DATA			(0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define E2P_DATA_MASK_			(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RFE_CTL				(0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RFE_CTL_TCPUDP_CKM		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RFE_CTL_IP_CKM			(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RFE_CTL_AB			(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RFE_CTL_AM			(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RFE_CTL_AU			(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RFE_CTL_VS			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RFE_CTL_UF			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define RFE_CTL_VF			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define RFE_CTL_SPF			(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define RFE_CTL_MHF			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RFE_CTL_DHF			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define RFE_CTL_DPF			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define RFE_CTL_RST_RF			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define VLAN_TYPE			(0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define VLAN_TYPE_MASK			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FCT_RX_CTL			(0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define FCT_RX_CTL_EN			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define FCT_RX_CTL_RST			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define FCT_RX_CTL_SBF			(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define FCT_RX_CTL_OVERFLOW		(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define FCT_RX_CTL_FRM_DROP		(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define FCT_RX_CTL_RX_NOT_EMPTY		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define FCT_RX_CTL_RX_EMPTY		(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define FCT_RX_CTL_RX_DISABLED		(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define FCT_RX_CTL_RXUSED		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define FCT_TX_CTL			(0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define FCT_TX_CTL_EN			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define FCT_TX_CTL_RST			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define FCT_TX_CTL_TX_NOT_EMPTY		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define FCT_TX_CTL_TX_EMPTY		(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FCT_TX_CTL_TX_DISABLED		(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define FCT_TX_CTL_TXUSED		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define FCT_RX_FIFO_END			(0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define FCT_RX_FIFO_END_MASK		(0x0000007F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define FCT_TX_FIFO_END			(0x009C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define FCT_TX_FIFO_END_MASK		(0x0000003F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define FCT_FLOW			(0x00A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define FCT_FLOW_THRESHOLD_OFF		(0x00007F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define FCT_FLOW_THRESHOLD_OFF_SHIFT	(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define FCT_FLOW_THRESHOLD_ON		(0x0000007F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* MAC CSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MAC_CR				(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MAC_CR_ADP			(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MAC_CR_ADD			(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MAC_CR_ASD			(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MAC_CR_INT_LOOP			(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MAC_CR_BOLMT			(0x000000C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MAC_CR_FDPX			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MAC_CR_CFG			(0x00000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MAC_CR_CFG_10			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MAC_CR_CFG_100			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MAC_CR_CFG_1000			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MAC_CR_RST			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MAC_RX				(0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MAC_RX_MAX_SIZE			(0x3FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MAC_RX_MAX_SIZE_SHIFT		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MAC_RX_FCS_STRIP		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MAC_RX_FSE			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MAC_RX_RXD			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MAC_RX_RXEN			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MAC_TX				(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MAC_TX_BFCS			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MAC_TX_TXD			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MAC_TX_TXEN			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define FLOW				(0x10C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define FLOW_FORCE_FC			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define FLOW_TX_FCEN			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define FLOW_RX_FCEN			(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define FLOW_FPF			(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FLOW_PAUSE_TIME			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define RAND_SEED			(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define RAND_SEED_MASK			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ERR_STS				(0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ERR_STS_FCS_ERR			(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ERR_STS_LFRM_ERR		(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ERR_STS_RUNT_ERR		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ERR_STS_COLLISION_ERR		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ERR_STS_ALIGN_ERR		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ERR_STS_URUN_ERR		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define RX_ADDRH			(0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define RX_ADDRH_MASK			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define RX_ADDRL			(0x11C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MII_ACCESS			(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MII_ACCESS_PHY_ADDR		(0x0000F800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MII_ACCESS_PHY_ADDR_SHIFT	(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MII_ACCESS_REG_ADDR		(0x000007C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MII_ACCESS_REG_ADDR_SHIFT	(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MII_ACCESS_READ			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MII_ACCESS_WRITE		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MII_ACCESS_BUSY			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MII_DATA			(0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MII_DATA_MASK			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define WUCSR				(0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define WUCSR_PFDA_FR			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define WUCSR_WUFR			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define WUCSR_MPR			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define WUCSR_BCAST_FR			(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define WUCSR_PFDA_EN			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define WUCSR_WUEN			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define WUCSR_MPEN			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define WUCSR_BCST_EN			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define WUF_CFGX			(0x144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define WUF_CFGX_EN			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define WUF_CFGX_ATYPE			(0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define WUF_CFGX_ATYPE_UNICAST		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define WUF_CFGX_ATYPE_MULTICAST	(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define WUF_CFGX_ATYPE_ALL		(0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define WUF_CFGX_PATTERN_OFFSET		(0x007F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define WUF_CFGX_PATTERN_OFFSET_SHIFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define WUF_CFGX_CRC16			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define WUF_NUM				(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define WUF_MASKX			(0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define WUF_MASKX_AVALID		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define WUF_MASKX_ATYPE			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ADDR_FILTX			(0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ADDR_FILTX_FB_VALID		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ADDR_FILTX_FB_TYPE		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ADDR_FILTX_FB_ADDRHI		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ADDR_FILTX_SB_ADDRLO		(0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define WUCSR2				(0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define WUCSR2_NS_RCD			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define WUCSR2_ARP_RCD			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define WUCSR2_TCPSYN_RCD		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define WUCSR2_NS_OFFLOAD		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define WUCSR2_ARP_OFFLOAD		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define WUCSR2_TCPSYN_OFFLOAD		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define WOL_FIFO_STS			(0x504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IPV6_ADDRX			(0x510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IPV4_ADDRX			(0x590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Vendor-specific PHY Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Mode Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PHY_MODE_CTRL_STS		(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MODE_CTRL_STS_EDPWRDOWN		((u16)0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define MODE_CTRL_STS_ENERGYON		((u16)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PHY_INT_SRC			(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PHY_INT_SRC_ENERGY_ON		((u16)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PHY_INT_SRC_ANEG_COMP		((u16)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PHY_INT_SRC_REMOTE_FAULT	((u16)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PHY_INT_SRC_LINK_DOWN		((u16)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PHY_INT_SRC_CLEAR_ALL		((u16)0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PHY_INT_MASK			(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PHY_INT_MASK_ENERGY_ON		((u16)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PHY_INT_MASK_ANEG_COMP		((u16)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PHY_INT_MASK_REMOTE_FAULT	((u16)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PHY_INT_MASK_LINK_DOWN		((u16)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PHY_INT_MASK_DEFAULT		(PHY_INT_MASK_ANEG_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 					 PHY_INT_MASK_LINK_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PHY_SPECIAL			(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PHY_SPECIAL_SPD			((u16)0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define PHY_SPECIAL_SPD_10HALF		((u16)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define PHY_SPECIAL_SPD_10FULL		((u16)0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PHY_SPECIAL_SPD_100HALF		((u16)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PHY_SPECIAL_SPD_100FULL		((u16)0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* USB Vendor Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define USB_VENDOR_REQUEST_WRITE_REGISTER	0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define USB_VENDOR_REQUEST_READ_REGISTER	0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define USB_VENDOR_REQUEST_GET_STATS		0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Interrupt Endpoint status word bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define INT_ENP_RDFO_INT		((u32)BIT(22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define INT_ENP_TXE_INT			((u32)BIT(21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define INT_ENP_TX_DIS_INT		((u32)BIT(19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define INT_ENP_RX_DIS_INT		((u32)BIT(18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define INT_ENP_PHY_INT			((u32)BIT(17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define INT_ENP_MAC_ERR_INT		((u32)BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define INT_ENP_RX_FIFO_DATA_INT	((u32)BIT(12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif /* _SMSC75XX_H */