^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2010 SMSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kmod.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitrev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/crc16.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/usb/usbnet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "smsc75xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SMSC_CHIPNAME "smsc75xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SMSC_DRIVER_VERSION "1.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HS_USB_PKT_SIZE (512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FS_USB_PKT_SIZE (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DEFAULT_BULK_IN_DELAY (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX_SINGLE_PACKET_SIZE (9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LAN75XX_EEPROM_MAGIC (0x7500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EEPROM_MAC_OFFSET (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DEFAULT_TX_CSUM_ENABLE (true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DEFAULT_RX_CSUM_ENABLE (true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SMSC75XX_INTERNAL_PHY_ID (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SMSC75XX_TX_OVERHEAD (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX_RX_FIFO_SIZE (20 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX_TX_FIFO_SIZE (12 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USB_VENDOR_ID_SMSC (0x0424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USB_PRODUCT_ID_LAN7500 (0x7500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USB_PRODUCT_ID_LAN7505 (0x7505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RXW_PADDING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUSPEND_SUSPEND0 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUSPEND_SUSPEND1 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUSPEND_SUSPEND2 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUSPEND_SUSPEND3 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct smsc75xx_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct usbnet *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 rfe_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mutex dataport_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spinlock_t rfe_ctl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct work_struct set_multicast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 suspend_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct usb_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct usb_ctrlrequest req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct usbnet *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static bool turbo_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) module_param(turbo_mode, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int smsc75xx_link_ok_nopm(struct usbnet *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int smsc75xx_phy_gig_workaround(struct usbnet *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 *data, int in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) fn = usbnet_read_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) fn = usbnet_read_cmd_nopm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0, index, &buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (unlikely(ret < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) le32_to_cpus(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 data, int in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) fn = usbnet_write_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) fn = usbnet_write_cmd_nopm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) buf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cpu_to_le32s(&buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0, index, &buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (unlikely(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return __smsc75xx_read_reg(dev, index, data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return __smsc75xx_write_reg(dev, index, data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return __smsc75xx_read_reg(dev, index, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return __smsc75xx_write_reg(dev, index, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Loop until the read is completed with timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * called with phy_mutex held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long start_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) netdev_warn(dev->net, "Error reading MII_ACCESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!(val & MII_ACCESS_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } while (!time_after(jiffies, start_time + HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct usbnet *dev = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 val, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mutex_lock(&dev->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* confirm MII not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* set the address, index & direction (read from PHY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) phy_id &= dev->mii.phy_id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) idx &= dev->mii.reg_num_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) | MII_ACCESS_READ | MII_ACCESS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) netdev_warn(dev->net, "Error writing MII_ACCESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) netdev_warn(dev->net, "Error reading MII_DATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = (u16)(val & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mutex_unlock(&dev->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int idx, int regval, int in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct usbnet *dev = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 val, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mutex_lock(&dev->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* confirm MII not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) netdev_warn(dev->net, "Error writing MII_DATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* set the address, index & direction (write to PHY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) phy_id &= dev->mii.phy_id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) idx &= dev->mii.reg_num_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) netdev_warn(dev->net, "Error writing MII_ACCESS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mutex_unlock(&dev->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int idx, int regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int smsc75xx_wait_eeprom(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned long start_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) netdev_warn(dev->net, "Error reading E2P_CMD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) udelay(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } while (!time_after(jiffies, start_time + HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) netdev_warn(dev->net, "EEPROM read operation timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long start_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) netdev_warn(dev->net, "Error reading E2P_CMD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!(val & E2P_CMD_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) udelay(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } while (!time_after(jiffies, start_time + HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) netdev_warn(dev->net, "EEPROM is busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) BUG_ON(!data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = smsc75xx_eeprom_confirm_not_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = smsc75xx_write_reg(dev, E2P_CMD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) netdev_warn(dev->net, "Error writing E2P_CMD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = smsc75xx_wait_eeprom(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) netdev_warn(dev->net, "Error reading E2P_DATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) data[i] = val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) offset++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) BUG_ON(!data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = smsc75xx_eeprom_confirm_not_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Issue write/erase enable command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) val = E2P_CMD_BUSY | E2P_CMD_EWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = smsc75xx_write_reg(dev, E2P_CMD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) netdev_warn(dev->net, "Error writing E2P_CMD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = smsc75xx_wait_eeprom(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) for (i = 0; i < length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Fill data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val = data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = smsc75xx_write_reg(dev, E2P_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) netdev_warn(dev->net, "Error writing E2P_DATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Send "write" command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = smsc75xx_write_reg(dev, E2P_CMD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) netdev_warn(dev->net, "Error writing E2P_CMD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = smsc75xx_wait_eeprom(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) offset++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 dp_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) netdev_warn(dev->net, "Error reading DP_SEL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (dp_sel & DP_SEL_DPRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) udelay(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 length, u32 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 dp_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mutex_lock(&pdata->dataport_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = smsc75xx_dataport_wait_not_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) netdev_warn(dev->net, "Error reading DP_SEL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dp_sel &= ~DP_SEL_RSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dp_sel |= ram_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) netdev_warn(dev->net, "Error writing DP_SEL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for (i = 0; i < length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) netdev_warn(dev->net, "Error writing DP_ADDR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) netdev_warn(dev->net, "Error writing DP_DATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) netdev_warn(dev->net, "Error writing DP_CMD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = smsc75xx_dataport_wait_not_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mutex_unlock(&pdata->dataport_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* returns hash bit number for given MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static u32 smsc75xx_hash(char addr[ETH_ALEN])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void smsc75xx_deferred_multicast_write(struct work_struct *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct smsc75xx_priv *pdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) container_of(param, struct smsc75xx_priv, set_multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct usbnet *dev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pdata->rfe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) netdev_warn(dev->net, "Error writing RFE_CRL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void smsc75xx_set_multicast(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct usbnet *dev = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pdata->rfe_ctl &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pdata->rfe_ctl |= RFE_CTL_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pdata->multicast_hash_table[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (dev->net->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } else if (dev->net->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } else if (!netdev_mc_empty(dev->net)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) netdev_for_each_mc_addr(ha, netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 bitnum = smsc75xx_hash(ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pdata->multicast_hash_table[bitnum / 32] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) (1 << (bitnum % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) netif_dbg(dev, drv, dev->net, "receive own packets only\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pdata->rfe_ctl |= RFE_CTL_DPF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* defer register writes to a sleepable context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) schedule_work(&pdata->set_multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 lcladv, u16 rmtadv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 flow = 0, fct_flow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (duplex == DUPLEX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (cap & FLOW_CTRL_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) flow = (FLOW_TX_FCEN | 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* set fct_flow thresholds to 20% and 80% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) fct_flow = (8 << 8) | 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (cap & FLOW_CTRL_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) flow |= FLOW_RX_FCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) netif_dbg(dev, link, dev->net, "half duplex\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = smsc75xx_write_reg(dev, FLOW, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) netdev_warn(dev->net, "Error writing FLOW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) netdev_warn(dev->net, "Error writing FCT_FLOW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int smsc75xx_link_reset(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct mii_if_info *mii = &dev->mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u16 lcladv, rmtadv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* write to clear phy interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PHY_INT_SRC_CLEAR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) netdev_warn(dev->net, "Error writing INT_STS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mii_check_media(mii, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mii_ethtool_gset(&dev->mii, &ecmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 intdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (urb->actual_length != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) netdev_warn(dev->net, "unexpected urb length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) intdata = get_unaligned_le32(urb->transfer_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (intdata & INT_ENP_PHY_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) usbnet_defer_kevent(dev, EVENT_LINK_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) intdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return MAX_EEPROM_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct ethtool_eeprom *ee, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct usbnet *dev = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ee->magic = LAN75XX_EEPROM_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct ethtool_eeprom *ee, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct usbnet *dev = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ee->magic != LAN75XX_EEPROM_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ee->magic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void smsc75xx_ethtool_get_wol(struct net_device *net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct ethtool_wolinfo *wolinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct usbnet *dev = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) wolinfo->supported = SUPPORTED_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) wolinfo->wolopts = pdata->wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int smsc75xx_ethtool_set_wol(struct net_device *net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct ethtool_wolinfo *wolinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct usbnet *dev = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (wolinfo->wolopts & ~SUPPORTED_WAKE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const struct ethtool_ops smsc75xx_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .get_link = usbnet_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .nway_reset = usbnet_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .get_drvinfo = usbnet_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .get_msglevel = usbnet_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .set_msglevel = usbnet_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .get_eeprom = smsc75xx_ethtool_get_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .set_eeprom = smsc75xx_ethtool_set_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .get_wol = smsc75xx_ethtool_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .set_wol = smsc75xx_ethtool_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .get_link_ksettings = usbnet_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .set_link_ksettings = usbnet_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct usbnet *dev = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!netif_running(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static void smsc75xx_init_mac_address(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* maybe the boot loader passed the MAC address in devicetree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!eth_platform_get_mac_address(&dev->udev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev->net->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (is_valid_ether_addr(dev->net->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* device tree values are valid so use them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) netif_dbg(dev, ifup, dev->net, "MAC address read from the device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* try reading mac address from EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev->net->dev_addr) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (is_valid_ether_addr(dev->net->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* eeprom values are valid so use them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) netif_dbg(dev, ifup, dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "MAC address read from EEPROM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* no useful static MAC address found. generate a random one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) eth_hw_addr_random(dev->net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static int smsc75xx_set_mac_address(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) addr_hi |= ADDR_FILTX_FB_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int smsc75xx_phy_initialize(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int bmcr, ret, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Initialize MII structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev->mii.dev = dev->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev->mii.mdio_read = smsc75xx_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev->mii.mdio_write = smsc75xx_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev->mii.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev->mii.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev->mii.supports_gmii = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* reset phy and wait for reset to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (bmcr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) netdev_warn(dev->net, "Error reading MII_BMCR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } while ((bmcr & BMCR_RESET) && (timeout < 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (timeout >= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) netdev_warn(dev->net, "timeout on PHY Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* phy workaround for gig link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) smsc75xx_phy_gig_workaround(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ADVERTISE_PAUSE_ASYM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ADVERTISE_1000FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* read and write to clear phy interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PHY_INT_MASK_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mii_nway_restart(&dev->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) bool rxenabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) rxenabled = ((buf & MAC_RX_RXEN) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (rxenabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) buf &= ~MAC_RX_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret = smsc75xx_write_reg(dev, MAC_RX, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* add 4 to size for FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) buf &= ~MAC_RX_MAX_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = smsc75xx_write_reg(dev, MAC_RX, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (rxenabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) buf |= MAC_RX_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = smsc75xx_write_reg(dev, MAC_RX, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct usbnet *dev = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) netdev_warn(dev->net, "Failed to set mac rx frame length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return usbnet_change_mtu(netdev, new_mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Enable or disable Rx checksum offload engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int smsc75xx_set_features(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) netdev_features_t features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct usbnet *dev = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (features & NETIF_F_RXCSUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* it's racing here! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) netdev_warn(dev->net, "Error writing RFE_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (buf & PMT_CTL_DEV_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) } while (timeout < 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) netdev_warn(dev->net, "timeout waiting for device ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int smsc75xx_phy_gig_workaround(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct mii_if_info *mii = &dev->mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int ret = 0, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 buf, link_up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* Set the phy in Gig loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) smsc75xx_mdio_write(dev->net, mii->phy_id, MII_BMCR, 0x4040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Wait for the link up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) link_up = smsc75xx_link_ok_nopm(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) } while ((!link_up) && (timeout < 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (timeout >= 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) netdev_warn(dev->net, "Timeout waiting for PHY link up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* phy reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) buf |= PMT_CTL_PHY_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (timeout >= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int smsc75xx_reset(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u32 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int ret = 0, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = smsc75xx_wait_ready(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) buf |= HW_CFG_LRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ret = smsc75xx_write_reg(dev, HW_CFG, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) } while ((buf & HW_CFG_LRST) && (timeout < 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (timeout >= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) buf |= PMT_CTL_PHY_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (timeout >= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = smsc75xx_set_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) netdev_warn(dev->net, "Failed to set mac address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dev->net->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) buf |= HW_CFG_BIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ret = smsc75xx_write_reg(dev, HW_CFG, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (!turbo_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) } else if (dev->udev->speed == USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) (ulong)dev->rx_urb_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) netif_dbg(dev, ifup, dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) netif_dbg(dev, ifup, dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (turbo_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) buf |= (HW_CFG_MEF | HW_CFG_BCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ret = smsc75xx_write_reg(dev, HW_CFG, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* set FIFO sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) buf = (MAX_RX_FIFO_SIZE - 512) / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) buf = (MAX_TX_FIFO_SIZE - 512) / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ret = smsc75xx_read_reg(dev, ID_REV, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* only set default GPIO/LED settings if no EEPROM is detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (!(buf & E2P_CMD_LOADED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret = smsc75xx_write_reg(dev, FLOW, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* Don't need rfe_ctl_lock during initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) pdata->rfe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Enable or disable checksum offload engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) smsc75xx_set_features(dev->net, dev->net->features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) smsc75xx_set_multicast(dev->net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ret = smsc75xx_phy_initialize(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* enable PHY interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) buf |= INT_ENP_PHY_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* allow mac to detect speed and duplex from phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) buf |= (MAC_CR_ADD | MAC_CR_ASD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ret = smsc75xx_write_reg(dev, MAC_CR, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) buf |= MAC_TX_TXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ret = smsc75xx_write_reg(dev, MAC_TX, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) buf |= FCT_TX_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) netdev_warn(dev->net, "Failed to set max rx frame length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) buf |= MAC_RX_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ret = smsc75xx_write_reg(dev, MAC_RX, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) buf |= FCT_RX_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static const struct net_device_ops smsc75xx_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .ndo_open = usbnet_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .ndo_stop = usbnet_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .ndo_start_xmit = usbnet_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .ndo_tx_timeout = usbnet_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .ndo_get_stats64 = usbnet_get_stats64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .ndo_change_mtu = smsc75xx_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .ndo_do_ioctl = smsc75xx_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .ndo_set_rx_mode = smsc75xx_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .ndo_set_features = smsc75xx_set_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct smsc75xx_priv *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ret = usbnet_get_endpoints(dev, intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) pdata->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) spin_lock_init(&pdata->rfe_ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) mutex_init(&pdata->dataport_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (DEFAULT_TX_CSUM_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (DEFAULT_RX_CSUM_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) dev->net->features |= NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ret = smsc75xx_wait_ready(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) goto free_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) smsc75xx_init_mac_address(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* Init all registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = smsc75xx_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) goto cancel_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dev->net->netdev_ops = &smsc75xx_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev->net->flags |= IFF_MULTICAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dev->net->max_mtu = MAX_SINGLE_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) cancel_work:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) cancel_work_sync(&pdata->set_multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) free_pdata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) kfree(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) dev->data[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) cancel_work_sync(&pdata->set_multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) netif_dbg(dev, ifdown, dev->net, "free pdata\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) kfree(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) dev->data[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static u16 smsc_crc(const u8 *buffer, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return bitrev16(crc16(0xFFFF, buffer, len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) u32 wuf_mask1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) int cfg_base = WUF_CFGX + filter * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) int mask_base = WUF_MASKX + filter * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) netdev_warn(dev->net, "Error writing WUF_CFGX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) netdev_warn(dev->net, "Error writing WUF_MASKX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) netdev_warn(dev->net, "Error writing WUF_MASKX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) netdev_warn(dev->net, "Error writing WUF_MASKX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) netdev_warn(dev->net, "Error writing WUF_MASKX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static int smsc75xx_enter_suspend0(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) netdev_warn(dev->net, "Error reading PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) pdata->suspend_flags |= SUSPEND_SUSPEND0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static int smsc75xx_enter_suspend1(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) netdev_warn(dev->net, "Error reading PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) val |= PMT_CTL_SUS_MODE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* clear wol status, enable energy detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) val &= ~PMT_CTL_WUPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) pdata->suspend_flags |= SUSPEND_SUSPEND1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static int smsc75xx_enter_suspend2(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) netdev_warn(dev->net, "Error reading PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) val |= PMT_CTL_SUS_MODE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) pdata->suspend_flags |= SUSPEND_SUSPEND2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static int smsc75xx_enter_suspend3(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (val & FCT_RX_CTL_RXUSED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) netdev_warn(dev->net, "Error reading PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* clear wol status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) val &= ~PMT_CTL_WUPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) val |= PMT_CTL_WUPS_WOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) pdata->suspend_flags |= SUSPEND_SUSPEND3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct mii_if_info *mii = &dev->mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* read to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /* enable interrupt source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ret |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static int smsc75xx_link_ok_nopm(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct mii_if_info *mii = &dev->mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* first, a dummy read, needed to latch some MII phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) netdev_warn(dev->net, "Error reading MII_BMSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) netdev_warn(dev->net, "Error reading MII_BMSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return !!(ret & BMSR_LSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (!netif_running(dev->net)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /* interface is ifconfig down so fully power down hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return smsc75xx_enter_suspend2(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (!link_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* link is down so enter EDPD mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) /* enable PHY wakeup events for if cable is attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) PHY_INT_MASK_ANEG_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) netdev_info(dev->net, "entering SUSPEND1 mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return smsc75xx_enter_suspend1(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* enable PHY wakeup events so we remote wakeup if cable is pulled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) PHY_INT_MASK_LINK_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return smsc75xx_enter_suspend3(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct usbnet *dev = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) u32 val, link_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ret = usbnet_suspend(intf, message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) netdev_warn(dev->net, "usbnet_suspend error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (pdata->suspend_flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) netdev_warn(dev->net, "error during last resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) pdata->suspend_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* determine if link is up using only _nopm functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) link_up = smsc75xx_link_ok_nopm(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (message.event == PM_EVENT_AUTO_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ret = smsc75xx_autosuspend(dev, link_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) /* if we get this far we're not autosuspending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /* if no wol options set, or if link is down and we're not waking on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * PHY activity, enter lowest power SUSPEND2 mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (!(pdata->wolopts & SUPPORTED_WAKE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) !(link_up || (pdata->wolopts & WAKE_PHY))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) netdev_info(dev->net, "entering SUSPEND2 mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) /* disable energy detect (link up) & wake up events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) val &= ~(WUCSR_MPEN | WUCSR_WUEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) netdev_warn(dev->net, "Error reading PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ret = smsc75xx_enter_suspend2(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (pdata->wolopts & WAKE_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* if link is down then configure EDPD and enter SUSPEND1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * otherwise enter SUSPEND0 below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (!link_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) struct mii_if_info *mii = &dev->mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) netdev_info(dev->net, "entering SUSPEND1 mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* enable energy detect power-down mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) PHY_MODE_CTRL_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) ret |= MODE_CTRL_STS_EDPWRDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) PHY_MODE_CTRL_STS, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* enter SUSPEND1 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ret = smsc75xx_enter_suspend1(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) int i, filter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /* disable all filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) for (i = 0; i < WUF_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) netdev_warn(dev->net, "Error writing WUF_CFGX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (pdata->wolopts & WAKE_MCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) const u8 mcast[] = {0x01, 0x00, 0x5E};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) netdev_info(dev->net, "enabling multicast detection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) | smsc_crc(mcast, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) netdev_warn(dev->net, "Error writing wakeup filter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (pdata->wolopts & WAKE_ARP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) const u8 arp[] = {0x08, 0x06};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) netdev_info(dev->net, "enabling ARP detection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) | smsc_crc(arp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) netdev_warn(dev->net, "Error writing wakeup filter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* clear any pending pattern match packet status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) val |= WUCSR_WUFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) netdev_info(dev->net, "enabling packet match detection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) val |= WUCSR_WUEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) netdev_info(dev->net, "disabling packet match detection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) val &= ~WUCSR_WUEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) /* disable magic, bcast & unicast wakeup sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) if (pdata->wolopts & WAKE_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) netdev_info(dev->net, "enabling PHY wakeup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) netdev_warn(dev->net, "Error reading PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /* clear wol status, enable energy detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) val &= ~PMT_CTL_WUPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (pdata->wolopts & WAKE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) netdev_info(dev->net, "enabling magic packet wakeup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* clear any pending magic packet status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) val |= WUCSR_MPR | WUCSR_MPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (pdata->wolopts & WAKE_BCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) netdev_info(dev->net, "enabling broadcast detection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (pdata->wolopts & WAKE_UCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) netdev_info(dev->net, "enabling unicast detection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) val |= WUCSR_WUFR | WUCSR_PFDA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* enable receiver to enable frame reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) val |= MAC_RX_RXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /* some wol options are enabled, so enter SUSPEND0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) netdev_info(dev->net, "entering SUSPEND0 mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ret = smsc75xx_enter_suspend0(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) * TODO: resume() might need to handle the suspend failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) * in system sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (ret && PMSG_IS_AUTO(message))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) usbnet_resume(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static int smsc75xx_resume(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) struct usbnet *dev = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) u8 suspend_flags = pdata->suspend_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) /* do this first to ensure it's cleared even in error case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) pdata->suspend_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (suspend_flags & SUSPEND_ALLMODES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /* Disable wakeup sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) netdev_warn(dev->net, "Error reading WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) | WUCSR_BCST_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) netdev_warn(dev->net, "Error writing WUCSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) /* clear wake-up status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) netdev_warn(dev->net, "Error reading PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) val &= ~PMT_CTL_WOL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) val |= PMT_CTL_WUPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (suspend_flags & SUSPEND_SUSPEND2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) netdev_info(dev->net, "resuming from SUSPEND2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) netdev_warn(dev->net, "Error reading PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) val |= PMT_CTL_PHY_PWRUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) netdev_warn(dev->net, "Error writing PMT_CTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) ret = smsc75xx_wait_ready(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) return usbnet_resume(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) u32 rx_cmd_a, u32 rx_cmd_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if (!(dev->net->features & NETIF_F_RXCSUM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) skb->ip_summed = CHECKSUM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) skb->ip_summed = CHECKSUM_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /* This check is no longer done by usbnet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (skb->len < dev->net->hard_header_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) while (skb->len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) u32 rx_cmd_a, rx_cmd_b, align_count, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) struct sk_buff *ax_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) unsigned char *packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) rx_cmd_a = get_unaligned_le32(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) skb_pull(skb, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) rx_cmd_b = get_unaligned_le32(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) skb_pull(skb, 4 + RXW_PADDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) packet = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /* get the packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) netif_dbg(dev, rx_err, dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) dev->net->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) dev->net->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (rx_cmd_a & RX_CMD_A_FCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) dev->net->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) dev->net->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) netif_dbg(dev, rx_err, dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) "size err rx_cmd_a=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) rx_cmd_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) /* last frame in this batch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (skb->len == size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) rx_cmd_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) skb_trim(skb, skb->len - 4); /* remove fcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) skb->truesize = size + sizeof(struct sk_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) ax_skb = skb_clone(skb, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (unlikely(!ax_skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) netdev_warn(dev->net, "Error allocating skb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) ax_skb->len = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) ax_skb->data = packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) skb_set_tail_pointer(ax_skb, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) rx_cmd_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) ax_skb->truesize = size + sizeof(struct sk_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) usbnet_skb_return(dev, ax_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) skb_pull(skb, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) /* padding bytes before the next frame starts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (skb->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) skb_pull(skb, align_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) struct sk_buff *skb, gfp_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) u32 tx_cmd_a, tx_cmd_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) if (skb_cow_head(skb, SMSC75XX_TX_OVERHEAD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (skb->ip_summed == CHECKSUM_PARTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) if (skb_is_gso(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) tx_cmd_a |= TX_CMD_A_LSO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) tx_cmd_b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ptr = skb_push(skb, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) put_unaligned_le32(tx_cmd_a, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) put_unaligned_le32(tx_cmd_b, ptr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) return skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static int smsc75xx_manage_power(struct usbnet *dev, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) dev->intf->needs_remote_wakeup = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) static const struct driver_info smsc75xx_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .description = "smsc75xx USB 2.0 Gigabit Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .bind = smsc75xx_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .unbind = smsc75xx_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .link_reset = smsc75xx_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .reset = smsc75xx_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .rx_fixup = smsc75xx_rx_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .tx_fixup = smsc75xx_tx_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .status = smsc75xx_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .manage_power = smsc75xx_manage_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static const struct usb_device_id products[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) /* SMSC7500 USB Gigabit Ethernet Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .driver_info = (unsigned long) &smsc75xx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) /* SMSC7500 USB Gigabit Ethernet Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .driver_info = (unsigned long) &smsc75xx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) { }, /* END */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) MODULE_DEVICE_TABLE(usb, products);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static struct usb_driver smsc75xx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .name = SMSC_CHIPNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .id_table = products,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .probe = usbnet_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .suspend = smsc75xx_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .resume = smsc75xx_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .reset_resume = smsc75xx_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .disconnect = usbnet_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .disable_hub_initiated_lpm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .supports_autosuspend = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) module_usb_driver(smsc75xx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) MODULE_AUTHOR("Nancy Lin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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