^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ipv6.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <net/ip6_checksum.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <uapi/linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/cdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <crypto/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Information for net-next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NETNEXT_VERSION "11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Information for net */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NET_VERSION "11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MODULENAME "r8152"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R8152_PHY_ID 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLA_IDR 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLA_RCR 0xc010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLA_RMS 0xc016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PLA_RXFIFO_CTRL0 0xc0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PLA_RXFIFO_CTRL1 0xc0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PLA_RXFIFO_CTRL2 0xc0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PLA_DMY_REG0 0xc0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PLA_FMC 0xc0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PLA_CFG_WOL 0xc0b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLA_TEREDO_CFG 0xc0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLA_TEREDO_WAKE_BASE 0xc0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PLA_MAR 0xcd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLA_BACKUP 0xd000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLA_BDC_CR 0xd1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLA_TEREDO_TIMER 0xd2cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PLA_REALWOW_TIMER 0xd2e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLA_UPHY_TIMER 0xd388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PLA_SUSPEND_FLAG 0xd38a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLA_INDICATE_FALG 0xd38c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLA_EXTRA_STATUS 0xd398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PLA_EFUSE_DATA 0xdd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PLA_EFUSE_CMD 0xdd02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PLA_LEDSEL 0xdd90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PLA_LED_FEATURE 0xdd92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PLA_PHYAR 0xde00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLA_BOOT_CTRL 0xe004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLA_LWAKE_CTRL_REG 0xe007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PLA_GPHY_INTR_IMR 0xe022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PLA_EEE_CR 0xe040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PLA_EEEP_CR 0xe080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PLA_MAC_PWR_CTRL 0xe0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PLA_MAC_PWR_CTRL2 0xe0ca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PLA_MAC_PWR_CTRL3 0xe0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PLA_MAC_PWR_CTRL4 0xe0ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PLA_WDT6_CTRL 0xe428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PLA_TCR0 0xe610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PLA_TCR1 0xe612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PLA_MTPS 0xe615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PLA_TXFIFO_CTRL 0xe618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PLA_RSTTALLY 0xe800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PLA_CR 0xe813
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PLA_CRWECR 0xe81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PLA_CONFIG5 0xe822
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PLA_PHY_PWR 0xe84c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PLA_OOB_CTRL 0xe84f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PLA_CPCR 0xe854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PLA_MISC_0 0xe858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PLA_MISC_1 0xe85a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PLA_OCP_GPHY_BASE 0xe86c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PLA_TALLYCNT 0xe890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PLA_SFF_STS_7 0xe8de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PLA_PHYSTATUS 0xe908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PLA_CONFIG6 0xe90a /* CONFIG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PLA_BP_BA 0xfc26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLA_BP_0 0xfc28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PLA_BP_1 0xfc2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PLA_BP_2 0xfc2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PLA_BP_3 0xfc2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PLA_BP_4 0xfc30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PLA_BP_5 0xfc32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PLA_BP_6 0xfc34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PLA_BP_7 0xfc36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PLA_BP_EN 0xfc38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define USB_USB2PHY 0xb41e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define USB_SSPHYLINK1 0xb426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define USB_SSPHYLINK2 0xb428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define USB_U2P3_CTRL 0xb460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define USB_CSR_DUMMY1 0xb464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define USB_CSR_DUMMY2 0xb466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define USB_DEV_STAT 0xb808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define USB_CONNECT_TIMER 0xcbf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define USB_MSC_TIMER 0xcbfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define USB_BURST_SIZE 0xcfc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define USB_FW_FIX_EN0 0xcfca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define USB_FW_FIX_EN1 0xcfcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define USB_LPM_CONFIG 0xcfd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define USB_CSTMR 0xcfef /* RTL8153A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define USB_FW_CTRL 0xd334 /* RTL8153B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define USB_FC_TIMER 0xd340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define USB_USB_CTRL 0xd406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define USB_PHY_CTRL 0xd408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define USB_TX_AGG 0xd40a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define USB_RX_BUF_TH 0xd40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define USB_USB_TIMER 0xd428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USB_RX_EARLY_TIMEOUT 0xd42c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define USB_RX_EARLY_SIZE 0xd42e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define USB_TX_DMA 0xd434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define USB_UPT_RXDMA_OWN 0xd437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USB_TOLERANCE 0xd490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define USB_LPM_CTRL 0xd41a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define USB_BMU_RESET 0xd4b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define USB_U1U2_TIMER 0xd4da
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define USB_FW_TASK 0xd4e8 /* RTL8153B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define USB_UPS_CTRL 0xd800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USB_POWER_CUT 0xd80a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define USB_MISC_0 0xd81a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define USB_MISC_1 0xd81f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USB_AFE_CTRL2 0xd824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USB_UPS_CFG 0xd842
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define USB_UPS_FLAGS 0xd848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define USB_WDT1_CTRL 0xe404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define USB_WDT11_CTRL 0xe43c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define USB_BP_BA PLA_BP_BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define USB_BP_0 PLA_BP_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define USB_BP_1 PLA_BP_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define USB_BP_2 PLA_BP_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define USB_BP_3 PLA_BP_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define USB_BP_4 PLA_BP_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define USB_BP_5 PLA_BP_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define USB_BP_6 PLA_BP_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USB_BP_7 PLA_BP_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define USB_BP_EN PLA_BP_EN /* RTL8153A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define USB_BP_8 0xfc38 /* RTL8153B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define USB_BP_9 0xfc3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define USB_BP_10 0xfc3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define USB_BP_11 0xfc3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define USB_BP_12 0xfc40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define USB_BP_13 0xfc42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define USB_BP_14 0xfc44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define USB_BP_15 0xfc46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define USB_BP2_EN 0xfc48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* OCP Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OCP_ALDPS_CONFIG 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OCP_EEE_CONFIG1 0x2080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OCP_EEE_CONFIG2 0x2092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OCP_EEE_CONFIG3 0x2094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OCP_BASE_MII 0xa400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OCP_EEE_AR 0xa41a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OCP_EEE_DATA 0xa41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OCP_PHY_STATUS 0xa420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OCP_NCTL_CFG 0xa42c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OCP_POWER_CFG 0xa430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OCP_EEE_CFG 0xa432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OCP_SRAM_ADDR 0xa436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OCP_SRAM_DATA 0xa438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OCP_DOWN_SPEED 0xa442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OCP_EEE_ABLE 0xa5c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OCP_EEE_ADV 0xa5d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OCP_EEE_LPABLE 0xa5d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OCP_PHY_PATCH_STAT 0xb800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OCP_PHY_PATCH_CMD 0xb820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OCP_PHY_LOCK 0xb82e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OCP_ADC_IOFFSET 0xbcfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OCP_ADC_CFG 0xbc06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OCP_SYSCLK_CFG 0xc416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* SRAM Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SRAM_GREEN_CFG 0x8011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SRAM_LPF_CFG 0x8012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SRAM_10M_AMP1 0x8080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SRAM_10M_AMP2 0x8082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SRAM_IMPEDANCE 0x8084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SRAM_PHY_LOCK 0xb82e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* PLA_RCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RCR_AAP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RCR_APM 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RCR_AM 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RCR_AB 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* PLA_RXFIFO_CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RXFIFO_THR1_NORMAL 0x00080002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RXFIFO_THR1_OOB 0x01800003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* PLA_RXFIFO_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define RXFIFO_THR2_FULL 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define RXFIFO_THR2_HIGH 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define RXFIFO_THR2_OOB 0x0000004a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RXFIFO_THR2_NORMAL 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* PLA_RXFIFO_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define RXFIFO_THR3_FULL 0x00000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define RXFIFO_THR3_HIGH 0x00000048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RXFIFO_THR3_OOB 0x0000005a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RXFIFO_THR3_NORMAL 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* PLA_TXFIFO_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TXFIFO_THR_NORMAL 0x00400008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TXFIFO_THR_NORMAL2 0x01000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* PLA_DMY_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ECM_ALDPS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* PLA_FMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define FMC_FCR_MCU_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* PLA_EEEP_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define EEEP_CR_EEEP_TX 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* PLA_WDT6_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define WDT6_SET_MODE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* PLA_TCR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TCR0_TX_EMPTY 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TCR0_AUTO_FIFO 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* PLA_TCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define VERSION_MASK 0x7cf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* PLA_MTPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MTPS_JUMBO (12 * 1024 / 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MTPS_DEFAULT (6 * 1024 / 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* PLA_RSTTALLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TALLY_RESET 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* PLA_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CR_RST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CR_RE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CR_TE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* PLA_CRWECR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CRWECR_NORAML 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CRWECR_CONFIG 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* PLA_OOB_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define NOW_IS_OOB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TXFIFO_EMPTY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RXFIFO_EMPTY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define LINK_LIST_READY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DIS_MCU_CLROOB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* PLA_MISC_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define RXDY_GATED_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* PLA_SFF_STS_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define RE_INIT_LL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MCU_BORW_EN 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* PLA_CPCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CPCR_RX_VLAN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* PLA_CFG_WOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MAGIC_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PLA_TEREDO_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TEREDO_SEL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TEREDO_WAKE_MASK 0x7f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TEREDO_RS_EVENT_MASK 0x00fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define OOB_TEREDO_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* PLA_BDC_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ALDPS_PROXY_MODE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* PLA_EFUSE_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define EFUSE_READ_CMD BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define EFUSE_DATA_BIT16 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* PLA_CONFIG34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define LINK_ON_WAKE_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define LINK_OFF_WAKE_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* PLA_CONFIG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define LANWAKE_CLR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* PLA_CONFIG5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define BWF_EN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MWF_EN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define UWF_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define LAN_WAKE_EN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* PLA_LED_FEATURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define LED_MODE_MASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* PLA_PHY_PWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TX_10M_IDLE_EN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PFM_PWM_SWITCH 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TEST_IO_OFF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* PLA_MAC_PWR_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define D3_CLK_GATED_EN 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MCU_CLK_RATIO 0x07010f07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ALDPS_SPDWN_RATIO 0x0f87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* PLA_MAC_PWR_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define EEE_SPDWN_RATIO 0x8007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MAC_CLK_SPDWN_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* PLA_MAC_PWR_CTRL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PLA_MCU_SPDWN_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define PKT_AVAIL_SPDWN_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SUSPEND_SPDWN_EN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define U1U2_SPDWN_EN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define L1_SPDWN_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* PLA_MAC_PWR_CTRL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PWRSAVE_SPDWN_EN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define RXDV_SPDWN_EN 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TX10MIDLE_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TP100_SPDWN_EN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define TP500_SPDWN_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TP1000_SPDWN_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define EEE_SPDWN_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* PLA_GPHY_INTR_IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define GPHY_STS_MSK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SPEED_DOWN_MSK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SPDWN_RXDV_MSK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SPDWN_LINKCHG_MSK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* PLA_PHYAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PHYAR_FLAG 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* PLA_EEE_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define EEE_RX_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define EEE_TX_EN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* PLA_BOOT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define AUTOLOAD_DONE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* PLA_LWAKE_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define LANWAKE_PIN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* PLA_SUSPEND_FLAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define LINK_CHG_EVENT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* PLA_INDICATE_FALG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define UPCOMING_RUNTIME_D3 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define DEBUG_OE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DEBUG_LTSSM 0x0082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* PLA_EXTRA_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CUR_LINK_OK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define LINK_CHANGE_FLAG BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define POLL_LINK_CHG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* USB_USB2PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define USB2PHY_SUSPEND 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define USB2PHY_L1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* USB_SSPHYLINK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DELAY_PHY_PWR_CHG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* USB_SSPHYLINK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define pwd_dn_scale_mask 0x3ffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define pwd_dn_scale(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* USB_CSR_DUMMY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DYNAMIC_BURST 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* USB_CSR_DUMMY2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define EP4_FULL_FC 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* USB_DEV_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define STAT_SPEED_MASK 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define STAT_SPEED_HIGH 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define STAT_SPEED_FULL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* USB_FW_FIX_EN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define FW_FIX_SUSPEND BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* USB_FW_FIX_EN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define FW_IP_RESET_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* USB_LPM_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define LPM_U1U2_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* USB_TX_AGG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define TX_AGG_MAX_THRESHOLD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* USB_RX_BUF_TH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define RX_THR_SUPPER 0x0c350180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define RX_THR_HIGH 0x7a120180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define RX_THR_SLOW 0xffff0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define RX_THR_B 0x00010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* USB_TX_DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define TEST_MODE_DISABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define TX_SIZE_ADJUST1 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* USB_BMU_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BMU_RESET_EP_IN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BMU_RESET_EP_OUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* USB_UPT_RXDMA_OWN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define OWN_UPDATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define OWN_CLEAR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* USB_FW_TASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define FC_PATCH_TASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* USB_UPS_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define POWER_CUT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* USB_PM_CTRL_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define RESUME_INDICATE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* USB_CSTMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define FORCE_SUPER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* USB_FW_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define FLOW_CTRL_PATCH_OPT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* USB_FC_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CTRL_TIMER_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* USB_USB_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define RX_AGG_DISABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define RX_ZERO_EN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* USB_U2P3_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define U2P3_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* USB_POWER_CUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define PWR_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define PHASE2_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define UPS_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define USP_PREWAKE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* USB_MISC_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define PCUT_STATUS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* USB_RX_EARLY_TIMEOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define COALESCE_SUPER 85000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define COALESCE_HIGH 250000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define COALESCE_SLOW 524280U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* USB_WDT1_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define WTD1_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* USB_WDT11_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define TIMER11_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* USB_LPM_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* bit 4 ~ 5: fifo empty boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* bit 2 ~ 3: LMP timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define LPM_TIMER_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define LPM_TIMER_500MS 0x04 /* 500 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define LPM_TIMER_500US 0x0c /* 500 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define ROK_EXIT_LPM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* USB_AFE_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SEN_VAL_MASK 0xf800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SEN_VAL_NORMAL 0xa000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SEL_RXIDLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* USB_UPS_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SAW_CNT_1MS_MASK 0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* USB_UPS_FLAGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define UPS_FLAGS_R_TUNE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define UPS_FLAGS_250M_CKDIV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define UPS_FLAGS_EN_ALDPS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define ups_flags_speed(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define UPS_FLAGS_EN_EEE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define UPS_FLAGS_EN_500M_EEE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define UPS_FLAGS_EN_GREEN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) enum spd_duplex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) NWAY_10M_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) NWAY_10M_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) NWAY_100M_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) NWAY_100M_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) NWAY_1000M_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) FORCE_10M_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) FORCE_10M_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) FORCE_100M_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) FORCE_100M_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* OCP_ALDPS_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define ENPWRSAVE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define ENPDNPS 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define LINKENA 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define DIS_SDSAVE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* OCP_PHY_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define PHY_STAT_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define PHY_STAT_EXT_INIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PHY_STAT_LAN_ON 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PHY_STAT_PWRDN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* OCP_NCTL_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define PGA_RETURN_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* OCP_POWER_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define EEE_CLKDIV_EN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define EN_ALDPS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define EN_10M_PLLOFF 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* OCP_EEE_CONFIG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define RG_TXLPI_MSK_HFDUP 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define RG_MATCLR_EN 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define EEE_10_CAP 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define EEE_NWAY_EN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define TX_QUIET_EN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define RX_QUIET_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define sd_rise_time_mask 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define RG_RXLPI_MSK_HFDUP 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* OCP_EEE_CONFIG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define RG_DACQUIET_EN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define RG_LDVQUIET_EN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define RG_CKRSEL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define RG_EEEPRG_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* OCP_EEE_CONFIG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define fast_snr_mask 0xff80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define MSK_PH 0x0006 /* bit 0 ~ 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* OCP_EEE_AR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* bit[15:14] function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define FUN_ADDR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define FUN_DATA 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* bit[4:0] device addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* OCP_EEE_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define CTAP_SHORT_EN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define EEE10_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* OCP_DOWN_SPEED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define EN_EEE_CMODE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define EN_EEE_1000 BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define EN_EEE_100 BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define EN_10M_CLKDIV BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define EN_10M_BGOFF 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* OCP_PHY_STATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define TXDIS_STATE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define ABD_STATE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* OCP_PHY_PATCH_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define PATCH_READY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* OCP_PHY_PATCH_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define PATCH_REQUEST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* OCP_PHY_LOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define PATCH_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* OCP_ADC_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define CKADSEL_L 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define ADC_EN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define EN_EMI_L 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* OCP_SYSCLK_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define clk_div_expo(x) (min(x, 5) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* SRAM_GREEN_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define GREEN_ETH_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define R_TUNE_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* SRAM_LPF_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define LPF_AUTO_TUNE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* SRAM_10M_AMP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define GDAC_IB_UPALL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* SRAM_10M_AMP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define AMP_DN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* SRAM_IMPEDANCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define RX_DRIVING_MASK 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* SRAM_PHY_LOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define PHY_PATCH_LOCK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* MAC PASSTHRU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define AD_MASK 0xfee0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define BND_MASK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define BD_MASK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define EFUSE 0xcfdb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define PASS_THRU_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) enum rtl_register_content {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) _1000bps = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) _100bps = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) _10bps = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) LINK_STATUS = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) FULL_DUP = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define RTL8152_MAX_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define RTL8152_MAX_RX 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define INTBUFSIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define TX_ALIGN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define RX_ALIGN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define RTL8152_RX_MAX_PENDING 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define RTL8152_RXFG_HEADSZ 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define INTR_LINK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define RTL8152_REQT_READ 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define RTL8152_REQT_WRITE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define RTL8152_REQ_GET_REGS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define RTL8152_REQ_SET_REGS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define BYTE_EN_DWORD 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define BYTE_EN_WORD 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define BYTE_EN_BYTE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define BYTE_EN_SIX_BYTES 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define BYTE_EN_START_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define BYTE_EN_END_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define RTL8153_MAX_PACKET 9216 /* 9K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ETH_FCS_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define RTL8153_RMS RTL8153_MAX_PACKET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define RTL8152_TX_TIMEOUT (5 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define RTL8152_NAPI_WEIGHT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sizeof(struct rx_desc) + RX_ALIGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* rtl8152 flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) enum rtl8152_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) RTL8152_UNPLUG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) RTL8152_SET_RX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) WORK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RTL8152_LINK_CHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) SELECTIVE_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PHY_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SCHEDULE_TASKLET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) GREEN_ETHERNET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) DELL_TB_RX_AGG_BUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) LENOVO_MACPASSTHRU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Define these values to match your device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define VENDOR_ID_REALTEK 0x0bda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define VENDOR_ID_MICROSOFT 0x045e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define VENDOR_ID_SAMSUNG 0x04e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define VENDOR_ID_LENOVO 0x17ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define VENDOR_ID_LINKSYS 0x13b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define VENDOR_ID_NVIDIA 0x0955
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define VENDOR_ID_TPLINK 0x2357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define MCU_TYPE_PLA 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define MCU_TYPE_USB 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct tally_counter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __le64 tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __le64 rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __le64 tx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __le32 rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __le16 rx_missed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __le16 align_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) __le32 tx_one_collision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) __le32 tx_multi_collision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) __le64 rx_unicast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) __le64 rx_broadcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) __le32 rx_multicast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) __le16 tx_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __le16 tx_underrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __le32 opts1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define RX_LEN_MASK 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __le32 opts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define RD_UDP_CS BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define RD_TCP_CS BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define RD_IPV6_CS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define RD_IPV4_CS BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __le32 opts3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define IPF BIT(23) /* IP checksum fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define UDPF BIT(22) /* UDP checksum fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define TCPF BIT(21) /* TCP checksum fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define RX_VLAN_TAG BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) __le32 opts4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __le32 opts5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __le32 opts6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) __le32 opts1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define TX_FS BIT(31) /* First segment of a packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define TX_LS BIT(30) /* Final segment of a packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define GTSENDV4 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define GTSENDV6 BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define GTTCPHO_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define GTTCPHO_MAX 0x7fU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define TX_LEN_MAX 0x3ffffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __le32 opts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define MSS_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define MSS_MAX 0x7ffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define TCPHO_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define TCPHO_MAX 0x7ffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define TX_VLAN_TAG BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct r8152;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct rx_agg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct list_head list, info_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct r8152 *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) void *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct tx_agg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct r8152 *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) void *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) void *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 skb_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 skb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct r8152 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct usb_interface *intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct urb *intr_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct tx_agg tx_info[RTL8152_MAX_TX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct list_head rx_info, rx_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct list_head rx_done, tx_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct sk_buff_head tx_queue, rx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) spinlock_t rx_lock, tx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct delayed_work schedule, hw_phy_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct mii_if_info mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct mutex control; /* use for hw setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct notifier_block pm_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct tasklet_struct tx_tl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct rtl_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) void (*init)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) int (*enable)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) void (*disable)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) void (*up)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) void (*down)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) void (*unload)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) bool (*in_nway)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) void (*hw_phy_cfg)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) void (*autosuspend_en)(struct r8152 *tp, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) } rtl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct ups_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 _10m_ckdiv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 _250m_ckdiv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u32 aldps:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 lite_mode:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 speed_duplex:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 eee:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 eee_lite:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 eee_ckdiv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u32 eee_plloff_100:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 eee_plloff_giga:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 eee_cmod_lv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 green:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u32 flow_control:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 ctap_short_off:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) } ups_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define RTL_VER_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct rtl_fw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) const char *fw_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) char version[RTL_VER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int (*pre_fw)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int (*post_fw)(struct r8152 *tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) bool retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) } rtl_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) atomic_t rx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) bool eee_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int intr_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u32 saved_wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 tx_qlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 coalesce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u32 rx_buf_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 rx_copybreak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u16 ocp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u16 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u16 eee_adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u8 *intr_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u8 duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u8 autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * struct fw_block - block type and total length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * RTL_FW_USB and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * @length: total length of the current block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct fw_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __le32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * struct fw_header - header of the firmware file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * @checksum: checksum of sha256 which is calculated from the whole file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * except the checksum field of the file. That is, calculate sha256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * from the version field to the end of the file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * @version: version of this firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * @blocks: the first firmware block of the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct fw_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u8 checksum[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) char version[RTL_VER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct fw_block blocks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * The layout of the firmware block is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * <struct fw_mac> + <info> + <firmware data>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * @fw_offset: offset of the firmware binary data. The start address of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * the data would be the address of struct fw_mac + @fw_offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * @fw_reg: the register to load the firmware. Depends on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * @bp_ba_addr: the register to write break point base address. Depends on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * @bp_ba_value: break point base address. Depends on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * @bp_en_addr: the register to write break point enabled mask. Depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * @bp_en_value: break point enabled mask. Depends on the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * @bp_start: the start register of break points. Depends on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * @bp_num: the break point number which needs to be set for this firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Depends on the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * @bp: break points. Depends on firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * @fw_ver_reg: the register to store the fw version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * @fw_ver_data: the firmware version of the current type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * @info: additional information for debugging, and is followed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * binary data of firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct fw_mac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct fw_block blk_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) __le16 fw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) __le16 fw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) __le16 bp_ba_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) __le16 bp_ba_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) __le16 bp_en_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) __le16 bp_en_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) __le16 bp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) __le16 bp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) __le16 bp[16]; /* any value determined by firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) __le16 fw_ver_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u8 fw_ver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) char info[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * This is used to set patch key when loading the firmware of PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * @key_reg: the register to write the patch key.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * @key_data: patch key.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct fw_phy_patch_key {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct fw_block blk_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) __le16 key_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) __le16 key_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * The layout of the firmware block is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * <struct fw_phy_nc> + <info> + <firmware data>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * @fw_offset: offset of the firmware binary data. The start address of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * the data would be the address of struct fw_phy_nc + @fw_offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * @fw_reg: the register to load the firmware. Depends on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * @ba_reg: the register to write the base address. Depends on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * @ba_data: base address. Depends on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * @patch_en_addr: the register of enabling patch mode. Depends on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * @patch_en_value: patch mode enabled mask. Depends on the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * @mode_reg: the regitster of switching the mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * @mod_pre: the mode needing to be set before loading the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * @mod_post: the mode to be set when finishing to load the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * @bp_start: the start register of break points. Depends on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * @bp_num: the break point number which needs to be set for this firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * Depends on the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * @bp: break points. Depends on firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * @info: additional information for debugging, and is followed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * binary data of firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct fw_phy_nc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct fw_block blk_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) __le16 fw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) __le16 fw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __le16 ba_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) __le16 ba_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) __le16 patch_en_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) __le16 patch_en_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) __le16 mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) __le16 mode_pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) __le16 mode_post;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) __le16 bp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) __le16 bp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) __le16 bp[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) char info[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) enum rtl_fw_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) RTL_FW_END = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) RTL_FW_PLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) RTL_FW_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) RTL_FW_PHY_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) RTL_FW_PHY_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) RTL_FW_PHY_NC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) enum rtl_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) RTL_VER_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) RTL_VER_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) RTL_VER_02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) RTL_VER_03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) RTL_VER_04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) RTL_VER_05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) RTL_VER_06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) RTL_VER_07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) RTL_VER_08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) RTL_VER_09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) RTL_VER_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) enum tx_csum_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) TX_CSUM_SUCCESS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) TX_CSUM_TSO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) TX_CSUM_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define RTL_ADVERTISED_10_HALF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define RTL_ADVERTISED_10_FULL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define RTL_ADVERTISED_100_HALF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define RTL_ADVERTISED_100_FULL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define RTL_ADVERTISED_1000_HALF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define RTL_ADVERTISED_1000_FULL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * The RTL chips use a 64 element hash table based on the Ethernet CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static const int multicast_filter_limit = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static unsigned int agg_buf_sz = 16384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) VLAN_ETH_HLEN - ETH_FCS_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) void *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) tmp = kmalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) value, index, tmp, size, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) memset(data, 0xff, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) memcpy(data, tmp, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) void *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) tmp = kmemdup(data, size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) value, index, tmp, size, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static void rtl_set_unplug(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (tp->udev->state == USB_STATE_NOTATTACHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) set_bit(RTL8152_UNPLUG, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) void *data, u16 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u16 limit = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* both size and indix must be 4 bytes align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if ((size & 3) || !size || (index & 3) || !data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if ((u32)index + (u32)size > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) while (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (size > limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = get_registers(tp, index, type, limit, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) index += limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) data += limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) size -= limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = get_registers(tp, index, type, size, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) index += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) data += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (ret == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) rtl_set_unplug(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u16 size, void *data, u16 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) u16 byteen_start, byteen_end, byen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) u16 limit = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* both size and indix must be 4 bytes align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if ((size & 3) || !size || (index & 3) || !data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if ((u32)index + (u32)size > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) byteen_start = byteen & BYTE_EN_START_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) byteen_end = byteen & BYTE_EN_END_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) byen = byteen_start | (byteen_start << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ret = set_registers(tp, index, type | byen, 4, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) index += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) data += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) size -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) size -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) while (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (size > limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = set_registers(tp, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) type | BYTE_EN_DWORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) limit, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) index += limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) data += limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) size -= limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ret = set_registers(tp, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) type | BYTE_EN_DWORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) size, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) index += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) data += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) byen = byteen_end | (byteen_end >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ret = set_registers(tp, index, type | byen, 4, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) error1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (ret == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) rtl_set_unplug(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) __le32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) generic_ocp_read(tp, index, sizeof(data), &data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return __le32_to_cpu(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) __le32 tmp = __cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) __le32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u16 byen = BYTE_EN_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u8 shift = index & 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) index &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) byen <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) data = __le32_to_cpu(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) data >>= (shift * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) data &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return (u16)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u32 mask = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) __le32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) u16 byen = BYTE_EN_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) u8 shift = index & 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) data &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (index & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) byen <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) mask <<= (shift * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) data <<= (shift * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) index &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) tmp = __cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) __le32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) u8 shift = index & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) index &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) data = __le32_to_cpu(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) data >>= (shift * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) data &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return (u8)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u32 mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) __le32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u16 byen = BYTE_EN_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u8 shift = index & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) data &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (index & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) byen <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) mask <<= (shift * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) data <<= (shift * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) index &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) tmp = __cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u16 ocp_base, ocp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ocp_base = addr & 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (ocp_base != tp->ocp_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) tp->ocp_base = ocp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ocp_index = (addr & 0x0fff) | 0xb000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) u16 ocp_base, ocp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ocp_base = addr & 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (ocp_base != tp->ocp_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) tp->ocp_base = ocp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ocp_index = (addr & 0x0fff) | 0xb000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static void sram_write(struct r8152 *tp, u16 addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ocp_reg_write(tp, OCP_SRAM_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static u16 sram_read(struct r8152 *tp, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return ocp_reg_read(tp, OCP_SRAM_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (phy_id != R8152_PHY_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret = r8152_mdio_read(tp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (phy_id != R8152_PHY_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) r8152_mdio_write(tp, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct sockaddr *addr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) int ret = -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (!is_valid_ether_addr(addr->sa_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* Devices containing proper chips can support a persistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * host system provided MAC address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * Examples of this are Dell TB15 and Dell WD15 docks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) union acpi_object *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) unsigned char buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) char *mac_obj_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) acpi_object_type mac_obj_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) int mac_strlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) mac_obj_name = "\\MACA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) mac_obj_type = ACPI_TYPE_STRING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) mac_strlen = 0x16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* test for -AD variant of RTL8153 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if ((ocp_data & AD_MASK) == 0x1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* test for MAC address pass-through bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if ((ocp_data & PASS_THRU_MASK) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) netif_dbg(tp, probe, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) "No efuse for RTL8153-AD MAC pass through\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* test for RTL8153-BND and RTL8153-BD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) netif_dbg(tp, probe, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) "Invalid variant for MAC pass through\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) mac_obj_name = "\\_SB.AMAC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) mac_obj_type = ACPI_TYPE_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) mac_strlen = 0x17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* returns _AUXMAC_#AABBCCDDEEFF# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) obj = (union acpi_object *)buffer.pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (!ACPI_SUCCESS(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) netif_warn(tp, probe, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) obj->type, obj->string.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) goto amacout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) netif_warn(tp, probe, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) "Invalid header when reading pass-thru MAC addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) goto amacout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ret = hex2bin(buf, obj->string.pointer + 9, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (!(ret == 0 && is_valid_ether_addr(buf))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) netif_warn(tp, probe, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ret, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) goto amacout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) memcpy(sa->sa_data, buf, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) netif_info(tp, probe, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) "Using pass-thru MAC addr %pM\n", sa->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) amacout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) kfree(obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct net_device *dev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) sa->sa_family = dev->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (tp->version == RTL_VER_01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* if device doesn't support MAC pass through this will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * be expected to be non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ret = vendor_mac_passthru_addr_read(tp, sa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ret = pla_ocp_read(tp, PLA_BACKUP, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) sa->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) netif_err(tp, probe, dev, "Get ether addr fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) } else if (!is_valid_ether_addr(sa->sa_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) sa->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) eth_hw_addr_random(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) ether_addr_copy(sa->sa_data, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) netif_info(tp, probe, dev, "Random ether addr %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) sa->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static int set_ethernet_addr(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct net_device *dev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct sockaddr sa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ret = determine_ethernet_addr(tp, &sa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (tp->version == RTL_VER_01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ether_addr_copy(dev->dev_addr, sa.sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ret = rtl8152_set_mac_address(dev, &sa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static void read_bulk_callback(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) int status = urb->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct rx_agg *agg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct r8152 *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) agg = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (!agg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) tp = agg->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (!tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (!test_bit(WORK_ENABLE, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* When link down, the driver would cancel all bulks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /* This avoid the re-submitting bulk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (!netif_carrier_ok(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) usb_mark_last_busy(tp->udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (urb->actual_length < ETH_ZLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) list_add_tail(&agg->list, &tp->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) napi_schedule(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) case -ESHUTDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) rtl_set_unplug(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) netif_device_detach(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) case -ENOENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return; /* the urb is in unlink state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) case -ETIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) netdev_warn(netdev, "maybe reset is needed?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) netdev_warn(netdev, "Rx status %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) r8152_submit_rx(tp, agg, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static void write_bulk_callback(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct net_device_stats *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) struct tx_agg *agg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct r8152 *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) int status = urb->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) agg = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (!agg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) tp = agg->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (!tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) stats = &netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) netdev_warn(netdev, "Tx status %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) stats->tx_errors += agg->skb_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) stats->tx_packets += agg->skb_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) stats->tx_bytes += agg->skb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) spin_lock_irqsave(&tp->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) list_add_tail(&agg->list, &tp->tx_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) spin_unlock_irqrestore(&tp->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) usb_autopm_put_interface_async(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (!netif_carrier_ok(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (!test_bit(WORK_ENABLE, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (!skb_queue_empty(&tp->tx_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) tasklet_schedule(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static void intr_callback(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct r8152 *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) __le16 *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) int status = urb->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) tp = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (!tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (!test_bit(WORK_ENABLE, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) case 0: /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) case -ECONNRESET: /* unlink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) case -ESHUTDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) netif_device_detach(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) case -ENOENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) case -EPROTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) netif_info(tp, intr, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) "Stop submitting intr, status %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) case -EOVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) goto resubmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* -EPIPE: should clear the halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) goto resubmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) d = urb->transfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (INTR_LINK & __le16_to_cpu(d[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (!netif_carrier_ok(tp->netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) set_bit(RTL8152_LINK_CHG, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) schedule_delayed_work(&tp->schedule, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (netif_carrier_ok(tp->netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) netif_stop_queue(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) set_bit(RTL8152_LINK_CHG, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) schedule_delayed_work(&tp->schedule, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) resubmit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) res = usb_submit_urb(urb, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (res == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) rtl_set_unplug(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) netif_device_detach(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) } else if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) netif_err(tp, intr, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) "can't resubmit intr, status %d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static inline void *rx_agg_align(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static inline void *tx_agg_align(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) list_del(&agg->info_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) usb_free_urb(agg->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) put_page(agg->page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) kfree(agg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) atomic_dec(&tp->rx_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) unsigned int order = get_order(tp->rx_buf_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) struct rx_agg *rx_agg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (!rx_agg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (!rx_agg->page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) goto free_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) rx_agg->buffer = page_address(rx_agg->page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) rx_agg->urb = usb_alloc_urb(0, mflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (!rx_agg->urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) goto free_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) rx_agg->context = tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) INIT_LIST_HEAD(&rx_agg->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) INIT_LIST_HEAD(&rx_agg->info_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) list_add_tail(&rx_agg->info_list, &tp->rx_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) atomic_inc(&tp->rx_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return rx_agg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) free_buf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) __free_pages(rx_agg->page, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) free_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) kfree(rx_agg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static void free_all_mem(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) struct rx_agg *agg, *agg_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) free_rx_agg(tp, agg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) WARN_ON(atomic_read(&tp->rx_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) for (i = 0; i < RTL8152_MAX_TX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) usb_free_urb(tp->tx_info[i].urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) tp->tx_info[i].urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) kfree(tp->tx_info[i].buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) tp->tx_info[i].buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) tp->tx_info[i].head = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) usb_free_urb(tp->intr_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) tp->intr_urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) kfree(tp->intr_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) tp->intr_buff = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static int alloc_all_mem(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) struct usb_interface *intf = tp->intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) struct usb_host_interface *alt = intf->cur_altsetting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) int node, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) spin_lock_init(&tp->rx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) spin_lock_init(&tp->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) INIT_LIST_HEAD(&tp->rx_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) INIT_LIST_HEAD(&tp->tx_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) INIT_LIST_HEAD(&tp->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) skb_queue_head_init(&tp->tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) skb_queue_head_init(&tp->rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) atomic_set(&tp->rx_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) for (i = 0; i < RTL8152_MAX_RX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (!alloc_rx_agg(tp, GFP_KERNEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) for (i = 0; i < RTL8152_MAX_TX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (buf != tx_agg_align(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) urb = usb_alloc_urb(0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (!urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) INIT_LIST_HEAD(&tp->tx_info[i].list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) tp->tx_info[i].context = tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) tp->tx_info[i].urb = urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) tp->tx_info[i].buffer = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) tp->tx_info[i].head = tx_agg_align(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (!tp->intr_urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (!tp->intr_buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) tp->intr_interval = (int)ep_intr->desc.bInterval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) tp->intr_buff, INTBUFSIZE, intr_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) tp, tp->intr_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) free_all_mem(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) struct tx_agg *agg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (list_empty(&tp->tx_free))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) spin_lock_irqsave(&tp->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (!list_empty(&tp->tx_free)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) struct list_head *cursor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) cursor = tp->tx_free.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) list_del_init(cursor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) agg = list_entry(cursor, struct tx_agg, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) spin_unlock_irqrestore(&tp->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return agg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* r8152_csum_workaround()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * The hw limits the value of the transport offset. When the offset is out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * range, calculate the checksum by sw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) struct sk_buff_head *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (skb_shinfo(skb)->gso_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) netdev_features_t features = tp->netdev->features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) struct sk_buff *segs, *seg, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) struct sk_buff_head seg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) segs = skb_gso_segment(skb, features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (IS_ERR(segs) || !segs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) __skb_queue_head_init(&seg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) skb_list_walk_safe(segs, seg, next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) skb_mark_not_on_list(seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) __skb_queue_tail(&seg_list, seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) skb_queue_splice(&seg_list, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (skb_checksum_help(skb) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) __skb_queue_head(list, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct net_device_stats *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) drop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) stats = &tp->netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) stats->tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (skb_vlan_tag_present(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) u32 opts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) desc->opts2 |= cpu_to_le32(opts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) u32 opts2 = le32_to_cpu(desc->opts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (opts2 & RX_VLAN_TAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) swab16(opts2 & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct sk_buff *skb, u32 len, u32 transport_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) u32 mss = skb_shinfo(skb)->gso_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) u32 opts1, opts2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) int ret = TX_CSUM_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) WARN_ON_ONCE(len > TX_LEN_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) opts1 = len | TX_FS | TX_LS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (mss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) if (transport_offset > GTTCPHO_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) netif_warn(tp, tx_err, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) "Invalid transport offset 0x%x for TSO\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) transport_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ret = TX_CSUM_TSO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) goto unavailable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) switch (vlan_get_protocol(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) case htons(ETH_P_IP):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) opts1 |= GTSENDV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) case htons(ETH_P_IPV6):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (skb_cow_head(skb, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ret = TX_CSUM_TSO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) goto unavailable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) tcp_v6_gso_csum_prep(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) opts1 |= GTSENDV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) opts1 |= transport_offset << GTTCPHO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) u8 ip_protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (transport_offset > TCPHO_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) netif_warn(tp, tx_err, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) "Invalid transport offset 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) transport_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ret = TX_CSUM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) goto unavailable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) switch (vlan_get_protocol(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) case htons(ETH_P_IP):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) opts2 |= IPV4_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) ip_protocol = ip_hdr(skb)->protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) case htons(ETH_P_IPV6):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) opts2 |= IPV6_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ip_protocol = ipv6_hdr(skb)->nexthdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ip_protocol = IPPROTO_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (ip_protocol == IPPROTO_TCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) opts2 |= TCP_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) else if (ip_protocol == IPPROTO_UDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) opts2 |= UDP_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) opts2 |= transport_offset << TCPHO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) desc->opts2 = cpu_to_le32(opts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) desc->opts1 = cpu_to_le32(opts1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) unavailable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) int remain, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) u8 *tx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) __skb_queue_head_init(&skb_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) spin_lock(&tx_queue->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) skb_queue_splice_init(tx_queue, &skb_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) spin_unlock(&tx_queue->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) tx_data = agg->head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) agg->skb_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) agg->skb_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) remain = agg_buf_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) struct tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) skb = __skb_dequeue(&skb_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) len = skb->len + sizeof(*tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (len > remain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) __skb_queue_head(&skb_head, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) tx_data = tx_agg_align(tx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) tx_desc = (struct tx_desc *)tx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) offset = (u32)skb_transport_offset(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) r8152_csum_workaround(tp, skb, &skb_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) rtl_tx_vlan_tag(tx_desc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) tx_data += sizeof(*tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) struct net_device_stats *stats = &tp->netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) stats->tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) tx_data -= sizeof(*tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) tx_data += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) agg->skb_len += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (!skb_queue_empty(&skb_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) spin_lock(&tx_queue->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) skb_queue_splice(&skb_head, tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) spin_unlock(&tx_queue->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) netif_tx_lock(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) if (netif_queue_stopped(tp->netdev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) netif_wake_queue(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) netif_tx_unlock(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ret = usb_autopm_get_interface_async(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) goto out_tx_fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) agg->head, (int)(tx_data - (u8 *)agg->head),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) (usb_complete_t)write_bulk_callback, agg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) usb_autopm_put_interface_async(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) out_tx_fill:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) u8 checksum = CHECKSUM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) u32 opts2, opts3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (!(tp->netdev->features & NETIF_F_RXCSUM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) goto return_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) opts2 = le32_to_cpu(rx_desc->opts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) opts3 = le32_to_cpu(rx_desc->opts3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (opts2 & RD_IPV4_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if (opts3 & IPF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) checksum = CHECKSUM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) checksum = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) checksum = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) } else if (opts2 & RD_IPV6_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) checksum = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) checksum = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) return_result:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) return checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) static inline bool rx_count_exceed(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) static inline int agg_offset(struct rx_agg *agg, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) return (int)(addr - agg->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) struct rx_agg *agg, *agg_next, *agg_free = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) if (page_count(agg->page) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (!agg_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) list_del_init(&agg->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) agg_free = agg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) if (rx_count_exceed(tp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) list_del_init(&agg->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) free_rx_agg(tp, agg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) agg_free = alloc_rx_agg(tp, mflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return agg_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static int rx_bottom(struct r8152 *tp, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct list_head *cursor, *next, rx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) int ret = 0, work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct napi_struct *napi = &tp->napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) if (!skb_queue_empty(&tp->rx_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) while (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) struct net_device_stats *stats = &netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) unsigned int pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) pkt_len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) napi_gro_receive(napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) work_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) stats->rx_bytes += pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) if (list_empty(&tp->rx_done))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) INIT_LIST_HEAD(&rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) list_splice_init(&tp->rx_done, &rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) list_for_each_safe(cursor, next, &rx_queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) struct rx_desc *rx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) struct rx_agg *agg, *agg_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) int len_used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) u8 *rx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) list_del_init(cursor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) agg = list_entry(cursor, struct rx_agg, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) urb = agg->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (urb->actual_length < ETH_ZLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) goto submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) rx_desc = agg->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) rx_data = agg->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) len_used += sizeof(struct rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) while (urb->actual_length > len_used) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) struct net_device_stats *stats = &netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) unsigned int pkt_len, rx_frag_head_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) /* limite the skb numbers for rx_queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (pkt_len < ETH_ZLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) len_used += pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) if (urb->actual_length < len_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) pkt_len -= ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) rx_data += sizeof(struct rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (!agg_free || tp->rx_copybreak > pkt_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) rx_frag_head_sz = pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) rx_frag_head_sz = tp->rx_copybreak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) skb = napi_alloc_skb(napi, rx_frag_head_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) stats->rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) goto find_next_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) skb->ip_summed = r8152_rx_csum(tp, rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) memcpy(skb->data, rx_data, rx_frag_head_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) skb_put(skb, rx_frag_head_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) pkt_len -= rx_frag_head_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) rx_data += rx_frag_head_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) if (pkt_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) skb_add_rx_frag(skb, 0, agg->page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) agg_offset(agg, rx_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) pkt_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) SKB_DATA_ALIGN(pkt_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) get_page(agg->page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) skb->protocol = eth_type_trans(skb, netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) rtl_rx_vlan_tag(rx_desc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) if (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) work_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) stats->rx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) napi_gro_receive(napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) __skb_queue_tail(&tp->rx_queue, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) find_next_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) rx_desc = (struct rx_desc *)rx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) len_used = agg_offset(agg, rx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) len_used += sizeof(struct rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) WARN_ON(!agg_free && page_count(agg->page) > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) if (agg_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) if (page_count(agg->page) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) list_add(&agg_free->list, &tp->rx_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) list_add_tail(&agg->list, &tp->rx_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) agg = agg_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) urb = agg->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) submit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) list_add_tail(&agg->list, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) if (!list_empty(&rx_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) list_splice_tail(&rx_queue, &tp->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static void tx_bottom(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) struct tx_agg *agg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (skb_queue_empty(&tp->tx_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) agg = r8152_get_tx_agg(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) if (!agg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) res = r8152_tx_agg_fill(tp, agg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (res == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) rtl_set_unplug(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) netif_device_detach(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) struct net_device_stats *stats = &netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) netif_warn(tp, tx_err, netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) "failed tx_urb %d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) stats->tx_dropped += agg->skb_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) spin_lock_irqsave(&tp->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) list_add_tail(&agg->list, &tp->tx_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) spin_unlock_irqrestore(&tp->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) } while (res == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static void bottom_half(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) struct r8152 *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) tp = (struct r8152 *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (!test_bit(WORK_ENABLE, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) /* When link down, the driver would cancel all bulks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) /* This avoid the re-submitting bulk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (!netif_carrier_ok(tp->netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) clear_bit(SCHEDULE_TASKLET, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) tx_bottom(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static int r8152_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) struct r8152 *tp = container_of(napi, struct r8152, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) int work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) work_done = rx_bottom(tp, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) if (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) if (!napi_complete_done(napi, work_done))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) if (!list_empty(&tp->rx_done))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) napi_schedule(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* The rx would be stopped, so skip submitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) agg->buffer, tp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) (usb_complete_t)read_bulk_callback, agg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) ret = usb_submit_urb(agg->urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (ret == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) rtl_set_unplug(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) netif_device_detach(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) } else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) struct urb *urb = agg->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) list_add_tail(&agg->list, &tp->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) netif_err(tp, rx_err, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) "Couldn't submit rx[%p], ret = %d\n", agg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) napi_schedule(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static void rtl_drop_queued_tx(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) struct net_device_stats *stats = &tp->netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) if (skb_queue_empty(tx_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) __skb_queue_head_init(&skb_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) spin_lock_bh(&tx_queue->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) skb_queue_splice_init(tx_queue, &skb_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) spin_unlock_bh(&tx_queue->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) while ((skb = __skb_dequeue(&skb_head))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) stats->tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) netif_warn(tp, tx_err, netdev, "Tx timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) usb_queue_reset_device(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static void rtl8152_set_rx_mode(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) if (netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) set_bit(RTL8152_SET_RX_MODE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) schedule_delayed_work(&tp->schedule, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) static void _rtl8152_set_rx_mode(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) u32 mc_filter[2]; /* Multicast hash filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) __le32 tmp[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) netif_stop_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) ocp_data &= ~RCR_ACPT_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ocp_data |= RCR_AB | RCR_APM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) if (netdev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) /* Unconditionally log net taps. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) ocp_data |= RCR_AM | RCR_AAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) mc_filter[1] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) mc_filter[0] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) (netdev->flags & IFF_ALLMULTI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /* Too many to filter perfectly -- accept all multicasts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) ocp_data |= RCR_AM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) mc_filter[1] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) mc_filter[0] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) mc_filter[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) mc_filter[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) netdev_for_each_mc_addr(ha, netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) ocp_data |= RCR_AM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) netif_wake_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) static netdev_features_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) netdev_features_t features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) u32 mss = skb_shinfo(skb)->gso_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) int offset = skb_transport_offset(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) features &= ~NETIF_F_GSO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) return features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) skb_tx_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) skb_queue_tail(&tp->tx_queue, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (!list_empty(&tp->tx_free)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) set_bit(SCHEDULE_TASKLET, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) schedule_delayed_work(&tp->schedule, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) usb_mark_last_busy(tp->udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) tasklet_schedule(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) netif_stop_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static void r8152b_reset_packet_filter(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) ocp_data &= ~FMC_FCR_MCU_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) ocp_data |= FMC_FCR_MCU_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) static void rtl8152_nic_reset(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) usleep_range(100, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static void set_tx_qlen(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) sizeof(struct tx_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) static inline u8 rtl8152_get_speed(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) static void rtl_set_eee_plus(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) u8 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) speed = rtl8152_get_speed(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if (speed & _10bps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) ocp_data |= EEEP_CR_EEEP_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) ocp_data &= ~EEEP_CR_EEEP_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) static void rxdy_gated_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) ocp_data |= RXDY_GATED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) ocp_data &= ~RXDY_GATED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) static int rtl_start_rx(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) struct rx_agg *agg, *agg_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) struct list_head tmp_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) int ret = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) INIT_LIST_HEAD(&tmp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) INIT_LIST_HEAD(&tp->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) INIT_LIST_HEAD(&tp->rx_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) list_splice_init(&tp->rx_info, &tmp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) INIT_LIST_HEAD(&agg->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) if (++i > RTL8152_MAX_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) list_add_tail(&agg->list, &tp->rx_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) } else if (unlikely(ret < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) list_add_tail(&agg->list, &tp->rx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) WARN_ON(!list_empty(&tp->rx_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) list_splice(&tmp_list, &tp->rx_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) static int rtl_stop_rx(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) struct rx_agg *agg, *agg_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) struct list_head tmp_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) INIT_LIST_HEAD(&tmp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) /* The usb_kill_urb() couldn't be used in atomic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) * Therefore, move the list of rx_info to a tmp one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) * Then, list_for_each_entry_safe could be used without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) * spin lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) list_splice_init(&tp->rx_info, &tmp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* At least RTL8152_MAX_RX rx_agg have the page_count being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) * equal to 1, so the other ones could be freed safely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) if (page_count(agg->page) > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) free_rx_agg(tp, agg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) usb_kill_urb(agg->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) /* Move back the list of temp to the rx_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) spin_lock_irqsave(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) WARN_ON(!list_empty(&tp->rx_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) list_splice(&tmp_list, &tp->rx_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) spin_unlock_irqrestore(&tp->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) while (!skb_queue_empty(&tp->rx_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) OWN_UPDATE | OWN_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) static int rtl_enable(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) r8152b_reset_packet_filter(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) ocp_data |= CR_RE | CR_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) r8153b_rx_agg_chg_indicate(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) rxdy_gated_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) static int rtl8152_enable(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) set_tx_qlen(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) rtl_set_eee_plus(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) return rtl_enable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) static void r8153_set_rx_early_timeout(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) u32 ocp_data = tp->coalesce / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) 128 / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) static void r8153_set_rx_early_size(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) ocp_data / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) ocp_data / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) static int rtl8153_enable(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) set_tx_qlen(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) rtl_set_eee_plus(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) r8153_set_rx_early_timeout(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) r8153_set_rx_early_size(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) if (tp->version == RTL_VER_09) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) ocp_data &= ~FC_PATCH_TASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) ocp_data |= FC_PATCH_TASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) return rtl_enable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) static void rtl_disable(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) rtl_drop_queued_tx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) ocp_data &= ~RCR_ACPT_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) rtl_drop_queued_tx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) for (i = 0; i < RTL8152_MAX_TX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) usb_kill_urb(tp->tx_info[i].urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) rxdy_gated_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) rtl_stop_rx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) rtl8152_nic_reset(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) static void r8152_power_cut_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) ocp_data |= POWER_CUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) ocp_data &= ~POWER_CUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) ocp_data &= ~RESUME_INDICATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) ocp_data |= CPCR_RX_VLAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) ocp_data &= ~CPCR_RX_VLAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static int rtl8152_set_features(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) netdev_features_t features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) netdev_features_t changed = features ^ dev->features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) if (features & NETIF_F_HW_VLAN_CTAG_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) rtl_rx_vlan_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) rtl_rx_vlan_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) static u32 __rtl_get_wol(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) u32 wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) if (ocp_data & LINK_ON_WAKE_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) wolopts |= WAKE_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) if (ocp_data & UWF_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) wolopts |= WAKE_UCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) if (ocp_data & BWF_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) wolopts |= WAKE_BCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) if (ocp_data & MWF_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) wolopts |= WAKE_MCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) if (ocp_data & MAGIC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) wolopts |= WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) return wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) ocp_data &= ~LINK_ON_WAKE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) if (wolopts & WAKE_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) ocp_data |= LINK_ON_WAKE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) if (wolopts & WAKE_UCAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) ocp_data |= UWF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) if (wolopts & WAKE_BCAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) ocp_data |= BWF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) if (wolopts & WAKE_MCAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) ocp_data |= MWF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) ocp_data &= ~MAGIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) if (wolopts & WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) ocp_data |= MAGIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) if (wolopts & WAKE_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) device_set_wakeup_enable(&tp->udev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) device_set_wakeup_enable(&tp->udev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) static void r8153_u1u2en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) u8 u1u2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) memset(u1u2, 0xff, sizeof(u1u2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) memset(u1u2, 0x00, sizeof(u1u2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) static void r8153b_u1u2en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) ocp_data |= LPM_U1U2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) ocp_data &= ~LPM_U1U2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) static void r8153_u2p3en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) ocp_data |= U2P3_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) ocp_data &= ~U2P3_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) static void r8153b_ups_flags(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) u32 ups_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) if (tp->ups_info.green)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) ups_flags |= UPS_FLAGS_EN_GREEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) if (tp->ups_info.aldps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) ups_flags |= UPS_FLAGS_EN_ALDPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) if (tp->ups_info.eee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) ups_flags |= UPS_FLAGS_EN_EEE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) if (tp->ups_info.flow_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) if (tp->ups_info.eee_ckdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) if (tp->ups_info.eee_cmod_lv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) if (tp->ups_info._10m_ckdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) if (tp->ups_info.eee_plloff_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) if (tp->ups_info.eee_plloff_giga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) if (tp->ups_info._250m_ckdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) ups_flags |= UPS_FLAGS_250M_CKDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (tp->ups_info.ctap_short_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) switch (tp->ups_info.speed_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) case NWAY_10M_HALF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) ups_flags |= ups_flags_speed(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) case NWAY_10M_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) ups_flags |= ups_flags_speed(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) case NWAY_100M_HALF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) ups_flags |= ups_flags_speed(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) case NWAY_100M_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) ups_flags |= ups_flags_speed(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) case NWAY_1000M_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) ups_flags |= ups_flags_speed(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) case FORCE_10M_HALF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) ups_flags |= ups_flags_speed(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) case FORCE_10M_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) ups_flags |= ups_flags_speed(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) case FORCE_100M_HALF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) ups_flags |= ups_flags_speed(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) case FORCE_100M_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) ups_flags |= ups_flags_speed(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) static void r8153b_green_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) data = sram_read(tp, SRAM_GREEN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) data |= GREEN_ETH_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) sram_write(tp, SRAM_GREEN_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) tp->ups_info.green = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) for (i = 0; i < 500; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) data = ocp_reg_read(tp, OCP_PHY_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) data &= PHY_STAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) if (desired) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) if (data == desired)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) data == PHY_STAT_EXT_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) static void r8153b_ups_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) r8153b_ups_flags(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) ocp_data |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) ocp_data &= ~(UPS_EN | USP_PREWAKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) ocp_data &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) ocp_data &= ~PCUT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) data = r8153_phy_status(tp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) switch (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) case PHY_STAT_PWRDN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) case PHY_STAT_EXT_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) r8153b_green_en(tp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) test_bit(GREEN_ETHERNET, &tp->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) data = r8152_mdio_read(tp, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) data &= ~BMCR_PDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) data |= BMCR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) r8152_mdio_write(tp, MII_BMCR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) if (data != PHY_STAT_LAN_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) netif_warn(tp, link, tp->netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) "PHY not ready");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) static void r8153_power_cut_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) ocp_data |= PWR_EN | PHASE2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) ocp_data &= ~(PWR_EN | PHASE2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) ocp_data &= ~PCUT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) ocp_data |= PWR_EN | PHASE2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) ocp_data &= ~PWR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) ocp_data &= ~PCUT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) static void r8153_queue_wake(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) ocp_data |= UPCOMING_RUNTIME_D3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) ocp_data &= ~UPCOMING_RUNTIME_D3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) ocp_data &= ~LINK_CHG_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) ocp_data &= ~LINK_CHANGE_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) static bool rtl_can_wakeup(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) struct usb_device *udev = tp->udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) __rtl_set_wol(tp, WAKE_ANY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) ocp_data |= LINK_OFF_WAKE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) __rtl_set_wol(tp, tp->saved_wolopts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) ocp_data &= ~LINK_OFF_WAKE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) r8153_u1u2en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) r8153_u2p3en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) rtl_runtime_suspend_enable(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) rtl_runtime_suspend_enable(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) r8153_u2p3en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) r8153_u1u2en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) r8153_queue_wake(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) r8153b_u1u2en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) r8153_u2p3en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) rtl_runtime_suspend_enable(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) r8153b_ups_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) r8153b_ups_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) r8153_queue_wake(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) rtl_runtime_suspend_enable(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) if (tp->udev->speed != USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) r8153b_u1u2en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) static void r8153_teredo_off(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) OOB_TEREDO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) /* The bit 0 ~ 7 are relative with teredo settings. They are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) * W1C (write 1 to clear), so set all 1 to disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) static void rtl_reset_bmu(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) /* Clear the bp to stop the firmware before loading a new one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) static void rtl_clear_bp(struct r8152 *tp, u16 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) ocp_write_byte(tp, type, PLA_BP_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) if (type == MCU_TYPE_USB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) ocp_write_word(tp, type, PLA_BP_0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) ocp_write_word(tp, type, PLA_BP_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) ocp_write_word(tp, type, PLA_BP_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) ocp_write_word(tp, type, PLA_BP_3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) ocp_write_word(tp, type, PLA_BP_4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) ocp_write_word(tp, type, PLA_BP_5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) ocp_write_word(tp, type, PLA_BP_6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) ocp_write_word(tp, type, PLA_BP_7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) /* wait 3 ms to make sure the firmware is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) usleep_range(3000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) ocp_write_word(tp, type, PLA_BP_BA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) static int r8153_patch_request(struct r8152 *tp, bool request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) if (request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) data |= PATCH_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) data &= ~PATCH_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) for (i = 0; request && i < 5000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) netif_err(tp, drv, tp->netdev, "patch request fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) r8153_patch_request(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) if (r8153_patch_request(tp, true)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) dev_err(&tp->intf->dev, "patch request fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) sram_write(tp, key_addr, patch_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) sram_write(tp, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) data = ocp_reg_read(tp, OCP_PHY_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) data &= ~PATCH_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) ocp_reg_write(tp, OCP_PHY_LOCK, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) sram_write(tp, key_addr, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) r8153_patch_request(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) bool rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) fw_reg = 0xa014;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) ba_reg = 0xa012;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) patch_en_addr = 0xa01a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) mode_reg = 0xb820;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) bp_start = 0xa000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) fw_offset = __le16_to_cpu(phy->fw_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) if (fw_offset < sizeof(*phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) dev_err(&tp->intf->dev, "fw_offset too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) length = __le32_to_cpu(phy->blk_hdr.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) if (length < fw_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) dev_err(&tp->intf->dev, "invalid fw_offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) length -= __le16_to_cpu(phy->fw_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) if (!length || (length & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) dev_err(&tp->intf->dev, "invalid block length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) dev_err(&tp->intf->dev, "invalid register to load firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) dev_err(&tp->intf->dev, "invalid base address register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) "invalid patch mode enabled register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) "invalid register to switch the mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) if (__le16_to_cpu(phy->bp_start) != bp_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) "invalid start register of break point\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) if (__le16_to_cpu(phy->bp_num) > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) dev_err(&tp->intf->dev, "invalid break point number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) rc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) bool rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) u32 length, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) int i, max_bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) type = __le32_to_cpu(mac->blk_hdr.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) if (type == RTL_FW_PLA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) fw_reg = 0xf800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) bp_ba_addr = PLA_BP_BA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) bp_en_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) bp_start = PLA_BP_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) max_bp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) fw_reg = 0xf800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) bp_ba_addr = PLA_BP_BA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) bp_en_addr = PLA_BP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) bp_start = PLA_BP_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) max_bp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) } else if (type == RTL_FW_USB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) fw_reg = 0xf800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) bp_ba_addr = USB_BP_BA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) bp_en_addr = USB_BP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) bp_start = USB_BP_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) max_bp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) fw_reg = 0xe600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) bp_ba_addr = USB_BP_BA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) bp_en_addr = USB_BP2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) bp_start = USB_BP_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) max_bp = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) fw_offset = __le16_to_cpu(mac->fw_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) if (fw_offset < sizeof(*mac)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) dev_err(&tp->intf->dev, "fw_offset too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) length = __le32_to_cpu(mac->blk_hdr.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) if (length < fw_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) dev_err(&tp->intf->dev, "invalid fw_offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) length -= fw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) if (length < 4 || (length & 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) dev_err(&tp->intf->dev, "invalid block length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) dev_err(&tp->intf->dev, "invalid register to load firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) dev_err(&tp->intf->dev, "invalid base address register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) dev_err(&tp->intf->dev, "invalid enabled mask register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) if (__le16_to_cpu(mac->bp_start) != bp_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) "invalid start register of break point\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) if (__le16_to_cpu(mac->bp_num) > max_bp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) dev_err(&tp->intf->dev, "invalid break point number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) if (mac->bp[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) rc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) /* Verify the checksum for the firmware file. It is calculated from the version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) * field to the end of the file. Compare the result with the checksum field to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) * make sure the file is correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) static long rtl8152_fw_verify_checksum(struct r8152 *tp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) struct fw_header *fw_hdr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) unsigned char checksum[sizeof(fw_hdr->checksum)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) struct crypto_shash *alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) struct shash_desc *sdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) alg = crypto_alloc_shash("sha256", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) if (IS_ERR(alg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) rc = PTR_ERR(alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) crypto_shash_digestsize(alg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) goto free_shash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) len = sizeof(*sdesc) + crypto_shash_descsize(alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) sdesc = kmalloc(len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) if (!sdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) goto free_shash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) sdesc->tfm = alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) len = size - sizeof(fw_hdr->checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) kfree(sdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) goto free_shash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) dev_err(&tp->intf->dev, "checksum fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) free_shash:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) crypto_free_shash(alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) const struct firmware *fw = rtl_fw->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) struct fw_header *fw_hdr = (struct fw_header *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) struct fw_mac *pla = NULL, *usb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) struct fw_phy_patch_key *start = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) struct fw_phy_nc *phy_nc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) struct fw_block *stop = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) long ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) if (fw->size < sizeof(*fw_hdr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) dev_err(&tp->intf->dev, "file too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) for (i = sizeof(*fw_hdr); i < fw->size;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) struct fw_block *block = (struct fw_block *)&fw->data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) if ((i + sizeof(*block)) > fw->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) type = __le32_to_cpu(block->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) case RTL_FW_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) if (__le32_to_cpu(block->length) != sizeof(*block))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) goto fw_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) case RTL_FW_PLA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) if (pla) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) "multiple PLA firmware encountered");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) pla = (struct fw_mac *)block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) if (!rtl8152_is_fw_mac_ok(tp, pla)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) "check PLA firmware failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) case RTL_FW_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) if (usb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) "multiple USB firmware encountered");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) usb = (struct fw_mac *)block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) if (!rtl8152_is_fw_mac_ok(tp, usb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) "check USB firmware failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) case RTL_FW_PHY_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) if (start || phy_nc || stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) "check PHY_START fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) if (__le32_to_cpu(block->length) != sizeof(*start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) "Invalid length for PHY_START\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) start = (struct fw_phy_patch_key *)block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) case RTL_FW_PHY_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) if (stop || !start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) "Check PHY_STOP fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) if (__le32_to_cpu(block->length) != sizeof(*block)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) "Invalid length for PHY_STOP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) stop = block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) case RTL_FW_PHY_NC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) if (!start || stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) "check PHY_NC fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) if (phy_nc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) "multiple PHY NC encountered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) phy_nc = (struct fw_phy_nc *)block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) dev_err(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) "check PHY NC firmware failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) /* next block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) i += ALIGN(__le32_to_cpu(block->length), 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) fw_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) if ((phy_nc || start) && !stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) dev_err(&tp->intf->dev, "without PHY_STOP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) u16 mode_reg, bp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) u32 length, i, num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) __le16 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) mode_reg = __le16_to_cpu(phy->mode_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) sram_write(tp, __le16_to_cpu(phy->ba_reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) __le16_to_cpu(phy->ba_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) length = __le32_to_cpu(phy->blk_hdr.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) length -= __le16_to_cpu(phy->fw_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) num = length / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) __le16_to_cpu(phy->patch_en_value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) bp_index = __le16_to_cpu(phy->bp_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) num = __le16_to_cpu(phy->bp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) bp_index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) switch (__le32_to_cpu(mac->blk_hdr.type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) case RTL_FW_PLA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) type = MCU_TYPE_PLA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) case RTL_FW_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) type = MCU_TYPE_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) rtl_clear_bp(tp, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) /* Enable backup/restore of MACDBG. This is required after clearing PLA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) * break points and before applying the PLA firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) length = __le32_to_cpu(mac->blk_hdr.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) length -= __le16_to_cpu(mac->fw_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) data = (u8 *)mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) data += __le16_to_cpu(mac->fw_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) __le16_to_cpu(mac->bp_ba_value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) bp_index = __le16_to_cpu(mac->bp_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) bp_num = __le16_to_cpu(mac->bp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) for (i = 0; i < bp_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) bp_index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) if (bp_en_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) ocp_write_word(tp, type, bp_en_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) __le16_to_cpu(mac->bp_en_value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) if (fw_ver_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) mac->fw_ver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) static void rtl8152_apply_firmware(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) struct rtl_fw *rtl_fw = &tp->rtl_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) struct fw_header *fw_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) struct fw_phy_patch_key *key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) u16 key_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) if (IS_ERR_OR_NULL(rtl_fw->fw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) fw = rtl_fw->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) fw_hdr = (struct fw_header *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) if (rtl_fw->pre_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) rtl_fw->pre_fw(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) struct fw_block *block = (struct fw_block *)&fw->data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) switch (__le32_to_cpu(block->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) case RTL_FW_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) goto post_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) case RTL_FW_PLA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) case RTL_FW_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) case RTL_FW_PHY_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) key = (struct fw_phy_patch_key *)block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) key_addr = __le16_to_cpu(key->key_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) r8153_pre_ram_code(tp, key_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) __le16_to_cpu(key->key_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) case RTL_FW_PHY_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) WARN_ON(!key_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) r8153_post_ram_code(tp, key_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) case RTL_FW_PHY_NC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) i += ALIGN(__le32_to_cpu(block->length), 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) post_fw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) if (rtl_fw->post_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) rtl_fw->post_fw(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) static void rtl8152_release_firmware(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) struct rtl_fw *rtl_fw = &tp->rtl_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) release_firmware(rtl_fw->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) rtl_fw->fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) static int rtl8152_request_firmware(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) struct rtl_fw *rtl_fw = &tp->rtl_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) if (rtl_fw->fw || !rtl_fw->fw_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) dev_info(&tp->intf->dev, "skip request firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) goto result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) goto result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) rc = rtl8152_check_firmware(tp, rtl_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) release_firmware(rtl_fw->fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) result:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) rtl_fw->fw = ERR_PTR(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) dev_warn(&tp->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) "unable to load firmware patch %s (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) rtl_fw->fw_name, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) static void r8152_aldps_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) LINKENA | DIS_SDSAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) DIS_SDSAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) ocp_reg_write(tp, OCP_EEE_DATA, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) r8152_mmd_indirect(tp, dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) data = ocp_reg_read(tp, OCP_EEE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) r8152_mmd_indirect(tp, dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) ocp_reg_write(tp, OCP_EEE_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) static void r8152_eee_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) u16 config1, config2, config3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) ocp_data |= EEE_RX_EN | EEE_TX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) config1 |= sd_rise_time(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) config3 |= fast_snr(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) RX_QUIET_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) config1 |= sd_rise_time(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) config3 |= fast_snr(511);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) static void r8153_eee_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) u16 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) config = ocp_reg_read(tp, OCP_EEE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) ocp_data |= EEE_RX_EN | EEE_TX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) config |= EEE10_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) config &= ~EEE10_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) ocp_reg_write(tp, OCP_EEE_CFG, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) tp->ups_info.eee = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) static void rtl_eee_enable(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) r8152_eee_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) tp->eee_adv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) r8152_eee_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) r8153_eee_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) r8153_eee_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) ocp_reg_write(tp, OCP_EEE_ADV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) static void r8152b_enable_fc(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) u16 anar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) anar = r8152_mdio_read(tp, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) r8152_mdio_write(tp, MII_ADVERTISE, anar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) tp->ups_info.flow_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) static void rtl8152_disable(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) r8152_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) rtl_disable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) r8152_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) static void r8152b_hw_phy_cfg(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) rtl8152_apply_firmware(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) rtl_eee_enable(tp, tp->eee_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) r8152_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) r8152b_enable_fc(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) set_bit(PHY_RESET, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) static void wait_oob_link_list_ready(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) if (ocp_data & LINK_LIST_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) static void r8152b_exit_oob(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) ocp_data &= ~RCR_ACPT_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) rxdy_gated_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) r8153_teredo_off(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) ocp_data &= ~NOW_IS_OOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) ocp_data &= ~MCU_BORW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) wait_oob_link_list_ready(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) ocp_data |= RE_INIT_LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) wait_oob_link_list_ready(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) rtl8152_nic_reset(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) /* rx share fifo credit full threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) if (tp->udev->speed == USB_SPEED_FULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) tp->udev->speed == USB_SPEED_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) /* rx share fifo credit near full threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) RXFIFO_THR2_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) RXFIFO_THR3_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) /* rx share fifo credit near full threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) RXFIFO_THR2_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) RXFIFO_THR3_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) /* TX share fifo free credit full threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) ocp_data |= TCR0_AUTO_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) static void r8152b_enter_oob(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) ocp_data &= ~NOW_IS_OOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) rtl_disable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) wait_oob_link_list_ready(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) ocp_data |= RE_INIT_LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) wait_oob_link_list_ready(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) rtl_rx_vlan_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) ocp_data |= ALDPS_PROXY_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) rxdy_gated_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) ocp_data |= RCR_APM | RCR_AM | RCR_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) static int r8153_pre_firmware_1(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) /* Wait till the WTD timer is ready. It would take at most 104 ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) for (i = 0; i < 104; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) if (!(ocp_data & WTD1_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) static int r8153_post_firmware_1(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) /* set USB_BP_4 to support USB_SPEED_SUPER only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) /* reset UPHY timer to 36 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) static int r8153_pre_firmware_2(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) r8153_pre_firmware_1(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) ocp_data &= ~FW_FIX_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) static int r8153_post_firmware_2(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) /* enable bp0 if support USB_SPEED_SUPER only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) ocp_data |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) /* reset UPHY timer to 36 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) /* enable U3P3 check, set the counter to 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) ocp_data |= FW_FIX_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) static int r8153_post_firmware_3(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) ocp_data |= FW_IP_RESET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) static int r8153b_pre_firmware_1(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) /* enable fc timer and set timer to 1 second. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) CTRL_TIMER_EN | (1000 / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) static int r8153b_post_firmware_1(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) /* enable bp0 for RTL8153-BND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) if (ocp_data & BND_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) ocp_data |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) ocp_data |= FLOW_CTRL_PATCH_OPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) ocp_data |= FC_PATCH_TASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) ocp_data |= FW_IP_RESET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) static void r8153_aldps_en(struct r8152 *tp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) data = ocp_reg_read(tp, OCP_POWER_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) data |= EN_ALDPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) ocp_reg_write(tp, OCP_POWER_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) data &= ~EN_ALDPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) ocp_reg_write(tp, OCP_POWER_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) tp->ups_info.aldps = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) static void r8153_hw_phy_cfg(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) /* disable ALDPS before updating the PHY parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) r8153_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) /* disable EEE before updating the PHY parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) rtl_eee_enable(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) rtl8152_apply_firmware(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) if (tp->version == RTL_VER_03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) data = ocp_reg_read(tp, OCP_EEE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) data &= ~CTAP_SHORT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) ocp_reg_write(tp, OCP_EEE_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) data = ocp_reg_read(tp, OCP_POWER_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) data |= EEE_CLKDIV_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) ocp_reg_write(tp, OCP_POWER_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) data = ocp_reg_read(tp, OCP_DOWN_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) data |= EN_10M_BGOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) ocp_reg_write(tp, OCP_DOWN_SPEED, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) data = ocp_reg_read(tp, OCP_POWER_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) data |= EN_10M_PLLOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) ocp_reg_write(tp, OCP_POWER_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) ocp_data |= PFM_PWM_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) /* Enable LPF corner auto tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) sram_write(tp, SRAM_LPF_CFG, 0xf70f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) /* Adjust 10M Amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) sram_write(tp, SRAM_10M_AMP1, 0x00af);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) sram_write(tp, SRAM_10M_AMP2, 0x0208);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) if (tp->eee_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) rtl_eee_enable(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) r8153_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) r8152b_enable_fc(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) r8153_u2p3en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) set_bit(PHY_RESET, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) return ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) static void r8153b_hw_phy_cfg(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) /* disable ALDPS before updating the PHY parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) r8153_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) /* disable EEE before updating the PHY parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) rtl_eee_enable(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) rtl8152_apply_firmware(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) data = sram_read(tp, SRAM_GREEN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) data |= R_TUNE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) sram_write(tp, SRAM_GREEN_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) data = ocp_reg_read(tp, OCP_NCTL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) data |= PGA_RETURN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) ocp_reg_write(tp, OCP_NCTL_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) /* ADC Bias Calibration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) * bit (bit3) to rebuild the real 16-bit data. Write the data to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) * ADC ioffset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) ocp_data = r8152_efuse_read(tp, 0x7d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) if (data != 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) /* ups mode tx-link-pulse timing adjustment:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) ocp_data = ocp_reg_read(tp, 0xc426);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) ocp_data &= 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) if (ocp_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) u32 swr_cnt_1ms_ini;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) ocp_data |= PFM_PWM_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) /* Advnace EEE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) if (!r8153_patch_request(tp, true)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) data = ocp_reg_read(tp, OCP_POWER_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) data |= EEE_CLKDIV_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) ocp_reg_write(tp, OCP_POWER_CFG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) tp->ups_info.eee_ckdiv = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) data = ocp_reg_read(tp, OCP_DOWN_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) ocp_reg_write(tp, OCP_DOWN_SPEED, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) tp->ups_info.eee_cmod_lv = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) tp->ups_info._10m_ckdiv = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) tp->ups_info.eee_plloff_giga = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) tp->ups_info._250m_ckdiv = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) r8153_patch_request(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) if (tp->eee_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) rtl_eee_enable(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) r8153_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) r8152b_enable_fc(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) set_bit(PHY_RESET, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) static void r8153_first_init(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) rxdy_gated_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) r8153_teredo_off(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) ocp_data &= ~RCR_ACPT_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) rtl8152_nic_reset(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) rtl_reset_bmu(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) ocp_data &= ~NOW_IS_OOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) ocp_data &= ~MCU_BORW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) wait_oob_link_list_ready(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) ocp_data |= RE_INIT_LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) wait_oob_link_list_ready(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) ocp_data |= TCR0_AUTO_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) rtl8152_nic_reset(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) /* rx share fifo credit full threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) /* TX share fifo free credit full threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) static void r8153_enter_oob(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) ocp_data &= ~NOW_IS_OOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) rtl_disable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) rtl_reset_bmu(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) wait_oob_link_list_ready(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) ocp_data |= RE_INIT_LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) wait_oob_link_list_ready(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) ocp_data &= ~TEREDO_WAKE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) /* Clear teredo wake event. bit[15:8] is the teredo wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) * type. Set it to zero. bits[7:0] are the W1C bits about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) * the events. Set them to all 1 to clear them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) rtl_rx_vlan_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) ocp_data |= ALDPS_PROXY_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) rxdy_gated_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) ocp_data |= RCR_APM | RCR_AM | RCR_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) static void rtl8153_disable(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) r8153_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) rtl_disable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) rtl_reset_bmu(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) r8153_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) u32 advertising)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) u16 bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) if (autoneg == AUTONEG_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) bmcr = BMCR_SPEED10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) if (duplex == DUPLEX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) bmcr |= BMCR_FULLDPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) tp->ups_info.speed_duplex = FORCE_10M_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) tp->ups_info.speed_duplex = FORCE_10M_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) bmcr = BMCR_SPEED100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) if (duplex == DUPLEX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) bmcr |= BMCR_FULLDPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) tp->ups_info.speed_duplex = FORCE_100M_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) tp->ups_info.speed_duplex = FORCE_100M_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) if (tp->mii.supports_gmii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) tp->ups_info.speed_duplex = NWAY_1000M_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) if (duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) tp->mii.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) tp->mii.full_duplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) tp->mii.force_media = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) u16 anar, tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) u32 support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) if (tp->mii.supports_gmii)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) support |= RTL_ADVERTISED_1000_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) if (!(advertising & support))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) anar = r8152_mdio_read(tp, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) ADVERTISE_100HALF | ADVERTISE_100FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) if (advertising & RTL_ADVERTISED_10_HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) tmp1 |= ADVERTISE_10HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) tp->ups_info.speed_duplex = NWAY_10M_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) if (advertising & RTL_ADVERTISED_10_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) tmp1 |= ADVERTISE_10FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) tp->ups_info.speed_duplex = NWAY_10M_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) if (advertising & RTL_ADVERTISED_100_HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) tmp1 |= ADVERTISE_100HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) tp->ups_info.speed_duplex = NWAY_100M_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) if (advertising & RTL_ADVERTISED_100_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) tmp1 |= ADVERTISE_100FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) tp->ups_info.speed_duplex = NWAY_100M_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) if (anar != tmp1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) tp->mii.advertising = tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) if (tp->mii.supports_gmii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) u16 gbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) gbcr = r8152_mdio_read(tp, MII_CTRL1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) tmp1 = gbcr & ~(ADVERTISE_1000FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) ADVERTISE_1000HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) if (advertising & RTL_ADVERTISED_1000_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) tmp1 |= ADVERTISE_1000FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) tp->ups_info.speed_duplex = NWAY_1000M_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) if (gbcr != tmp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) r8152_mdio_write(tp, MII_CTRL1000, tmp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) tp->mii.force_media = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) if (test_and_clear_bit(PHY_RESET, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) bmcr |= BMCR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) r8152_mdio_write(tp, MII_BMCR, bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) if (bmcr & BMCR_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) static void rtl8152_up(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) r8152_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) r8152b_exit_oob(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) r8152_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) static void rtl8152_down(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) rtl_drop_queued_tx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) r8152_power_cut_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) r8152_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) r8152b_enter_oob(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) r8152_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) static void rtl8153_up(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) r8153_u1u2en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) r8153_u2p3en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) r8153_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) r8153_first_init(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) ocp_data |= LANWAKE_CLR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) ocp_data &= ~LANWAKE_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) ocp_data &= ~DELAY_PHY_PWR_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) r8153_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) r8153_u2p3en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) r8153_u1u2en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) static void rtl8153_down(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) rtl_drop_queued_tx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) ocp_data &= ~LANWAKE_CLR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) r8153_u1u2en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) r8153_u2p3en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) r8153_power_cut_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) r8153_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) r8153_enter_oob(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) r8153_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) static void rtl8153b_up(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) r8153b_u1u2en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) r8153_u2p3en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) r8153_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) r8153_first_init(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) ocp_data &= ~PLA_MCU_SPDWN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) r8153_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) if (tp->udev->speed != USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) r8153b_u1u2en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) static void rtl8153b_down(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) rtl_drop_queued_tx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) ocp_data |= PLA_MCU_SPDWN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) r8153b_u1u2en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) r8153_u2p3en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) r8153b_power_cut_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) r8153_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) r8153_enter_oob(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) r8153_aldps_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) static bool rtl8152_in_nway(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) u16 nway_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) tp->ocp_base = 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) if (nway_state & 0xc000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) static bool rtl8153_in_nway(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) static void set_carrier(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) struct napi_struct *napi = &tp->napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) u8 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) speed = rtl8152_get_speed(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) if (speed & LINK_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) if (!netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) tp->rtl_ops.enable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) netif_stop_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) napi_disable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) netif_carrier_on(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) rtl_start_rx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) _rtl8152_set_rx_mode(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) napi_enable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) netif_wake_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) netif_info(tp, link, netdev, "carrier on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) } else if (netif_queue_stopped(netdev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) netif_wake_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) if (netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) netif_carrier_off(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) tasklet_disable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) napi_disable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) tp->rtl_ops.disable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) napi_enable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) tasklet_enable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) netif_info(tp, link, netdev, "carrier off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) static void rtl_work_func_t(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) struct r8152 *tp = container_of(work, struct r8152, schedule.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) /* If the device is unplugged or !netif_running(), the workqueue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) * doesn't need to wake the device, and could return directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) if (usb_autopm_get_interface(tp->intf) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) if (!test_bit(WORK_ENABLE, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) if (!mutex_trylock(&tp->control)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) schedule_delayed_work(&tp->schedule, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) set_carrier(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) _rtl8152_set_rx_mode(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) /* don't schedule tasket before linking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) netif_carrier_ok(tp->netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) tasklet_schedule(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) static void rtl_hw_phy_work_func_t(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) if (usb_autopm_get_interface(tp->intf) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) tp->rtl_fw.retry = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) tp->rtl_fw.fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) /* Delay execution in case request_firmware() is not ready yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) goto ignore_once;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) tp->rtl_ops.hw_phy_cfg(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) tp->advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) ignore_once:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) static int rtl_notifier(struct notifier_block *nb, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) case PM_HIBERNATION_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) case PM_SUSPEND_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) case PM_POST_HIBERNATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) case PM_POST_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) case PM_POST_RESTORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) case PM_RESTORE_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) static int rtl8152_open(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) cancel_delayed_work_sync(&tp->hw_phy_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) res = alloc_all_mem(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) res = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) tp->rtl_ops.up(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) netif_carrier_off(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) netif_start_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) set_bit(WORK_ENABLE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) if (res == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) netif_device_detach(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) napi_enable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) tasklet_enable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) tp->pm_notifier.notifier_call = rtl_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) register_pm_notifier(&tp->pm_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) free_all_mem(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) static int rtl8152_close(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) unregister_pm_notifier(&tp->pm_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) tasklet_disable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) clear_bit(WORK_ENABLE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) usb_kill_urb(tp->intr_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) cancel_delayed_work_sync(&tp->schedule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) napi_disable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) netif_stop_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) res = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) rtl_drop_queued_tx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) rtl_stop_rx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) tp->rtl_ops.down(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) free_all_mem(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) static void rtl_tally_reset(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) ocp_data |= TALLY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) static void r8152b_init(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) data = r8152_mdio_read(tp, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) if (data & BMCR_PDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) data &= ~BMCR_PDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) r8152_mdio_write(tp, MII_BMCR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) r8152_aldps_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) if (tp->version == RTL_VER_01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) ocp_data &= ~LED_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) r8152_power_cut_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) ocp_data &= ~MCU_CLK_RATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) rtl_tally_reset(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) /* enable rx aggregation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) static void r8153_init(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) r8153_u1u2en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) for (i = 0; i < 500; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) AUTOLOAD_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) data = r8153_phy_status(tp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) tp->version == RTL_VER_05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) data = r8152_mdio_read(tp, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) if (data & BMCR_PDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) data &= ~BMCR_PDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) r8152_mdio_write(tp, MII_BMCR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) r8153_u2p3en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) if (tp->version == RTL_VER_04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) ocp_data &= ~pwd_dn_scale_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) ocp_data |= pwd_dn_scale(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) } else if (tp->version == RTL_VER_05) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) ocp_data &= ~ECM_ALDPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) ocp_data &= ~DYNAMIC_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) ocp_data |= DYNAMIC_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) } else if (tp->version == RTL_VER_06) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) ocp_data &= ~DYNAMIC_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) ocp_data |= DYNAMIC_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) r8153_queue_wake(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) if (rtl8152_get_speed(tp) & LINK_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) ocp_data |= CUR_LINK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) ocp_data &= ~CUR_LINK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) ocp_data |= POLL_LINK_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) ocp_data |= EP4_FULL_FC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) ocp_data &= ~TIMER11_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) ocp_data &= ~LED_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) ocp_data |= LPM_TIMER_500MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) ocp_data |= LPM_TIMER_500US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) ocp_data &= ~SEN_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) /* MAC clock speed down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) r8153_power_cut_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) rtl_runtime_suspend_enable(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) r8153_u1u2en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) usb_enable_lpm(tp->udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) ocp_data |= LANWAKE_CLR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) ocp_data &= ~LANWAKE_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) /* rx aggregation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) ocp_data |= RX_AGG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) rtl_tally_reset(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) switch (tp->udev->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) case USB_SPEED_SUPER_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) tp->coalesce = COALESCE_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) tp->coalesce = COALESCE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) tp->coalesce = COALESCE_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) static void r8153b_init(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) r8153b_u1u2en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) for (i = 0; i < 500; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) AUTOLOAD_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) data = r8153_phy_status(tp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) data = r8152_mdio_read(tp, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) if (data & BMCR_PDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) data &= ~BMCR_PDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) r8152_mdio_write(tp, MII_BMCR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) r8153_u2p3en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) /* MSC timer = 0xfff * 8ms = 32760 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) /* U1/U2/L1 idle timer. 500 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) r8153b_power_cut_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) r8153b_ups_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) r8153_queue_wake(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) rtl_runtime_suspend_enable(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) if (rtl8152_get_speed(tp) & LINK_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) ocp_data |= CUR_LINK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) ocp_data &= ~CUR_LINK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) ocp_data |= POLL_LINK_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) if (tp->udev->speed != USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) r8153b_u1u2en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) usb_enable_lpm(tp->udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) /* MAC clock speed down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) ocp_data |= MAC_CLK_SPDWN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) ocp_data &= ~PLA_MCU_SPDWN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) if (tp->version == RTL_VER_09) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) /* Disable Test IO for 32QFN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) ocp_data |= TEST_IO_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) set_bit(GREEN_ETHERNET, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) /* rx aggregation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) rtl_tally_reset(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) tp->coalesce = 15000; /* 15 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) static int rtl8152_pre_reset(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) struct r8152 *tp = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) if (!tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) if (!netif_running(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) netif_stop_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) tasklet_disable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) clear_bit(WORK_ENABLE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) usb_kill_urb(tp->intr_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) cancel_delayed_work_sync(&tp->schedule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) napi_disable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) if (netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) tp->rtl_ops.disable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) static int rtl8152_post_reset(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) struct r8152 *tp = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) struct sockaddr sa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) if (!tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) /* reset the MAC adddress in case of policy change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) if (determine_ethernet_addr(tp, &sa) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) dev_set_mac_address (tp->netdev, &sa, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) if (!netif_running(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) set_bit(WORK_ENABLE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) if (netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) tp->rtl_ops.enable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) rtl_start_rx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) _rtl8152_set_rx_mode(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) napi_enable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) tasklet_enable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) netif_wake_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) usb_submit_urb(tp->intr_urb, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) if (!list_empty(&tp->rx_done))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) napi_schedule(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) static bool delay_autosuspend(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) bool sw_linking = !!netif_carrier_ok(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) /* This means a linking change occurs and the driver doesn't detect it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) * yet. If the driver has disabled tx/rx and hw is linking on, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) * device wouldn't wake up by receiving any packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) /* If the linking down is occurred by nway, the device may miss the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) * linking change event. And it wouldn't wake when linking on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) if (!sw_linking && tp->rtl_ops.in_nway(tp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) else if (!skb_queue_empty(&tp->tx_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) static int rtl8152_runtime_resume(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) if (netif_running(netdev) && netdev->flags & IFF_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) struct napi_struct *napi = &tp->napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) tp->rtl_ops.autosuspend_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) napi_disable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) set_bit(WORK_ENABLE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) if (netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) if (rtl8152_get_speed(tp) & LINK_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) rtl_start_rx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) netif_carrier_off(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) tp->rtl_ops.disable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) netif_info(tp, link, netdev, "linking down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) napi_enable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) clear_bit(SELECTIVE_SUSPEND, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) if (!list_empty(&tp->rx_done))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) napi_schedule(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) usb_submit_urb(tp->intr_urb, GFP_NOIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) if (netdev->flags & IFF_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) tp->rtl_ops.autosuspend_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) clear_bit(SELECTIVE_SUSPEND, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) static int rtl8152_system_resume(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) netif_device_attach(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) tp->rtl_ops.up(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) netif_carrier_off(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) set_bit(WORK_ENABLE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) usb_submit_urb(tp->intr_urb, GFP_NOIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) static int rtl8152_runtime_suspend(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) set_bit(SELECTIVE_SUSPEND, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) u32 rcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) if (netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) u32 ocp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) ocp_data = rcr & ~RCR_ACPT_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) rxdy_gated_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) PLA_OOB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) if (!(ocp_data & RXFIFO_EMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) rxdy_gated_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) clear_bit(SELECTIVE_SUSPEND, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) clear_bit(WORK_ENABLE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) usb_kill_urb(tp->intr_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) tp->rtl_ops.autosuspend_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) if (netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) struct napi_struct *napi = &tp->napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) napi_disable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) rtl_stop_rx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) rxdy_gated_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) napi_enable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) if (delay_autosuspend(tp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) rtl8152_runtime_resume(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) static int rtl8152_system_suspend(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) struct net_device *netdev = tp->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) netif_device_detach(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) struct napi_struct *napi = &tp->napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) clear_bit(WORK_ENABLE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) usb_kill_urb(tp->intr_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) tasklet_disable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) napi_disable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) cancel_delayed_work_sync(&tp->schedule);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) tp->rtl_ops.down(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) napi_enable(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) tasklet_enable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) struct r8152 *tp = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) if (PMSG_IS_AUTO(message))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) ret = rtl8152_runtime_suspend(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) ret = rtl8152_system_suspend(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) static int rtl8152_resume(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) struct r8152 *tp = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) ret = rtl8152_runtime_resume(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) ret = rtl8152_system_resume(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) static int rtl8152_reset_resume(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) struct r8152 *tp = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) clear_bit(SELECTIVE_SUSPEND, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) tp->rtl_ops.init(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) set_ethernet_addr(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) return rtl8152_resume(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) if (usb_autopm_get_interface(tp->intf) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) if (!rtl_can_wakeup(tp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) wol->supported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) wol->supported = WAKE_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) wol->wolopts = __rtl_get_wol(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) if (!rtl_can_wakeup(tp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) if (wol->wolopts & ~WAKE_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) goto out_set_wol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) __rtl_set_wol(tp, wol->wolopts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) tp->saved_wolopts = wol->wolopts & WAKE_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) out_set_wol:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) static u32 rtl8152_get_msglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) return tp->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) tp->msg_enable = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) static void rtl8152_get_drvinfo(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) strlcpy(info->driver, MODULENAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) strlcpy(info->fw_version, tp->rtl_fw.version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) sizeof(info->fw_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) int rtl8152_get_link_ksettings(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) if (!tp->mii.mdio_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) mii_ethtool_get_link_ksettings(&tp->mii, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) static int rtl8152_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) u32 advertising = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) cmd->link_modes.advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) advertising |= RTL_ADVERTISED_10_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) cmd->link_modes.advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) advertising |= RTL_ADVERTISED_10_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) cmd->link_modes.advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) advertising |= RTL_ADVERTISED_100_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) cmd->link_modes.advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) advertising |= RTL_ADVERTISED_100_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) cmd->link_modes.advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) advertising |= RTL_ADVERTISED_1000_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) cmd->link_modes.advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) advertising |= RTL_ADVERTISED_1000_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) cmd->base.duplex, advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) tp->autoneg = cmd->base.autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) tp->speed = cmd->base.speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) tp->duplex = cmd->base.duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) tp->advertising = advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) "tx_packets",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) "rx_packets",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) "tx_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) "rx_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) "rx_missed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) "align_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) "tx_single_collisions",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) "tx_multi_collisions",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) "rx_unicast",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) "rx_broadcast",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) "rx_multicast",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) "tx_aborted",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) "tx_underrun",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) static int rtl8152_get_sset_count(struct net_device *dev, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) switch (sset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) return ARRAY_SIZE(rtl8152_gstrings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) static void rtl8152_get_ethtool_stats(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) struct tally_counter tally;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) if (usb_autopm_get_interface(tp->intf) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) data[0] = le64_to_cpu(tally.tx_packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) data[1] = le64_to_cpu(tally.rx_packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) data[2] = le64_to_cpu(tally.tx_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) data[3] = le32_to_cpu(tally.rx_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) data[4] = le16_to_cpu(tally.rx_missed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) data[5] = le16_to_cpu(tally.align_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) data[6] = le32_to_cpu(tally.tx_one_collision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) data[7] = le32_to_cpu(tally.tx_multi_collision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) data[8] = le64_to_cpu(tally.rx_unicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) data[9] = le64_to_cpu(tally.rx_broadcast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) data[10] = le32_to_cpu(tally.rx_multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) data[11] = le16_to_cpu(tally.tx_aborted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) data[12] = le16_to_cpu(tally.tx_underrun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) switch (stringset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) u32 lp, adv, supported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) supported = mmd_eee_cap_to_ethtool_sup_t(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) adv = mmd_eee_adv_to_ethtool_adv_t(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) lp = mmd_eee_adv_to_ethtool_adv_t(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) eee->eee_enabled = tp->eee_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) eee->eee_active = !!(supported & adv & lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) eee->supported = supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) eee->advertised = tp->eee_adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) eee->lp_advertised = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) tp->eee_en = eee->eee_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) tp->eee_adv = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) rtl_eee_enable(tp, tp->eee_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) u32 lp, adv, supported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) val = ocp_reg_read(tp, OCP_EEE_ABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) supported = mmd_eee_cap_to_ethtool_sup_t(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) val = ocp_reg_read(tp, OCP_EEE_ADV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) adv = mmd_eee_adv_to_ethtool_adv_t(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) val = ocp_reg_read(tp, OCP_EEE_LPABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) lp = mmd_eee_adv_to_ethtool_adv_t(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) eee->eee_enabled = tp->eee_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) eee->eee_active = !!(supported & adv & lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) eee->supported = supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) eee->advertised = tp->eee_adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) eee->lp_advertised = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) struct r8152 *tp = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) ret = tp->rtl_ops.eee_get(tp, edata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) struct r8152 *tp = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) ret = tp->rtl_ops.eee_set(tp, edata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) ret = mii_nway_restart(&tp->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) static int rtl8152_nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) ret = mii_nway_restart(&tp->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) static int rtl8152_get_coalesce(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) struct ethtool_coalesce *coalesce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) coalesce->rx_coalesce_usecs = tp->coalesce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) static int rtl8152_set_coalesce(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) struct ethtool_coalesce *coalesce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) if (tp->coalesce != coalesce->rx_coalesce_usecs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) tp->coalesce = coalesce->rx_coalesce_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) if (netif_running(netdev) && netif_carrier_ok(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) netif_stop_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) napi_disable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) tp->rtl_ops.disable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) tp->rtl_ops.enable(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) rtl_start_rx(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) _rtl8152_set_rx_mode(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) napi_enable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) netif_wake_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) static int rtl8152_get_tunable(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) const struct ethtool_tunable *tunable, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) switch (tunable->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) case ETHTOOL_RX_COPYBREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) *(u32 *)d = tp->rx_copybreak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) static int rtl8152_set_tunable(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) const struct ethtool_tunable *tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) const void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) switch (tunable->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) case ETHTOOL_RX_COPYBREAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) val = *(u32 *)d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) if (val < ETH_ZLEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) netif_err(tp, rx_err, netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) "Invalid rx copy break value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) if (tp->rx_copybreak != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) if (netdev->flags & IFF_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) napi_disable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) tp->rx_copybreak = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) napi_enable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) tp->rx_copybreak = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) static void rtl8152_get_ringparam(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) struct ethtool_ringparam *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) ring->rx_pending = tp->rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) static int rtl8152_set_ringparam(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) struct ethtool_ringparam *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) if (ring->rx_pending < (RTL8152_MAX_RX * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) if (tp->rx_pending != ring->rx_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) if (netdev->flags & IFF_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) napi_disable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) tp->rx_pending = ring->rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) napi_enable(&tp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) tp->rx_pending = ring->rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) static const struct ethtool_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) .get_drvinfo = rtl8152_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) .nway_reset = rtl8152_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) .get_msglevel = rtl8152_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) .set_msglevel = rtl8152_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) .get_wol = rtl8152_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) .set_wol = rtl8152_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) .get_strings = rtl8152_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) .get_sset_count = rtl8152_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) .get_ethtool_stats = rtl8152_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) .get_coalesce = rtl8152_get_coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) .set_coalesce = rtl8152_set_coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) .get_eee = rtl_ethtool_get_eee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) .set_eee = rtl_ethtool_set_eee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) .get_link_ksettings = rtl8152_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) .set_link_ksettings = rtl8152_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) .get_tunable = rtl8152_get_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) .set_tunable = rtl8152_set_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) .get_ringparam = rtl8152_get_ringparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) .set_ringparam = rtl8152_set_ringparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) struct r8152 *tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) struct mii_ioctl_data *data = if_mii(rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) res = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) case SIOCGMIIPHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) data->phy_id = R8152_PHY_ID; /* Internal PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) case SIOCGMIIREG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) data->val_out = r8152_mdio_read(tp, data->reg_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) case SIOCSMIIREG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) if (!capable(CAP_NET_ADMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) res = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) r8152_mdio_write(tp, data->reg_num, data->val_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) res = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) struct r8152 *tp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) dev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) ret = usb_autopm_get_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) mutex_lock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) dev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) if (netif_carrier_ok(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) r8153_set_rx_early_size(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) mutex_unlock(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) usb_autopm_put_interface(tp->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) static const struct net_device_ops rtl8152_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) .ndo_open = rtl8152_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) .ndo_stop = rtl8152_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) .ndo_do_ioctl = rtl8152_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) .ndo_start_xmit = rtl8152_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) .ndo_tx_timeout = rtl8152_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) .ndo_set_features = rtl8152_set_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) .ndo_set_rx_mode = rtl8152_set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) .ndo_set_mac_address = rtl8152_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) .ndo_change_mtu = rtl8152_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) .ndo_features_check = rtl8152_features_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) static void rtl8152_unload(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) if (tp->version != RTL_VER_01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) r8152_power_cut_en(tp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) static void rtl8153_unload(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) r8153_power_cut_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) static void rtl8153b_unload(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) if (test_bit(RTL8152_UNPLUG, &tp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) r8153b_power_cut_en(tp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) static int rtl_ops_init(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) struct rtl_ops *ops = &tp->rtl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) ops->init = r8152b_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) ops->enable = rtl8152_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) ops->disable = rtl8152_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) ops->up = rtl8152_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) ops->down = rtl8152_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) ops->unload = rtl8152_unload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) ops->eee_get = r8152_get_eee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) ops->eee_set = r8152_set_eee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) ops->in_nway = rtl8152_in_nway;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) ops->hw_phy_cfg = r8152b_hw_phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) ops->autosuspend_en = rtl_runtime_suspend_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) tp->rx_buf_sz = 16 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) tp->eee_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) tp->eee_adv = MDIO_EEE_100TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) case RTL_VER_03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) ops->init = r8153_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) ops->enable = rtl8153_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) ops->disable = rtl8153_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) ops->up = rtl8153_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) ops->down = rtl8153_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) ops->unload = rtl8153_unload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) ops->eee_get = r8153_get_eee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) ops->eee_set = r8152_set_eee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) ops->in_nway = rtl8153_in_nway;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) ops->hw_phy_cfg = r8153_hw_phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) ops->autosuspend_en = rtl8153_runtime_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) if (tp->udev->speed < USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) tp->rx_buf_sz = 16 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) tp->rx_buf_sz = 32 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) tp->eee_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) case RTL_VER_08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) ops->init = r8153b_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) ops->enable = rtl8153_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) ops->disable = rtl8153_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) ops->up = rtl8153b_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) ops->down = rtl8153b_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) ops->unload = rtl8153b_unload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) ops->eee_get = r8153_get_eee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) ops->eee_set = r8152_set_eee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) ops->in_nway = rtl8153_in_nway;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) ops->hw_phy_cfg = r8153b_hw_phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) ops->autosuspend_en = rtl8153b_runtime_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) tp->rx_buf_sz = 32 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) tp->eee_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) netif_err(tp, probe, tp->netdev, "Unknown Device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) MODULE_FIRMWARE(FIRMWARE_8153A_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) MODULE_FIRMWARE(FIRMWARE_8153A_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) MODULE_FIRMWARE(FIRMWARE_8153A_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) MODULE_FIRMWARE(FIRMWARE_8153B_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) static int rtl_fw_init(struct r8152 *tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) struct rtl_fw *rtl_fw = &tp->rtl_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) case RTL_VER_04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) rtl_fw->fw_name = FIRMWARE_8153A_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) rtl_fw->pre_fw = r8153_pre_firmware_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) rtl_fw->post_fw = r8153_post_firmware_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) case RTL_VER_05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) rtl_fw->fw_name = FIRMWARE_8153A_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) rtl_fw->pre_fw = r8153_pre_firmware_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) rtl_fw->post_fw = r8153_post_firmware_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) case RTL_VER_06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) rtl_fw->fw_name = FIRMWARE_8153A_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) rtl_fw->post_fw = r8153_post_firmware_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) case RTL_VER_09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) rtl_fw->fw_name = FIRMWARE_8153B_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) rtl_fw->pre_fw = r8153b_pre_firmware_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) rtl_fw->post_fw = r8153b_post_firmware_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) static u8 rtl_get_version(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) struct usb_device *udev = interface_to_usbdev(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) u32 ocp_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) __le32 *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) switch (ocp_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) case 0x4c00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) version = RTL_VER_01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) case 0x4c10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) version = RTL_VER_02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) case 0x5c00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) version = RTL_VER_03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) case 0x5c10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) version = RTL_VER_04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) case 0x5c20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) version = RTL_VER_05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) case 0x5c30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) version = RTL_VER_06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) case 0x4800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) version = RTL_VER_07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) case 0x6000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) version = RTL_VER_08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) case 0x6010:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) version = RTL_VER_09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) version = RTL_VER_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) return version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) static int rtl8152_probe(struct usb_interface *intf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661) struct usb_device *udev = interface_to_usbdev(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) u8 version = rtl_get_version(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) struct r8152 *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) if (version == RTL_VER_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) if (udev->actconfig->desc.bConfigurationValue != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) usb_driver_set_configuration(udev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) if (intf->cur_altsetting->desc.bNumEndpoints < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) usb_reset_device(udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) netdev = alloc_etherdev(sizeof(struct r8152));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) if (!netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) dev_err(&intf->dev, "Out of memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) SET_NETDEV_DEV(netdev, &intf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) tp = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) tp->msg_enable = 0x7FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) tp->udev = udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) tp->netdev = netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) tp->intf = intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) tp->version = version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) switch (version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) case RTL_VER_07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) tp->mii.supports_gmii = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) tp->mii.supports_gmii = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) ret = rtl_ops_init(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) rtl_fw_init(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) mutex_init(&tp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) tasklet_disable(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) netdev->netdev_ops = &rtl8152_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) NETIF_F_HW_VLAN_CTAG_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) NETIF_F_TSO | NETIF_F_FRAGLIST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) if (tp->version == RTL_VER_01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) netdev->features &= ~NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) netdev->hw_features &= ~NETIF_F_RXCSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) switch (le16_to_cpu(udev->descriptor.idProduct)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) set_bit(LENOVO_MACPASSTHRU, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) (!strcmp(udev->serial, "000001000000") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747) !strcmp(udev->serial, "000002000000"))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) netdev->ethtool_ops = &ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) /* MTU range: 68 - 1500 or 9194 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) netdev->min_mtu = ETH_MIN_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) switch (tp->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) case RTL_VER_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) case RTL_VER_02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) netdev->max_mtu = ETH_DATA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) netdev->max_mtu = RTL8153_MAX_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) tp->mii.dev = netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) tp->mii.mdio_read = read_mii_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) tp->mii.mdio_write = write_mii_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) tp->mii.phy_id_mask = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) tp->mii.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) tp->mii.phy_id = R8152_PHY_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) tp->autoneg = AUTONEG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) tp->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) if (tp->mii.supports_gmii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) tp->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) tp->advertising |= RTL_ADVERTISED_1000_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) tp->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) tp->rx_pending = 10 * RTL8152_MAX_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) intf->needs_remote_wakeup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) if (!rtl_can_wakeup(tp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) __rtl_set_wol(tp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) tp->saved_wolopts = __rtl_get_wol(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) tp->rtl_ops.init(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) #if IS_BUILTIN(CONFIG_USB_RTL8152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) /* Retry in case request_firmware() is not ready yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) tp->rtl_fw.retry = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) set_ethernet_addr(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) usb_set_intfdata(intf, tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) ret = register_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) netif_err(tp, probe, netdev, "couldn't register the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) if (tp->saved_wolopts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) device_set_wakeup_enable(&udev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) device_set_wakeup_enable(&udev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) tasklet_kill(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) usb_set_intfdata(intf, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) free_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) static void rtl8152_disconnect(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) struct r8152 *tp = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) usb_set_intfdata(intf, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) if (tp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) rtl_set_unplug(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) unregister_netdev(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) tasklet_kill(&tp->tx_tl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) cancel_delayed_work_sync(&tp->hw_phy_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) tp->rtl_ops.unload(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) rtl8152_release_firmware(tp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) free_netdev(tp->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) #define REALTEK_USB_DEVICE(vend, prod) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) USB_DEVICE_ID_MATCH_INT_CLASS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) .idVendor = (vend), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) .idProduct = (prod), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) USB_DEVICE_ID_MATCH_DEVICE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) .idVendor = (vend), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) .idProduct = (prod), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) .bInterfaceClass = USB_CLASS_COMM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) .bInterfaceProtocol = USB_CDC_PROTO_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) /* table of devices that work with this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) static const struct usb_device_id rtl8152_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) MODULE_DEVICE_TABLE(usb, rtl8152_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) static struct usb_driver rtl8152_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) .name = MODULENAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) .id_table = rtl8152_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) .probe = rtl8152_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) .disconnect = rtl8152_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) .suspend = rtl8152_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) .resume = rtl8152_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) .reset_resume = rtl8152_reset_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) .pre_reset = rtl8152_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) .post_reset = rtl8152_post_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) .supports_autosuspend = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) .disable_hub_initiated_lpm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) module_usb_driver(rtl8152_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) MODULE_VERSION(DRIVER_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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