Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015 Microchip Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef _LAN78XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define _LAN78XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /* USB Vendor Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define USB_VENDOR_REQUEST_WRITE_REGISTER	0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define USB_VENDOR_REQUEST_READ_REGISTER	0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define USB_VENDOR_REQUEST_GET_STATS		0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* Interrupt Endpoint status word bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define INT_ENP_EEE_START_TX_LPI_INT		BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define INT_ENP_EEE_STOP_TX_LPI_INT		BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define INT_ENP_EEE_RX_LPI_INT			BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define INT_ENP_RDFO_INT			BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define INT_ENP_TXE_INT				BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define INT_ENP_TX_DIS_INT			BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define INT_ENP_RX_DIS_INT			BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define INT_ENP_PHY_INT				BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define INT_ENP_DP_INT				BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define INT_ENP_MAC_ERR_INT			BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define INT_ENP_TDFU_INT			BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define INT_ENP_TDFO_INT			BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define INT_ENP_UTX_FP_INT			BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TX_PKT_ALIGNMENT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RX_PKT_ALIGNMENT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Tx Command A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TX_CMD_A_IGE_			(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TX_CMD_A_ICE_			(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TX_CMD_A_LSO_			(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TX_CMD_A_IPE_			(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TX_CMD_A_TPE_			(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TX_CMD_A_IVTG_			(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TX_CMD_A_RVTG_			(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TX_CMD_A_FCS_			(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TX_CMD_A_LEN_MASK_		(0x000FFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* Tx Command B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TX_CMD_B_MSS_SHIFT_		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TX_CMD_B_MSS_MASK_		(0x3FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TX_CMD_B_MSS_MIN_		((unsigned short)8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TX_CMD_B_VTAG_MASK_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TX_CMD_B_VTAG_PRI_MASK_		(0x0000E000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TX_CMD_B_VTAG_CFI_MASK_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TX_CMD_B_VTAG_VID_MASK_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* Rx Command A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RX_CMD_A_ICE_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RX_CMD_A_TCE_			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RX_CMD_A_CSE_MASK_		(0xC0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RX_CMD_A_IPV_			(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define RX_CMD_A_PID_MASK_		(0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RX_CMD_A_PID_NONE_IP_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define RX_CMD_A_PID_TCP_IP_		(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define RX_CMD_A_PID_UDP_IP_		(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define RX_CMD_A_PID_IP_		(0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define RX_CMD_A_PFF_			(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define RX_CMD_A_BAM_			(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define RX_CMD_A_MAM_			(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define RX_CMD_A_FVTG_			(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RX_CMD_A_RED_			(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define RX_CMD_A_RX_ERRS_MASK_		(0xC03F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define RX_CMD_A_RWT_			(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define RX_CMD_A_RUNT_			(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define RX_CMD_A_LONG_			(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define RX_CMD_A_RXE_			(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define RX_CMD_A_DRB_			(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define RX_CMD_A_FCS_			(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define RX_CMD_A_UAM_			(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define RX_CMD_A_ICSM_			(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define RX_CMD_A_LEN_MASK_		(0x00003FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* Rx Command B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define RX_CMD_B_CSUM_SHIFT_		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define RX_CMD_B_CSUM_MASK_		(0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define RX_CMD_B_VTAG_MASK_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define RX_CMD_B_VTAG_PRI_MASK_		(0x0000E000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define RX_CMD_B_VTAG_CFI_MASK_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define RX_CMD_B_VTAG_VID_MASK_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Rx Command C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define RX_CMD_C_WAKE_SHIFT_		(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define RX_CMD_C_WAKE_			(0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define RX_CMD_C_REF_FAIL_SHIFT_	(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define RX_CMD_C_REF_FAIL_		(0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* SCSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define NUMBER_OF_REGS			(193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ID_REV				(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ID_REV_CHIP_ID_MASK_		(0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ID_REV_CHIP_REV_MASK_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ID_REV_CHIP_ID_7800_		(0x7800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ID_REV_CHIP_ID_7850_		(0x7850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ID_REV_CHIP_ID_7801_		(0x7801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FPGA_REV			(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FPGA_REV_MINOR_MASK_		(0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FPGA_REV_MAJOR_MASK_		(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define INT_STS				(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define INT_STS_CLEAR_ALL_		(0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define INT_STS_EEE_TX_LPI_STRT_	(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define INT_STS_EEE_TX_LPI_STOP_	(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define INT_STS_EEE_RX_LPI_		(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INT_STS_RDFO_			(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define INT_STS_TXE_			(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define INT_STS_TX_DIS_			(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define INT_STS_RX_DIS_			(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define INT_STS_PHY_INT_		(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define INT_STS_DP_INT_			(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define INT_STS_MAC_ERR_		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define INT_STS_TDFU_			(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INT_STS_TDFO_			(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define INT_STS_UFX_FP_			(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INT_STS_GPIO_MASK_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INT_STS_GPIO11_			(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define INT_STS_GPIO10_			(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define INT_STS_GPIO9_			(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define INT_STS_GPIO8_			(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define INT_STS_GPIO7_			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define INT_STS_GPIO6_			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define INT_STS_GPIO5_			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define INT_STS_GPIO4_			(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define INT_STS_GPIO3_			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INT_STS_GPIO2_			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define INT_STS_GPIO1_			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define INT_STS_GPIO0_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HW_CFG				(0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HW_CFG_CLK125_EN_		(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HW_CFG_REFCLK25_EN_		(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HW_CFG_LED3_EN_			(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HW_CFG_LED2_EN_			(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HW_CFG_LED1_EN_			(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HW_CFG_LED0_EN_			(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HW_CFG_EEE_PHY_LUSU_		(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HW_CFG_EEE_TSU_			(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HW_CFG_NETDET_STS_		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HW_CFG_NETDET_EN_		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HW_CFG_EEM_			(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HW_CFG_RST_PROTECT_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HW_CFG_CONNECT_BUF_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HW_CFG_CONNECT_EN_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HW_CFG_CONNECT_POL_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HW_CFG_SUSPEND_N_SEL_MASK_	(0x000000C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HW_CFG_SUSPEND_N_SEL_2		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HW_CFG_SUSPEND_N_SEL_12N	(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HW_CFG_SUSPEND_N_SEL_012N	(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HW_CFG_SUSPEND_N_SEL_0123N	(0x000000C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HW_CFG_SUSPEND_N_POL_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HW_CFG_MEF_			(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HW_CFG_ETC_			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HW_CFG_LRST_			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HW_CFG_SRST_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PMT_CTL				(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PMT_CTL_EEE_WAKEUP_EN_		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PMT_CTL_EEE_WUPS_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PMT_CTL_MAC_SRST_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PMT_CTL_PHY_PWRUP_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PMT_CTL_RES_CLR_WKP_MASK_	(0x00000300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PMT_CTL_RES_CLR_WKP_STS_	(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PMT_CTL_RES_CLR_WKP_EN_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PMT_CTL_READY_			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PMT_CTL_SUS_MODE_MASK_		(0x00000060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PMT_CTL_SUS_MODE_0_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PMT_CTL_SUS_MODE_1_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PMT_CTL_SUS_MODE_2_		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PMT_CTL_SUS_MODE_3_		(0x00000060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PMT_CTL_PHY_RST_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PMT_CTL_WOL_EN_			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PMT_CTL_PHY_WAKE_EN_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PMT_CTL_WUPS_MASK_		(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PMT_CTL_WUPS_MLT_		(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PMT_CTL_WUPS_MAC_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PMT_CTL_WUPS_PHY_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GPIO_CFG0			(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GPIO_CFG0_GPIOEN_MASK_		(0x0000F000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GPIO_CFG0_GPIOEN3_		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GPIO_CFG0_GPIOEN2_		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GPIO_CFG0_GPIOEN1_		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GPIO_CFG0_GPIOEN0_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GPIO_CFG0_GPIOBUF_MASK_		(0x00000F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GPIO_CFG0_GPIOBUF3_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GPIO_CFG0_GPIOBUF2_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GPIO_CFG0_GPIOBUF1_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GPIO_CFG0_GPIOBUF0_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GPIO_CFG0_GPIODIR_MASK_		(0x000000F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GPIO_CFG0_GPIODIR3_		(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GPIO_CFG0_GPIODIR2_		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GPIO_CFG0_GPIODIR1_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GPIO_CFG0_GPIODIR0_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GPIO_CFG0_GPIOD_MASK_		(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GPIO_CFG0_GPIOD3_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GPIO_CFG0_GPIOD2_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GPIO_CFG0_GPIOD1_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GPIO_CFG0_GPIOD0_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GPIO_CFG1			(0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GPIO_CFG1_GPIOEN_MASK_		(0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GPIO_CFG1_GPIOEN11_		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GPIO_CFG1_GPIOEN10_		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GPIO_CFG1_GPIOEN9_		(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GPIO_CFG1_GPIOEN8_		(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GPIO_CFG1_GPIOEN7_		(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GPIO_CFG1_GPIOEN6_		(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GPIO_CFG1_GPIOEN5_		(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GPIO_CFG1_GPIOEN4_		(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GPIO_CFG1_GPIOBUF_MASK_		(0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GPIO_CFG1_GPIOBUF11_		(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GPIO_CFG1_GPIOBUF10_		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GPIO_CFG1_GPIOBUF9_		(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GPIO_CFG1_GPIOBUF8_		(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GPIO_CFG1_GPIOBUF7_		(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GPIO_CFG1_GPIOBUF6_		(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GPIO_CFG1_GPIOBUF5_		(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GPIO_CFG1_GPIOBUF4_		(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GPIO_CFG1_GPIODIR_MASK_		(0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GPIO_CFG1_GPIODIR11_		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GPIO_CFG1_GPIODIR10_		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GPIO_CFG1_GPIODIR9_		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GPIO_CFG1_GPIODIR8_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define GPIO_CFG1_GPIODIR7_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GPIO_CFG1_GPIODIR6_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GPIO_CFG1_GPIODIR5_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GPIO_CFG1_GPIODIR4_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GPIO_CFG1_GPIOD_MASK_		(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GPIO_CFG1_GPIOD11_		(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GPIO_CFG1_GPIOD10_		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GPIO_CFG1_GPIOD9_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GPIO_CFG1_GPIOD8_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GPIO_CFG1_GPIOD7_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define GPIO_CFG1_GPIOD6_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GPIO_CFG1_GPIOD6_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GPIO_CFG1_GPIOD5_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GPIO_CFG1_GPIOD4_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GPIO_WAKE			(0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GPIO_WAKE_GPIOPOL_MASK_		(0x0FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GPIO_WAKE_GPIOPOL11_		(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GPIO_WAKE_GPIOPOL10_		(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GPIO_WAKE_GPIOPOL9_		(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GPIO_WAKE_GPIOPOL8_		(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define GPIO_WAKE_GPIOPOL7_		(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GPIO_WAKE_GPIOPOL6_		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define GPIO_WAKE_GPIOPOL5_		(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GPIO_WAKE_GPIOPOL4_		(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GPIO_WAKE_GPIOPOL3_		(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GPIO_WAKE_GPIOPOL2_		(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GPIO_WAKE_GPIOPOL1_		(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GPIO_WAKE_GPIOPOL0_		(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GPIO_WAKE_GPIOWK_MASK_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define GPIO_WAKE_GPIOWK11_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define GPIO_WAKE_GPIOWK10_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define GPIO_WAKE_GPIOWK9_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GPIO_WAKE_GPIOWK8_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GPIO_WAKE_GPIOWK7_		(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define GPIO_WAKE_GPIOWK6_		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define GPIO_WAKE_GPIOWK5_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GPIO_WAKE_GPIOWK4_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GPIO_WAKE_GPIOWK3_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define GPIO_WAKE_GPIOWK2_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define GPIO_WAKE_GPIOWK1_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define GPIO_WAKE_GPIOWK0_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DP_SEL				(0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DP_SEL_DPRDY_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DP_SEL_RSEL_MASK_		(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DP_SEL_RSEL_USB_PHY_CSRS_	(0x0000000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DP_SEL_RSEL_OTP_64BIT_		(0x00000009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DP_SEL_RSEL_OTP_8BIT_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DP_SEL_RSEL_UTX_BUF_RAM_	(0x00000007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DP_SEL_RSEL_DESC_RAM_		(0x00000005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DP_SEL_RSEL_TXFIFO_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DP_SEL_RSEL_RXFIFO_		(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DP_SEL_RSEL_LSO_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DP_SEL_RSEL_VLAN_DA_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DP_SEL_RSEL_URXBUF_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DP_SEL_VHF_HASH_LEN		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DP_SEL_VHF_VLAN_LEN		(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DP_CMD				(0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DP_CMD_WRITE_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DP_CMD_READ_			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DP_ADDR				(0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DP_ADDR_MASK_			(0x00003FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DP_DATA				(0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define E2P_CMD				(0x040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define E2P_CMD_EPC_BUSY_		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define E2P_CMD_EPC_CMD_MASK_		(0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define E2P_CMD_EPC_CMD_RELOAD_		(0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define E2P_CMD_EPC_CMD_ERAL_		(0x60000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define E2P_CMD_EPC_CMD_ERASE_		(0x50000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define E2P_CMD_EPC_CMD_WRAL_		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define E2P_CMD_EPC_CMD_WRITE_		(0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define E2P_CMD_EPC_CMD_EWEN_		(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define E2P_CMD_EPC_CMD_EWDS_		(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define E2P_CMD_EPC_CMD_READ_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define E2P_CMD_EPC_TIMEOUT_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define E2P_CMD_EPC_DL_			(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define E2P_CMD_EPC_ADDR_MASK_		(0x000001FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define E2P_DATA			(0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define E2P_DATA_EEPROM_DATA_MASK_	(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define BOS_ATTR			(0x050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define BOS_ATTR_BLOCK_SIZE_MASK_	(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SS_ATTR				(0x054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SS_ATTR_POLL_INT_MASK_		(0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SS_ATTR_DEV_DESC_SIZE_MASK_	(0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SS_ATTR_CFG_BLK_SIZE_MASK_	(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HS_ATTR				(0x058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HS_ATTR_POLL_INT_MASK_		(0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HS_ATTR_DEV_DESC_SIZE_MASK_	(0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HS_ATTR_CFG_BLK_SIZE_MASK_	(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define FS_ATTR				(0x05C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define FS_ATTR_POLL_INT_MASK_		(0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define FS_ATTR_DEV_DESC_SIZE_MASK_	(0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define FS_ATTR_CFG_BLK_SIZE_MASK_	(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define STR_ATTR0			    (0x060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define STR_ATTR0_CFGSTR_DESC_SIZE_MASK_    (0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define STR_ATTR0_SERSTR_DESC_SIZE_MASK_    (0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define STR_ATTR0_PRODSTR_DESC_SIZE_MASK_   (0x0000FF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define STR_ATTR0_MANUF_DESC_SIZE_MASK_     (0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define STR_ATTR1			    (0x064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define STR_ATTR1_INTSTR_DESC_SIZE_MASK_    (0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define STR_FLAG_ATTR			    (0x068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define STR_FLAG_ATTR_PME_FLAGS_MASK_	    (0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define USB_CFG0			(0x080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define USB_CFG_LPM_RESPONSE_		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define USB_CFG_LPM_CAPABILITY_		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define USB_CFG_LPM_ENBL_SLPM_		(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define USB_CFG_HIRD_THR_MASK_		(0x1F000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define USB_CFG_HIRD_THR_960_		(0x1C000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define USB_CFG_HIRD_THR_885_		(0x1B000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define USB_CFG_HIRD_THR_810_		(0x1A000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define USB_CFG_HIRD_THR_735_		(0x19000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define USB_CFG_HIRD_THR_660_		(0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define USB_CFG_HIRD_THR_585_		(0x17000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define USB_CFG_HIRD_THR_510_		(0x16000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define USB_CFG_HIRD_THR_435_		(0x15000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define USB_CFG_HIRD_THR_360_		(0x14000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define USB_CFG_HIRD_THR_285_		(0x13000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define USB_CFG_HIRD_THR_210_		(0x12000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define USB_CFG_HIRD_THR_135_		(0x11000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define USB_CFG_HIRD_THR_60_		(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define USB_CFG_MAX_BURST_BI_MASK_	(0x00F00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define USB_CFG_MAX_BURST_BO_MASK_	(0x000F0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define USB_CFG_MAX_DEV_SPEED_MASK_	(0x0000E000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define USB_CFG_MAX_DEV_SPEED_SS_	(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define USB_CFG_MAX_DEV_SPEED_HS_	(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define USB_CFG_MAX_DEV_SPEED_FS_	(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define USB_CFG_PHY_BOOST_MASK_		(0x00000180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define USB_CFG_PHY_BOOST_PLUS_12_	(0x00000180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define USB_CFG_PHY_BOOST_PLUS_8_	(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define USB_CFG_PHY_BOOST_PLUS_4_	(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define USB_CFG_PHY_BOOST_NORMAL_	(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define USB_CFG_BIR_			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define USB_CFG_BCE_			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define USB_CFG_PORT_SWAP_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define USB_CFG_LPM_EN_			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define USB_CFG_RMT_WKP_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define USB_CFG_PWR_SEL_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define USB_CFG_STALL_BO_DIS_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define USB_CFG1			(0x084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define USB_CFG1_U1_TIMEOUT_MASK_	(0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define USB_CFG1_U2_TIMEOUT_MASK_	(0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define USB_CFG1_HS_TOUT_CAL_MASK_	(0x0000E000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define USB_CFG1_DEV_U2_INIT_EN_	(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define USB_CFG1_DEV_U2_EN_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define USB_CFG1_DEV_U1_INIT_EN_	(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define USB_CFG1_DEV_U1_EN_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define USB_CFG1_LTM_ENABLE_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define USB_CFG1_FS_TOUT_CAL_MASK_	(0x00000070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define USB_CFG1_SCALE_DOWN_MASK_	(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define USB_CFG1_SCALE_DOWN_MODE3_	(0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define USB_CFG1_SCALE_DOWN_MODE2_	(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define USB_CFG1_SCALE_DOWN_MODE1_	(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define USB_CFG1_SCALE_DOWN_MODE0_	(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define USB_CFG2			    (0x088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define USB_CFG2_SS_DETACH_TIME_MASK_	    (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define USB_CFG2_HS_DETACH_TIME_MASK_	    (0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define BURST_CAP			(0x090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define BURST_CAP_SIZE_MASK_		(0x000000FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define BULK_IN_DLY			(0x094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define BULK_IN_DLY_MASK_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define INT_EP_CTL			(0x098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define INT_EP_INTEP_ON_		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define INT_STS_EEE_TX_LPI_STRT_EN_	(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define INT_STS_EEE_TX_LPI_STOP_EN_	(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define INT_STS_EEE_RX_LPI_EN_		(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define INT_EP_RDFO_EN_			(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define INT_EP_TXE_EN_			(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define INT_EP_TX_DIS_EN_		(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define INT_EP_RX_DIS_EN_		(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define INT_EP_PHY_INT_EN_		(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define INT_EP_DP_INT_EN_		(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define INT_EP_MAC_ERR_EN_		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define INT_EP_TDFU_EN_			(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define INT_EP_TDFO_EN_			(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define INT_EP_UTX_FP_EN_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define INT_EP_GPIO_EN_MASK_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PIPE_CTL			(0x09C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PIPE_CTL_TXSWING_		(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PIPE_CTL_TXMARGIN_MASK_		(0x00000038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PIPE_CTL_TXDEEMPHASIS_MASK_	(0x00000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PIPE_CTL_ELASTICITYBUFFERMODE_	(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define U1_LATENCY			(0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define U2_LATENCY			(0xA4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define USB_STATUS			(0x0A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define USB_STATUS_REMOTE_WK_		(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define USB_STATUS_FUNC_REMOTE_WK_	(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define USB_STATUS_LTM_ENABLE_		(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define USB_STATUS_U2_ENABLE_		(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define USB_STATUS_U1_ENABLE_		(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define USB_STATUS_SET_SEL_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define USB_STATUS_REMOTE_WK_STS_	(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define USB_STATUS_FUNC_REMOTE_WK_STS_	(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define USB_STATUS_LTM_ENABLE_STS_	(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define USB_STATUS_U2_ENABLE_STS_	(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define USB_STATUS_U1_ENABLE_STS_	(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define USB_CFG3			(0x0AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define USB_CFG3_EN_U2_LTM_		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define USB_CFG3_BULK_OUT_NUMP_OVR_	(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define USB_CFG3_DIS_FAST_U1_EXIT_	(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define USB_CFG3_LPM_NYET_THR_		(0x0F000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define USB_CFG3_RX_DET_2_POL_LFPS_	(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define USB_CFG3_LFPS_FILT_		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define USB_CFG3_SKIP_RX_DET_		(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define USB_CFG3_DELAY_P1P2P3_		(0x001C0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define USB_CFG3_DELAY_PHY_PWR_CHG_	(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define USB_CFG3_U1U2_EXIT_FR_		(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define USB_CFG3_REQ_P1P2P3		(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define USB_CFG3_HST_PRT_CMPL_		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define USB_CFG3_DIS_SCRAMB_		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define USB_CFG3_PWR_DN_SCALE_		(0x00001FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define RFE_CTL				(0x0B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define RFE_CTL_IGMP_COE_		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define RFE_CTL_ICMP_COE_		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define RFE_CTL_TCPUDP_COE_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define RFE_CTL_IP_COE_			(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define RFE_CTL_BCAST_EN_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define RFE_CTL_MCAST_EN_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define RFE_CTL_UCAST_EN_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define RFE_CTL_VLAN_STRIP_		(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define RFE_CTL_DISCARD_UNTAGGED_	(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define RFE_CTL_VLAN_FILTER_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define RFE_CTL_SA_FILTER_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define RFE_CTL_MCAST_HASH_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define RFE_CTL_DA_HASH_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define RFE_CTL_DA_PERFECT_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define RFE_CTL_RST_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define VLAN_TYPE			(0x0B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define VLAN_TYPE_MASK_			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define FCT_RX_CTL			(0x0C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define FCT_RX_CTL_EN_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define FCT_RX_CTL_RST_			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define FCT_RX_CTL_SBF_			(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define FCT_RX_CTL_OVFL_		(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define FCT_RX_CTL_DROP_		(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define FCT_RX_CTL_NOT_EMPTY_		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define FCT_RX_CTL_EMPTY_		(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define FCT_RX_CTL_DIS_			(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define FCT_RX_CTL_USED_MASK_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define FCT_TX_CTL			(0x0C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define FCT_TX_CTL_EN_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define FCT_TX_CTL_RST_			(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define FCT_TX_CTL_NOT_EMPTY_		(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define FCT_TX_CTL_EMPTY_		(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define FCT_TX_CTL_DIS_			(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define FCT_TX_CTL_USED_MASK_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define FCT_RX_FIFO_END			(0x0C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define FCT_RX_FIFO_END_MASK_		(0x0000007F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define FCT_TX_FIFO_END			(0x0CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define FCT_TX_FIFO_END_MASK_		(0x0000003F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define FCT_FLOW			(0x0D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define FCT_FLOW_OFF_MASK_		(0x00007F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define FCT_FLOW_ON_MASK_		(0x0000007F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define RX_DP_STOR			(0x0D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define RX_DP_STORE_TOT_RXUSED_MASK_	(0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define RX_DP_STORE_UTX_RXUSED_MASK_	(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define TX_DP_STOR			(0x0D8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define TX_DP_STORE_TOT_TXUSED_MASK_	(0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define TX_DP_STORE_URX_TXUSED_MASK_	(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define LTM_BELT_IDLE0			(0x0E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define LTM_BELT_IDLE0_IDLE1000_	(0x0FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define LTM_BELT_IDLE0_IDLE100_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define LTM_BELT_IDLE1			(0x0E4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define LTM_BELT_IDLE1_IDLE10_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define LTM_BELT_ACT0			(0x0E8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define LTM_BELT_ACT0_ACT1000_		(0x0FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define LTM_BELT_ACT0_ACT100_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define LTM_BELT_ACT1			(0x0EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define LTM_BELT_ACT1_ACT10_		(0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define LTM_INACTIVE0			(0x0F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define LTM_INACTIVE0_TIMER1000_	(0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define LTM_INACTIVE0_TIMER100_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define LTM_INACTIVE1			(0x0F4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define LTM_INACTIVE1_TIMER10_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define MAC_CR				(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define MAC_CR_GMII_EN_			(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define MAC_CR_EEE_TX_CLK_STOP_EN_	(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define MAC_CR_EEE_EN_			(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define MAC_CR_EEE_TLAR_EN_		(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define MAC_CR_ADP_			(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define MAC_CR_AUTO_DUPLEX_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define MAC_CR_AUTO_SPEED_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define MAC_CR_LOOPBACK_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define MAC_CR_BOLMT_MASK_		(0x000000C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define MAC_CR_FULL_DUPLEX_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MAC_CR_SPEED_MASK_		(0x00000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define MAC_CR_SPEED_1000_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define MAC_CR_SPEED_100_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define MAC_CR_SPEED_10_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MAC_CR_RST_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define MAC_RX				(0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MAC_RX_MAX_SIZE_SHIFT_		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MAC_RX_MAX_SIZE_MASK_		(0x3FFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define MAC_RX_FCS_STRIP_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define MAC_RX_VLAN_FSE_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define MAC_RX_RXD_			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define MAC_RX_RXEN_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define MAC_TX				(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define MAC_TX_BAD_FCS_			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define MAC_TX_TXD_			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define MAC_TX_TXEN_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define FLOW				(0x10C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define FLOW_CR_FORCE_FC_		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define FLOW_CR_TX_FCEN_		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define FLOW_CR_RX_FCEN_		(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define FLOW_CR_FPF_			(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define FLOW_CR_FCPT_MASK_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define RAND_SEED			(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define RAND_SEED_MASK_			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define ERR_STS				(0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define ERR_STS_FERR_			(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define ERR_STS_LERR_			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define ERR_STS_RFERR_			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define ERR_STS_ECERR_			(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define ERR_STS_ALERR_			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define ERR_STS_URERR_			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define RX_ADDRH			(0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define RX_ADDRH_MASK_			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define RX_ADDRL			(0x11C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define RX_ADDRL_MASK_			(0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define MII_ACC				(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define MII_ACC_PHY_ADDR_SHIFT_		(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define MII_ACC_PHY_ADDR_MASK_		(0x0000F800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define MII_ACC_MIIRINDA_SHIFT_		(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define MII_ACC_MIIRINDA_MASK_		(0x000007C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define MII_ACC_MII_READ_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define MII_ACC_MII_WRITE_		(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define MII_ACC_MII_BUSY_		(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define MII_DATA			(0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define MII_DATA_MASK_			(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define MAC_RGMII_ID			(0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define MAC_RGMII_ID_TXC_DELAY_EN_	(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define MAC_RGMII_ID_RXC_DELAY_EN_	(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define EEE_TX_LPI_REQ_DLY		(0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define EEE_TX_LPI_REQ_DLY_CNT_MASK_	(0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define EEE_TW_TX_SYS			(0x134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define EEE_TW_TX_SYS_CNT1G_MASK_	(0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define EEE_TW_TX_SYS_CNT100M_MASK_	(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define EEE_TX_LPI_REM_DLY		(0x138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define EEE_TX_LPI_REM_DLY_CNT_		(0x00FFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define WUCSR				(0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define WUCSR_TESTMODE_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define WUCSR_RFE_WAKE_EN_		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define WUCSR_EEE_TX_WAKE_		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define WUCSR_EEE_TX_WAKE_EN_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define WUCSR_EEE_RX_WAKE_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define WUCSR_EEE_RX_WAKE_EN_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define WUCSR_RFE_WAKE_FR_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define WUCSR_STORE_WAKE_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define WUCSR_PFDA_FR_			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define WUCSR_WUFR_			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define WUCSR_MPR_			(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define WUCSR_BCST_FR_			(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define WUCSR_PFDA_EN_			(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define WUCSR_WAKE_EN_			(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define WUCSR_MPEN_			(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define WUCSR_BCST_EN_			(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define WK_SRC				(0x144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define WK_SRC_GPIOX_INT_WK_SHIFT_	(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define WK_SRC_GPIOX_INT_WK_MASK_	(0xFFF00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define WK_SRC_IPV6_TCPSYN_RCD_WK_	(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define WK_SRC_IPV4_TCPSYN_RCD_WK_	(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define WK_SRC_EEE_TX_WK_		(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define WK_SRC_EEE_RX_WK_		(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define WK_SRC_GOOD_FR_WK_		(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define WK_SRC_PFDA_FR_WK_		(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define WK_SRC_MP_FR_WK_		(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define WK_SRC_BCAST_FR_WK_		(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define WK_SRC_WU_FR_WK_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define WK_SRC_WUFF_MATCH_MASK_		(0x0000001F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define WUF_CFG0			(0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define NUM_OF_WUF_CFG			(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define WUF_CFG_BEGIN			(WUF_CFG0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define WUF_CFG(index)			(WUF_CFG_BEGIN + (4 * (index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define WUF_CFGX_EN_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define WUF_CFGX_TYPE_MASK_		(0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define WUF_CFGX_TYPE_MCAST_		(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define WUF_CFGX_TYPE_ALL_		(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define WUF_CFGX_TYPE_UCAST_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define WUF_CFGX_OFFSET_SHIFT_		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define WUF_CFGX_OFFSET_MASK_		(0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define WUF_CFGX_CRC16_MASK_		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define WUF_MASK0_0			(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define WUF_MASK0_1			(0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define WUF_MASK0_2			(0x208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define WUF_MASK0_3			(0x20C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define NUM_OF_WUF_MASK			(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define WUF_MASK0_BEGIN			(WUF_MASK0_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define WUF_MASK1_BEGIN			(WUF_MASK0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define WUF_MASK2_BEGIN			(WUF_MASK0_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define WUF_MASK3_BEGIN			(WUF_MASK0_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define WUF_MASK0(index)		(WUF_MASK0_BEGIN + (0x10 * (index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define WUF_MASK1(index)		(WUF_MASK1_BEGIN + (0x10 * (index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define WUF_MASK2(index)		(WUF_MASK2_BEGIN + (0x10 * (index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define WUF_MASK3(index)		(WUF_MASK3_BEGIN + (0x10 * (index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define MAF_BASE			(0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define MAF_HIX				(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define MAF_LOX				(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define NUM_OF_MAF			(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define MAF_HI_BEGIN			(MAF_BASE + MAF_HIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define MAF_LO_BEGIN			(MAF_BASE + MAF_LOX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define MAF_HI(index)			(MAF_BASE + (8 * (index)) + (MAF_HIX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define MAF_LO(index)			(MAF_BASE + (8 * (index)) + (MAF_LOX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define MAF_HI_VALID_			(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define MAF_HI_TYPE_MASK_		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define MAF_HI_TYPE_SRC_		(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define MAF_HI_TYPE_DST_		(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define MAF_HI_ADDR_MASK		(0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define MAF_LO_ADDR_MASK		(0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define WUCSR2				(0x600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define WUCSR2_CSUM_DISABLE_		(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define WUCSR2_NA_SA_SEL_		(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define WUCSR2_NS_RCD_			(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define WUCSR2_ARP_RCD_			(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define WUCSR2_IPV6_TCPSYN_RCD_		(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define WUCSR2_IPV4_TCPSYN_RCD_		(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define WUCSR2_NS_OFFLOAD_EN_		(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define WUCSR2_ARP_OFFLOAD_EN_		(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define WUCSR2_IPV6_TCPSYN_WAKE_EN_	(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define WUCSR2_IPV4_TCPSYN_WAKE_EN_	(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define NS1_IPV6_ADDR_DEST0		(0x610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define NS1_IPV6_ADDR_DEST1		(0x614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define NS1_IPV6_ADDR_DEST2		(0x618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define NS1_IPV6_ADDR_DEST3		(0x61C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define NS1_IPV6_ADDR_SRC0		(0x620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define NS1_IPV6_ADDR_SRC1		(0x624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define NS1_IPV6_ADDR_SRC2		(0x628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define NS1_IPV6_ADDR_SRC3		(0x62C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define NS1_ICMPV6_ADDR0_0		(0x630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define NS1_ICMPV6_ADDR0_1		(0x634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define NS1_ICMPV6_ADDR0_2		(0x638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define NS1_ICMPV6_ADDR0_3		(0x63C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define NS1_ICMPV6_ADDR1_0		(0x640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define NS1_ICMPV6_ADDR1_1		(0x644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define NS1_ICMPV6_ADDR1_2		(0x648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define NS1_ICMPV6_ADDR1_3		(0x64C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define NS2_IPV6_ADDR_DEST0		(0x650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define NS2_IPV6_ADDR_DEST1		(0x654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define NS2_IPV6_ADDR_DEST2		(0x658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define NS2_IPV6_ADDR_DEST3		(0x65C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define NS2_IPV6_ADDR_SRC0		(0x660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define NS2_IPV6_ADDR_SRC1		(0x664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define NS2_IPV6_ADDR_SRC2		(0x668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define NS2_IPV6_ADDR_SRC3		(0x66C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define NS2_ICMPV6_ADDR0_0		(0x670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define NS2_ICMPV6_ADDR0_1		(0x674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define NS2_ICMPV6_ADDR0_2		(0x678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define NS2_ICMPV6_ADDR0_3		(0x67C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define NS2_ICMPV6_ADDR1_0		(0x680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define NS2_ICMPV6_ADDR1_1		(0x684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define NS2_ICMPV6_ADDR1_2		(0x688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define NS2_ICMPV6_ADDR1_3		(0x68C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define SYN_IPV4_ADDR_SRC		(0x690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define SYN_IPV4_ADDR_DEST		(0x694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define SYN_IPV4_TCP_PORTS		(0x698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define SYN_IPV4_TCP_PORTS_IPV4_DEST_PORT_SHIFT_    (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SYN_IPV4_TCP_PORTS_IPV4_DEST_PORT_MASK_     (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define SYN_IPV4_TCP_PORTS_IPV4_SRC_PORT_MASK_	    (0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define SYN_IPV6_ADDR_SRC0		(0x69C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define SYN_IPV6_ADDR_SRC1		(0x6A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define SYN_IPV6_ADDR_SRC2		(0x6A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SYN_IPV6_ADDR_SRC3		(0x6A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define SYN_IPV6_ADDR_DEST0		(0x6AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SYN_IPV6_ADDR_DEST1		(0x6B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define SYN_IPV6_ADDR_DEST2		(0x6B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define SYN_IPV6_ADDR_DEST3		(0x6B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define SYN_IPV6_TCP_PORTS		(0x6BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define SYN_IPV6_TCP_PORTS_IPV6_DEST_PORT_SHIFT_    (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define SYN_IPV6_TCP_PORTS_IPV6_DEST_PORT_MASK_     (0xFFFF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define SYN_IPV6_TCP_PORTS_IPV6_SRC_PORT_MASK_	    (0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define ARP_SPA				(0x6C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define ARP_TPA				(0x6C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define PHY_DEV_ID			(0x700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define PHY_DEV_ID_REV_SHIFT_		(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define PHY_DEV_ID_REV_SHIFT_		(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define PHY_DEV_ID_REV_MASK_		(0xF0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define PHY_DEV_ID_MODEL_SHIFT_		(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define PHY_DEV_ID_MODEL_MASK_		(0x0FC00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define PHY_DEV_ID_OUI_MASK_		(0x003FFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define RGMII_TX_BYP_DLL		(0x708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define RGMII_TX_BYP_DLL_TX_TUNE_ADJ_MASK_	(0x000FC00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define RGMII_TX_BYP_DLL_TX_TUNE_SEL_MASK_	(0x00003F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define RGMII_TX_BYP_DLL_TX_DLL_RESET_		(0x0000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define RGMII_TX_BYP_DLL_TX_DLL_BYPASS_		(0x0000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define RGMII_RX_BYP_DLL		(0x70C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define RGMII_RX_BYP_DLL_RX_TUNE_ADJ_MASK_	(0x000FC00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define RGMII_RX_BYP_DLL_RX_TUNE_SEL_MASK_	(0x00003F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define RGMII_RX_BYP_DLL_RX_DLL_RESET_		(0x0000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define RGMII_RX_BYP_DLL_RX_DLL_BYPASS_		(0x0000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define OTP_BASE_ADDR			(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define OTP_ADDR_RANGE_			(0x1FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define OTP_PWR_DN			(OTP_BASE_ADDR + 4 * 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define OTP_PWR_DN_PWRDN_N_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define OTP_ADDR1			(OTP_BASE_ADDR + 4 * 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define OTP_ADDR1_15_11			(0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define OTP_ADDR2			(OTP_BASE_ADDR + 4 * 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define OTP_ADDR2_10_3			(0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define OTP_ADDR3			(OTP_BASE_ADDR + 4 * 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define OTP_ADDR3_2_0			(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define OTP_PRGM_DATA			(OTP_BASE_ADDR + 4 * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define OTP_PRGM_MODE			(OTP_BASE_ADDR + 4 * 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define OTP_PRGM_MODE_BYTE_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define OTP_RD_DATA			(OTP_BASE_ADDR + 4 * 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define OTP_FUNC_CMD			(OTP_BASE_ADDR + 4 * 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define OTP_FUNC_CMD_RESET_		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define OTP_FUNC_CMD_PROGRAM_		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define OTP_FUNC_CMD_READ_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define OTP_TST_CMD			(OTP_BASE_ADDR + 4 * 0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define OTP_TST_CMD_TEST_DEC_SEL_	(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define OTP_TST_CMD_PRGVRFY_		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define OTP_TST_CMD_WRTEST_		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define OTP_TST_CMD_TESTDEC_		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define OTP_TST_CMD_BLANKCHECK_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define OTP_CMD_GO			(OTP_BASE_ADDR + 4 * 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define OTP_CMD_GO_GO_			(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define OTP_PASS_FAIL			(OTP_BASE_ADDR + 4 * 0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define OTP_PASS_FAIL_PASS_		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define OTP_PASS_FAIL_FAIL_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define OTP_STATUS			(OTP_BASE_ADDR + 4 * 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define OTP_STATUS_OTP_LOCK_		(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define OTP_STATUS_WEB_			(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define OTP_STATUS_PGMEN		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define OTP_STATUS_CPUMPEN_		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define OTP_STATUS_BUSY_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define OTP_MAX_PRG			(OTP_BASE_ADDR + 4 * 0x0D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define OTP_MAX_PRG_MAX_PROG		(0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define OTP_INTR_STATUS			(OTP_BASE_ADDR + 4 * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define OTP_INTR_STATUS_READY_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define OTP_INTR_MASK			(OTP_BASE_ADDR + 4 * 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define OTP_INTR_MASK_READY_		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define OTP_RSTB_PW1			(OTP_BASE_ADDR + 4 * 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define OTP_RSTB_PW2			(OTP_BASE_ADDR + 4 * 0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define OTP_PGM_PW1			(OTP_BASE_ADDR + 4 * 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define OTP_PGM_PW2			(OTP_BASE_ADDR + 4 * 0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define OTP_READ_PW1			(OTP_BASE_ADDR + 4 * 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define OTP_READ_PW2			(OTP_BASE_ADDR + 4 * 0x1D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define OTP_TCRST			(OTP_BASE_ADDR + 4 * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define OTP_RSRD			(OTP_BASE_ADDR + 4 * 0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define OTP_TREADEN_VAL			(OTP_BASE_ADDR + 4 * 0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define OTP_TDLES_VAL			(OTP_BASE_ADDR + 4 * 0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define OTP_TWWL_VAL			(OTP_BASE_ADDR + 4 * 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define OTP_TDLEH_VAL			(OTP_BASE_ADDR + 4 * 0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define OTP_TWPED_VAL			(OTP_BASE_ADDR + 4 * 0x26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define OTP_TPES_VAL			(OTP_BASE_ADDR + 4 * 0x27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define OTP_TCPS_VAL			(OTP_BASE_ADDR + 4 * 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define OTP_TCPH_VAL			(OTP_BASE_ADDR + 4 * 0x29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define OTP_TPGMVFY_VAL			(OTP_BASE_ADDR + 4 * 0x2A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define OTP_TPEH_VAL			(OTP_BASE_ADDR + 4 * 0x2B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define OTP_TPGRST_VAL			(OTP_BASE_ADDR + 4 * 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define OTP_TCLES_VAL			(OTP_BASE_ADDR + 4 * 0x2D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define OTP_TCLEH_VAL			(OTP_BASE_ADDR + 4 * 0x2E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define OTP_TRDES_VAL			(OTP_BASE_ADDR + 4 * 0x2F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define OTP_TBCACC_VAL			(OTP_BASE_ADDR + 4 * 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define OTP_TAAC_VAL			(OTP_BASE_ADDR + 4 * 0x31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define OTP_TACCT_VAL			(OTP_BASE_ADDR + 4 * 0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define OTP_TRDEP_VAL			(OTP_BASE_ADDR + 4 * 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define OTP_TPGSV_VAL			(OTP_BASE_ADDR + 4 * 0x39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define OTP_TPVSR_VAL			(OTP_BASE_ADDR + 4 * 0x3A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define OTP_TPVHR_VAL			(OTP_BASE_ADDR + 4 * 0x3B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define OTP_TPVSA_VAL			(OTP_BASE_ADDR + 4 * 0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #endif /* _LAN78XX_H */