^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ASIX AX8817X based USB 2.0 Ethernet Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2002-2003 TiVo Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "asix.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PHY_MODE_MARVELL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MII_MARVELL_LED_CTRL 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MII_MARVELL_STATUS 0x001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MII_MARVELL_CTRL 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MARVELL_LED_MANUAL 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MARVELL_STATUS_HWCFG 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MARVELL_CTRL_TXDELAY 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MARVELL_CTRL_RXDELAY 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PHY_MODE_RTL8211CL 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AX88772A_PHY14H 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AX88772A_PHY14H_DEFAULT 0x442C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AX88772A_PHY15H 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AX88772A_PHY15H_DEFAULT 0x03C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AX88772A_PHY16H 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AX88772A_PHY16H_DEFAULT 0x4044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct ax88172_int_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __le16 res1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __le16 res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __le16 res3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void asix_status(struct usbnet *dev, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct ax88172_int_data *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (urb->actual_length < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) event = urb->transfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) link = event->link & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (netif_carrier_ok(dev->net) != link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) usbnet_link_change(dev, link, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) netdev_dbg(dev->net, "Link Status is: %d\n", link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (is_valid_ether_addr(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) memcpy(dev->net->dev_addr, addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) netdev_info(dev->net, "invalid hw address, using random\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) eth_hw_addr_random(dev->net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static u32 asix_get_phyid(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Poll for the rare case the FW or phy isn't ready yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (phy_reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (phy_reg != 0 && phy_reg != 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (phy_reg <= 0 || phy_reg == 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) phy_id = (phy_reg & 0xffff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (phy_reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) phy_id |= (phy_reg & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static u32 asix_get_link(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct usbnet *dev = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return mii_link_ok(&dev->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct usbnet *dev = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* We need to override some ethtool_ops so we require our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) own structure so we don't interfere with other usbnet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) devices that may be connected at the same time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct ethtool_ops ax88172_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .get_drvinfo = asix_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .get_link = asix_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .get_msglevel = usbnet_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .set_msglevel = usbnet_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .get_wol = asix_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .set_wol = asix_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .get_eeprom_len = asix_get_eeprom_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .get_eeprom = asix_get_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .set_eeprom = asix_set_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .nway_reset = usbnet_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .get_link_ksettings = usbnet_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .set_link_ksettings = usbnet_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void ax88172_set_multicast(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct usbnet *dev = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct asix_data *data = (struct asix_data *)&dev->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 rx_ctl = 0x8c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (net->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rx_ctl |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } else if (net->flags & IFF_ALLMULTI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) netdev_mc_count(net) > AX_MAX_MCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rx_ctl |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } else if (netdev_mc_empty(net)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* just broadcast and directed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* We use the 20 byte dev->data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * for our 8 byte filter buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * to avoid allocating memory that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * is tricky to free later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 crc_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Build the multicast hash filter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) netdev_for_each_mc_addr(ha, net) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) data->multi_filter[crc_bits >> 3] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 1 << (crc_bits & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) AX_MCAST_FILTER_SIZE, data->multi_filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rx_ctl |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int ax88172_link_reset(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mii_check_media(&dev->mii, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mii_ethtool_gset(&dev->mii, &ecmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mode = AX88172_MEDIUM_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ecmd.duplex != DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mode |= ~AX88172_MEDIUM_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) asix_write_medium_mode(dev, mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct net_device_ops ax88172_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .ndo_open = usbnet_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .ndo_stop = usbnet_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .ndo_start_xmit = usbnet_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .ndo_tx_timeout = usbnet_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .ndo_change_mtu = usbnet_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .ndo_get_stats64 = usbnet_get_stats64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .ndo_do_ioctl = asix_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .ndo_set_rx_mode = ax88172_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int timeout = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* give phy_id a chance to process reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) & BMCR_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev->mii.phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 buf[ETH_ALEN] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long gpio_bits = dev->driver_info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) usbnet_get_endpoints(dev,intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Toggle the GPIOs in a manufacturer/model specific way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 2; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = asix_write_rx_ctl(dev, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Get the MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0, 0, ETH_ALEN, buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) asix_set_netdev_dev_addr(dev, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Initialize MII structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev->mii.dev = dev->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev->mii.mdio_read = asix_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev->mii.mdio_write = asix_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev->mii.phy_id_mask = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev->mii.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev->mii.phy_id = asix_get_phy_addr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev->net->netdev_ops = &ax88172_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev->net->ethtool_ops = &ax88172_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) asix_phy_reset(dev, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mii_nway_restart(&dev->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct ethtool_ops ax88772_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .get_drvinfo = asix_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .get_link = asix_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .get_msglevel = usbnet_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .set_msglevel = usbnet_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .get_wol = asix_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .set_wol = asix_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .get_eeprom_len = asix_get_eeprom_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .get_eeprom = asix_get_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .set_eeprom = asix_set_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .nway_reset = usbnet_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .get_link_ksettings = usbnet_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .set_link_ksettings = usbnet_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int ax88772_link_reset(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mii_check_media(&dev->mii, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mii_ethtool_gset(&dev->mii, &ecmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mode = AX88772_MEDIUM_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ethtool_cmd_speed(&ecmd) != SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mode &= ~AX_MEDIUM_PS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ecmd.duplex != DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mode &= ~AX_MEDIUM_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) asix_write_medium_mode(dev, mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int ax88772_reset(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct asix_data *data = (struct asix_data *)&dev->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Rewrite MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ether_addr_copy(data->mac_addr, dev->net->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ETH_ALEN, data->mac_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Set RX_CTL to default values with 2k buffer, and enable cactus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct asix_data *data = (struct asix_data *)&dev->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int ret, embd_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u16 rx_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) AX_GPIO_GPO2EN, 5, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 0, 0, NULL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (embd_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MII_PHYSID1))){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Rewrite MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ether_addr_copy(data->mac_addr, dev->net->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ETH_ALEN, data->mac_addr, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Set RX_CTL to default values with 2k buffer, and enable cactus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rx_ctl = asix_read_rx_ctl(dev, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) rx_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) rx_ctl = asix_read_medium_status(dev, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) netdev_dbg(dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "Medium Status is 0x%04x after all initializations\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rx_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct asix_data *data = (struct asix_data *)&dev->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int ret, embd_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u16 rx_ctl, phy14h, phy15h, phy16h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 chipcode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) msleep(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MII_PHYSID1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0, 1, &chipcode, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0, NULL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Check if the PHY registers have default settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) AX88772A_PHY14H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) AX88772A_PHY15H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) AX88772A_PHY16H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) netdev_dbg(dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) phy14h, phy15h, phy16h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Restore PHY registers default setting if not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (phy14h != AX88772A_PHY14H_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) AX88772A_PHY14H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) AX88772A_PHY14H_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (phy15h != AX88772A_PHY15H_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) AX88772A_PHY15H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) AX88772A_PHY15H_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (phy16h != AX88772A_PHY16H_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) AX88772A_PHY16H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) AX88772A_PHY16H_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Rewrite MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) data->mac_addr, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Set RX_CTL to default values with 2k buffer, and enable cactus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Set RX_CTL to default values with 2k buffer, and enable cactus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) rx_ctl = asix_read_rx_ctl(dev, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) rx_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) rx_ctl = asix_read_medium_status(dev, in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) netdev_dbg(dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) "Medium Status is 0x%04x after all initializations\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) rx_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const struct net_device_ops ax88772_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .ndo_open = usbnet_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .ndo_stop = usbnet_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .ndo_start_xmit = usbnet_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .ndo_tx_timeout = usbnet_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .ndo_change_mtu = usbnet_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .ndo_get_stats64 = usbnet_get_stats64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .ndo_set_mac_address = asix_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .ndo_do_ioctl = asix_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .ndo_set_rx_mode = asix_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static void ax88772_suspend(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct asix_common_private *priv = dev->driver_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u16 medium;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Stop MAC operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) medium = asix_read_medium_status(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) medium &= ~AX_MEDIUM_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) asix_write_medium_mode(dev, medium, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) asix_read_medium_status(dev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Preserve BMCR for restoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) priv->presvd_phy_bmcr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Preserve ANAR for restoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) priv->presvd_phy_advertise =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int asix_suspend(struct usb_interface *intf, pm_message_t message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct usbnet *dev = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct asix_common_private *priv = dev->driver_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (priv && priv->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) priv->suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return usbnet_suspend(intf, message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void ax88772_restore_phy(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct asix_common_private *priv = dev->driver_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (priv->presvd_phy_advertise) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Restore Advertisement control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) priv->presvd_phy_advertise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Restore BMCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (priv->presvd_phy_bmcr & BMCR_ANENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) priv->presvd_phy_bmcr |= BMCR_ANRESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) priv->presvd_phy_bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) priv->presvd_phy_advertise = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) priv->presvd_phy_bmcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void ax88772_resume(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!ax88772_hw_reset(dev, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ax88772_restore_phy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void ax88772a_resume(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!ax88772a_hw_reset(dev, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ax88772_restore_phy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int asix_resume(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct usbnet *dev = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct asix_common_private *priv = dev->driver_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (priv && priv->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) priv->resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return usbnet_resume(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 buf[ETH_ALEN] = {0}, chipcode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct asix_common_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) usbnet_get_endpoints(dev, intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Maybe the boot loader passed the MAC address via device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) netif_dbg(dev, ifup, dev->net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "MAC address read from device tree");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Try getting the MAC address from EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (dev->driver_info->data & FLAG_EEPROM_MAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) for (i = 0; i < (ETH_ALEN >> 1); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 0x04 + i, 0, 2, buf + i * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 0, 0, ETH_ALEN, buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) netdev_dbg(dev->net, "Failed to read MAC address: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) asix_set_netdev_dev_addr(dev, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Initialize MII structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev->mii.dev = dev->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev->mii.mdio_read = asix_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev->mii.mdio_write = asix_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev->mii.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev->mii.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev->mii.phy_id = asix_get_phy_addr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev->net->netdev_ops = &ax88772_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev->net->ethtool_ops = &ax88772_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) chipcode &= AX_CHIPCODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ax88772a_hw_reset(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Read PHYID register *AFTER* the PHY was reset properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) phyid = asix_get_phyid(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (dev->driver_info->flags & FLAG_FRAMING_AX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* hard_mtu is still the default - the device does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) jumbo eth frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev->rx_urb_size = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (!dev->driver_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) priv = dev->driver_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) priv->presvd_phy_bmcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) priv->presvd_phy_advertise = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (chipcode == AX_AX88772_CHIPCODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) priv->resume = ax88772_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) priv->suspend = ax88772_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) priv->resume = ax88772a_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) priv->suspend = ax88772_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) asix_rx_fixup_common_free(dev->driver_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) kfree(dev->driver_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const struct ethtool_ops ax88178_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .get_drvinfo = asix_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .get_link = asix_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .get_msglevel = usbnet_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .set_msglevel = usbnet_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .get_wol = asix_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .set_wol = asix_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .get_eeprom_len = asix_get_eeprom_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .get_eeprom = asix_get_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .set_eeprom = asix_set_eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .nway_reset = usbnet_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .get_link_ksettings = usbnet_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .set_link_ksettings = usbnet_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int marvell_phy_init(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct asix_data *data = (struct asix_data *)&dev->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) netdev_dbg(dev->net, "marvell_phy_init()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (data->ledmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) reg = asix_mdio_read(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) MII_MARVELL_LED_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) reg &= 0xf8ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) reg |= (1 + 0x0100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) asix_mdio_write(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) MII_MARVELL_LED_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) reg = asix_mdio_read(dev->net, dev->mii.phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) MII_MARVELL_LED_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) reg &= 0xfc0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int rtl8211cl_phy_init(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct asix_data *data = (struct asix_data *)&dev->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (data->ledmode == 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int marvell_led_status(struct usbnet *dev, u16 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Clear out the center LED bits - 0x03F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) reg &= 0xfc0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) reg |= 0x03e0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) reg |= 0x03b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) reg |= 0x02f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int ax88178_reset(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct asix_data *data = (struct asix_data *)&dev->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __le16 eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int gpio0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 phyid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (eeprom == cpu_to_le16(0xffff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) data->phymode = PHY_MODE_MARVELL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) data->ledmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) gpio0 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) data->phymode = le16_to_cpu(eeprom) & 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) data->ledmode = le16_to_cpu(eeprom) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Power up external GigaPHY through AX88178 GPIO pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) AX_GPIO_GPO1EN, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if ((le16_to_cpu(eeprom) >> 8) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) asix_write_gpio(dev, 0x003c, 30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) asix_write_gpio(dev, 0x001c, 300, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) asix_write_gpio(dev, 0x003c, 30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) netdev_dbg(dev->net, "gpio phymode == 1 path\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* Read PHYID register *AFTER* powering up PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) phyid = asix_get_phyid(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) asix_sw_reset(dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) asix_write_rx_ctl(dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (data->phymode == PHY_MODE_MARVELL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) marvell_phy_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } else if (data->phymode == PHY_MODE_RTL8211CL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rtl8211cl_phy_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ADVERTISE_1000FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) mii_nway_restart(&dev->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Rewrite MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) data->mac_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static int ax88178_link_reset(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct asix_data *data = (struct asix_data *)&dev->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) netdev_dbg(dev->net, "ax88178_link_reset()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mii_check_media(&dev->mii, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) mii_ethtool_gset(&dev->mii, &ecmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mode = AX88178_MEDIUM_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) speed = ethtool_cmd_speed(&ecmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (speed == SPEED_1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mode |= AX_MEDIUM_GM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) else if (speed == SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) mode |= AX_MEDIUM_PS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mode |= AX_MEDIUM_ENCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ecmd.duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mode |= AX_MEDIUM_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mode &= ~AX_MEDIUM_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) speed, ecmd.duplex, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) asix_write_medium_mode(dev, mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) marvell_led_status(dev, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static void ax88178_set_mfb(struct usbnet *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u16 mfb = AX_RX_CTL_MFB_16384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u16 rxctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u16 medium;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int old_rx_urb_size = dev->rx_urb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (dev->hard_mtu < 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dev->rx_urb_size = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) mfb = AX_RX_CTL_MFB_2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) } else if (dev->hard_mtu < 4096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev->rx_urb_size = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mfb = AX_RX_CTL_MFB_4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) } else if (dev->hard_mtu < 8192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev->rx_urb_size = 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) mfb = AX_RX_CTL_MFB_8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) } else if (dev->hard_mtu < 16384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev->rx_urb_size = 16384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) mfb = AX_RX_CTL_MFB_16384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) rxctl = asix_read_rx_ctl(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) medium = asix_read_medium_status(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (dev->net->mtu > 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) medium |= AX_MEDIUM_JFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) medium &= ~AX_MEDIUM_JFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) asix_write_medium_mode(dev, medium, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (dev->rx_urb_size > old_rx_urb_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) usbnet_unlink_rx_urbs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int ax88178_change_mtu(struct net_device *net, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct usbnet *dev = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) int ll_mtu = new_mtu + net->hard_header_len + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if ((ll_mtu % dev->maxpacket) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) net->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev->hard_mtu = net->mtu + net->hard_header_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ax88178_set_mfb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* max qlen depend on hard_mtu and rx_urb_size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) usbnet_update_max_qlen(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct net_device_ops ax88178_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .ndo_open = usbnet_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .ndo_stop = usbnet_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .ndo_start_xmit = usbnet_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .ndo_tx_timeout = usbnet_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .ndo_get_stats64 = usbnet_get_stats64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .ndo_set_mac_address = asix_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .ndo_set_rx_mode = asix_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .ndo_do_ioctl = asix_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .ndo_change_mtu = ax88178_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u8 buf[ETH_ALEN] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) usbnet_get_endpoints(dev,intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Get the MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) asix_set_netdev_dev_addr(dev, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Initialize MII structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev->mii.dev = dev->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dev->mii.mdio_read = asix_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev->mii.mdio_write = asix_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev->mii.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dev->mii.reg_num_mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) dev->mii.supports_gmii = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dev->mii.phy_id = asix_get_phy_addr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev->net->netdev_ops = &ax88178_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev->net->ethtool_ops = &ax88178_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Blink LEDS so users know driver saw dongle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) asix_sw_reset(dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (dev->driver_info->flags & FLAG_FRAMING_AX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* hard_mtu is still the default - the device does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) jumbo eth frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) dev->rx_urb_size = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!dev->driver_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static const struct driver_info ax8817x_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .description = "ASIX AX8817x USB 2.0 Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .bind = ax88172_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .status = asix_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .link_reset = ax88172_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .reset = ax88172_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .flags = FLAG_ETHER | FLAG_LINK_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .data = 0x00130103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const struct driver_info dlink_dub_e100_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .description = "DLink DUB-E100 USB Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .bind = ax88172_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .status = asix_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .link_reset = ax88172_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .reset = ax88172_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .flags = FLAG_ETHER | FLAG_LINK_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .data = 0x009f9d9f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const struct driver_info netgear_fa120_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .description = "Netgear FA-120 USB Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .bind = ax88172_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .status = asix_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .link_reset = ax88172_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .reset = ax88172_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .flags = FLAG_ETHER | FLAG_LINK_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .data = 0x00130103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static const struct driver_info hawking_uf200_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .description = "Hawking UF200 USB Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .bind = ax88172_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .status = asix_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .link_reset = ax88172_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .reset = ax88172_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .flags = FLAG_ETHER | FLAG_LINK_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .data = 0x001f1d1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static const struct driver_info ax88772_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .description = "ASIX AX88772 USB 2.0 Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .bind = ax88772_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .unbind = ax88772_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .status = asix_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .link_reset = ax88772_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .reset = ax88772_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .rx_fixup = asix_rx_fixup_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .tx_fixup = asix_tx_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const struct driver_info ax88772b_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .description = "ASIX AX88772B USB 2.0 Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .bind = ax88772_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .unbind = ax88772_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .status = asix_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .link_reset = ax88772_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .reset = ax88772_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) FLAG_MULTI_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .rx_fixup = asix_rx_fixup_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .tx_fixup = asix_tx_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .data = FLAG_EEPROM_MAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static const struct driver_info ax88178_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .description = "ASIX AX88178 USB 2.0 Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .bind = ax88178_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .unbind = ax88772_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .status = asix_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .link_reset = ax88178_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .reset = ax88178_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) FLAG_MULTI_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .rx_fixup = asix_rx_fixup_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .tx_fixup = asix_tx_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * no-name packaging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * USB device strings are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * 1: Manufacturer: USBLINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * 2: Product: HG20F9 USB2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * 3: Serial: 000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * Appears to be compatible with Asix 88772B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static const struct driver_info hg20f9_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .description = "HG20F9 USB 2.0 Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .bind = ax88772_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .unbind = ax88772_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .status = asix_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .link_reset = ax88772_link_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .reset = ax88772_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) FLAG_MULTI_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .rx_fixup = asix_rx_fixup_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .tx_fixup = asix_tx_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .data = FLAG_EEPROM_MAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static const struct usb_device_id products [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) // Linksys USB200M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) USB_DEVICE (0x077b, 0x2226),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) // Netgear FA120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) USB_DEVICE (0x0846, 0x1040),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .driver_info = (unsigned long) &netgear_fa120_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) // DLink DUB-E100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) USB_DEVICE (0x2001, 0x1a00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .driver_info = (unsigned long) &dlink_dub_e100_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) // Intellinet, ST Lab USB Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) USB_DEVICE (0x0b95, 0x1720),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) // Hawking UF200, TrendNet TU2-ET100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) USB_DEVICE (0x07b8, 0x420a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .driver_info = (unsigned long) &hawking_uf200_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) // Billionton Systems, USB2AR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) USB_DEVICE (0x08dd, 0x90ff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) // Billionton Systems, GUSB2AM-1G-B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) USB_DEVICE(0x08dd, 0x0114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) // ATEN UC210T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) USB_DEVICE (0x0557, 0x2009),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) // Buffalo LUA-U2-KTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) USB_DEVICE (0x0411, 0x003d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) // Buffalo LUA-U2-GT 10/100/1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) USB_DEVICE (0x0411, 0x006e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) USB_DEVICE (0x6189, 0x182d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) USB_DEVICE (0x0df6, 0x0056),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) USB_DEVICE (0x0df6, 0x061c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) // corega FEther USB2-TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) USB_DEVICE (0x07aa, 0x0017),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) // Surecom EP-1427X-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) USB_DEVICE (0x1189, 0x0893),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) // goodway corp usb gwusb2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) USB_DEVICE (0x1631, 0x6200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) // JVC MP-PRX1 Port Replicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) USB_DEVICE (0x04f1, 0x3008),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .driver_info = (unsigned long) &ax8817x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) // Lenovo U2L100P 10/100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) USB_DEVICE (0x17ef, 0x7203),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .driver_info = (unsigned long)&ax88772b_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) // ASIX AX88772B 10/100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) USB_DEVICE (0x0b95, 0x772b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .driver_info = (unsigned long) &ax88772b_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) // ASIX AX88772 10/100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) USB_DEVICE (0x0b95, 0x7720),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) // ASIX AX88178 10/100/1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) USB_DEVICE (0x0b95, 0x1780),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) // Logitec LAN-GTJ/U2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) USB_DEVICE (0x0789, 0x0160),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) // Linksys USB200M Rev 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) USB_DEVICE (0x13b1, 0x0018),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) // 0Q0 cable ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) USB_DEVICE (0x1557, 0x7720),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) // DLink DUB-E100 H/W Ver B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) USB_DEVICE (0x07d1, 0x3c05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) // DLink DUB-E100 H/W Ver B1 Alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) USB_DEVICE (0x2001, 0x3c05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) // DLink DUB-E100 H/W Ver C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) USB_DEVICE (0x2001, 0x1a02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) // Linksys USB1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) USB_DEVICE (0x1737, 0x0039),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) // IO-DATA ETG-US2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) USB_DEVICE (0x04bb, 0x0930),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) // Belkin F5D5055
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) USB_DEVICE(0x050d, 0x5055),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) // Apple USB Ethernet Adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) USB_DEVICE(0x05ac, 0x1402),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) // Cables-to-Go USB Ethernet Adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) USB_DEVICE(0x0b95, 0x772a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) // ABOCOM for pci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) USB_DEVICE(0x14ea, 0xab11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .driver_info = (unsigned long) &ax88178_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) // ASIX 88772a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) USB_DEVICE(0x0db0, 0xa877),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .driver_info = (unsigned long) &ax88772_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) // Asus USB Ethernet Adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) USB_DEVICE (0x0b95, 0x7e2b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .driver_info = (unsigned long)&ax88772b_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* ASIX 88172a demo board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) USB_DEVICE(0x0b95, 0x172a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .driver_info = (unsigned long) &ax88172a_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * USBLINK HG20F9 "USB 2.0 LAN"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * Appears to have gazumped Linksys's manufacturer ID but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * doesn't (yet) conflict with any known Linksys product.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) USB_DEVICE(0x066b, 0x20f9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .driver_info = (unsigned long) &hg20f9_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) { }, // END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) MODULE_DEVICE_TABLE(usb, products);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static struct usb_driver asix_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .id_table = products,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .probe = usbnet_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .suspend = asix_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .resume = asix_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .reset_resume = asix_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .disconnect = usbnet_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .supports_autosuspend = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .disable_hub_initiated_lpm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) module_usb_driver(asix_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) MODULE_AUTHOR("David Hollis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) MODULE_VERSION(DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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