^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ASIX AX8817X based USB 2.0 Ethernet Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2002-2003 TiVo Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _ASIX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _ASIX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) // #define DEBUG // error path messages, extra info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // #define VERBOSE // more; success messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kmod.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb/usbnet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRIVER_VERSION "22-Dec-2011"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_NAME "asix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* ASIX AX8817X based USB 2.0 Ethernet Devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AX_CMD_SET_SW_MII 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AX_CMD_READ_MII_REG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AX_CMD_WRITE_MII_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AX_CMD_STATMNGSTS_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AX_CMD_SET_HW_MII 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AX_CMD_READ_EEPROM 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AX_CMD_WRITE_EEPROM 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AX_CMD_WRITE_ENABLE 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AX_CMD_WRITE_DISABLE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AX_CMD_READ_RX_CTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AX_CMD_WRITE_RX_CTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AX_CMD_READ_IPG012 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AX_CMD_WRITE_IPG0 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AX_CMD_WRITE_IPG1 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AX_CMD_READ_NODE_ID 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AX_CMD_WRITE_NODE_ID 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AX_CMD_WRITE_IPG2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AX_CMD_WRITE_MULTI_FILTER 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AX88172_CMD_READ_NODE_ID 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AX_CMD_READ_PHY_ID 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AX_CMD_READ_MEDIUM_STATUS 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AX_CMD_READ_MONITOR_MODE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AX_CMD_WRITE_MONITOR_MODE 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AX_CMD_READ_GPIOS 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AX_CMD_WRITE_GPIOS 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AX_CMD_SW_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AX_CMD_SW_PHY_STATUS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AX_CMD_SW_PHY_SELECT 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AX_QCTCTRL 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AX_CHIPCODE_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AX_AX88772_CHIPCODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AX_AX88772A_CHIPCODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AX_AX88772B_CHIPCODE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AX_HOST_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AX_PHYSEL_PSEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AX_PHYSEL_SSMII 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AX_PHYSEL_SSEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AX_PHY_SELECT_MASK (BIT(3) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AX_PHY_SELECT_INTERNAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AX_PHY_SELECT_EXTERNAL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AX_MONITOR_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AX_MONITOR_LINK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AX_MONITOR_MAGIC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AX_MONITOR_HSFS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* AX88172 Medium Status Register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AX88172_MEDIUM_FD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AX88172_MEDIUM_TX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AX88172_MEDIUM_FC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AX88172_MEDIUM_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AX_MCAST_FILTER_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AX_MAX_MCAST 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AX_SWRESET_CLEAR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AX_SWRESET_RR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AX_SWRESET_RT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AX_SWRESET_PRTE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AX_SWRESET_PRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AX_SWRESET_BZ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AX_SWRESET_IPRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AX_SWRESET_IPPD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AX88772_IPG0_DEFAULT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AX88772_IPG1_DEFAULT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AX88772_IPG2_DEFAULT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* AX88772 & AX88178 Medium Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AX_MEDIUM_PF 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AX_MEDIUM_JFE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AX_MEDIUM_TFC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AX_MEDIUM_RFC 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AX_MEDIUM_ENCK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AX_MEDIUM_AC 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AX_MEDIUM_FD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AX_MEDIUM_GM 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AX_MEDIUM_SM 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AX_MEDIUM_SBP 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AX_MEDIUM_PS 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AX_MEDIUM_RE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AX88178_MEDIUM_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AX_MEDIUM_RE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AX88772_MEDIUM_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) AX_MEDIUM_TFC | AX_MEDIUM_PS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) AX_MEDIUM_AC | AX_MEDIUM_RE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* AX88772 & AX88178 RX_CTL values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AX_RX_CTL_SO 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AX_RX_CTL_AP 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AX_RX_CTL_AM 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AX_RX_CTL_AB 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AX_RX_CTL_SEP 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AX_RX_CTL_AMALL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AX_RX_CTL_PRO 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AX_RX_CTL_MFB_2048 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AX_RX_CTL_MFB_4096 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AX_RX_CTL_MFB_8192 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AX_RX_CTL_MFB_16384 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* GPIO 0 .. 2 toggles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AX_GPIO_RESERVED 0x40 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AX_EEPROM_MAGIC 0xdeadbeef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AX_EEPROM_LEN 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct asix_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 multi_filter[AX_MCAST_FILTER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 mac_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 phymode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 ledmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct asix_rx_fixup_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct sk_buff *ax_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u16 remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bool split_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct asix_common_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void (*resume)(struct usbnet *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void (*suspend)(struct usbnet *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u16 presvd_phy_advertise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u16 presvd_phy_bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct asix_rx_fixup_info rx_fixup_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) extern const struct driver_info ax88172a_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* ASIX specific flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FLAG_EEPROM_MAC (1UL << 0) /* init device MAC from eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 size, void *data, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u16 size, void *data, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u16 index, u16 size, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int asix_rx_fixup_internal(struct usbnet *dev, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct asix_rx_fixup_info *rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int asix_rx_fixup_common(struct usbnet *dev, struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void asix_rx_fixup_common_free(struct asix_common_private *dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int asix_set_sw_mii(struct usbnet *dev, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int asix_set_hw_mii(struct usbnet *dev, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int asix_read_phy_addr(struct usbnet *dev, int internal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int asix_get_phy_addr(struct usbnet *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int asix_sw_reset(struct usbnet *dev, u8 flags, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 asix_read_rx_ctl(struct usbnet *dev, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int asix_write_rx_ctl(struct usbnet *dev, u16 mode, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u16 asix_read_medium_status(struct usbnet *dev, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int asix_write_medium_mode(struct usbnet *dev, u16 mode, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void asix_set_multicast(struct net_device *net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int asix_mdio_read(struct net_device *netdev, int phy_id, int loc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int asix_mdio_read_nopm(struct net_device *netdev, int phy_id, int loc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int asix_get_eeprom_len(struct net_device *net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int asix_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int asix_set_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void asix_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int asix_set_mac_address(struct net_device *net, void *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #endif /* _ASIX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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