^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Aquantia Corp. Aquantia AQtion USB to 5GbE Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002-2003 TiVo Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017-2018 ASIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2018 Aquantia Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __LINUX_USBNET_AQC111_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __LINUX_USBNET_AQC111_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define URB_SIZE (1024 * 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AQ_MCAST_FILTER_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AQ_MAX_MCAST 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AQ_ACCESS_MAC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AQ_FLASH_PARAMETERS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AQ_PHY_POWER 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AQ_WOL_CFG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AQ_PHY_OPS 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AQ_USB_PHY_SET_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AQ_USB_SET_TIMEOUT 4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Feature. ********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AQ_SUPPORT_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) NETIF_F_HW_VLAN_CTAG_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AQ_SUPPORT_HW_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_FILTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AQ_SUPPORT_VLAN_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) NETIF_F_TSO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* SFR Reg. ********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SFR_GENERAL_STATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SFR_CHIP_STATUS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SFR_RX_CTL 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SFR_RX_CTL_TXPADCRC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SFR_RX_CTL_IPE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SFR_RX_CTL_DROPCRCERR 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SFR_RX_CTL_START 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SFR_RX_CTL_RF_WAK 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SFR_RX_CTL_AP 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SFR_RX_CTL_AM 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SFR_RX_CTL_AB 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SFR_RX_CTL_AMALL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SFR_RX_CTL_PRO 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SFR_RX_CTL_STOP 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SFR_INTER_PACKET_GAP_0 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SFR_NODE_ID 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SFR_MULTI_FILTER_ARRY 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SFR_MEDIUM_STATUS_MODE 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SFR_MEDIUM_XGMIIMODE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SFR_MEDIUM_FULL_DUPLEX 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SFR_MEDIUM_RXFLOW_CTRLEN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SFR_MEDIUM_TXFLOW_CTRLEN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SFR_MEDIUM_JUMBO_EN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SFR_MEDIUM_RECEIVE_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SFR_MONITOR_MODE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SFR_MONITOR_MODE_EPHYRW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SFR_MONITOR_MODE_RWLC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SFR_MONITOR_MODE_RWMP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SFR_MONITOR_MODE_RWWF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SFR_MONITOR_MODE_RW_FLAG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SFR_MONITOR_MODE_PMEPOL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SFR_MONITOR_MODE_PMETYPE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SFR_PHYPWR_RSTCTL 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SFR_PHYPWR_RSTCTL_BZ 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SFR_PHYPWR_RSTCTL_IPRL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SFR_VLAN_ID_ADDRESS 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SFR_VLAN_ID_CONTROL 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SFR_VLAN_CONTROL_WE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SFR_VLAN_CONTROL_RD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SFR_VLAN_CONTROL_VSO 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SFR_VLAN_CONTROL_VFE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SFR_VLAN_ID_DATA0 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SFR_VLAN_ID_DATA1 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SFR_RX_BULKIN_QCTRL 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SFR_RX_BULKIN_QCTRL_TIME 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SFR_RX_BULKIN_QCTRL_IFG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SFR_RX_BULKIN_QCTRL_SIZE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SFR_RX_BULKIN_QTIMR_LOW 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SFR_RX_BULKIN_QTIMR_HIGH 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SFR_RX_BULKIN_QSIZE 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SFR_RX_BULKIN_QIFG 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SFR_RXCOE_CTL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SFR_RXCOE_IP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SFR_RXCOE_TCP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SFR_RXCOE_UDP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SFR_RXCOE_ICMP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SFR_RXCOE_IGMP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SFR_RXCOE_TCPV6 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SFR_RXCOE_UDPV6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SFR_RXCOE_ICMV6 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SFR_TXCOE_CTL 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SFR_TXCOE_IP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SFR_TXCOE_TCP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SFR_TXCOE_UDP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SFR_TXCOE_ICMP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SFR_TXCOE_IGMP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SFR_TXCOE_TCPV6 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SFR_TXCOE_UDPV6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SFR_TXCOE_ICMV6 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SFR_BM_INT_MASK 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SFR_BMRX_DMA_CONTROL 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SFR_BMRX_DMA_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SFR_BMTX_DMA_CONTROL 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SFR_PAUSE_WATERLVL_LOW 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SFR_PAUSE_WATERLVL_HIGH 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SFR_ARC_CTRL 0x9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SFR_SWP_CTRL 0xB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SFR_TX_PAUSE_RESEND_T 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SFR_ETH_MAC_PATH 0xB7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SFR_RX_PATH_READY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SFR_BULK_OUT_CTRL 0xB9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SFR_BULK_OUT_FLUSH_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SFR_BULK_OUT_EFF_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AQ_FW_VER_MAJOR 0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AQ_FW_VER_MINOR 0xDB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AQ_FW_VER_REV 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*PHY_OPS**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AQ_ADV_100M BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AQ_ADV_1G BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AQ_ADV_2G5 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AQ_ADV_5G BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AQ_ADV_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AQ_PAUSE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AQ_ASYM_PAUSE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AQ_LOW_POWER BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AQ_PHY_POWER_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AQ_WOL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AQ_DOWNSHIFT BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AQ_DSH_RETRIES_SHIFT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AQ_DSH_RETRIES_MASK 0xF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AQ_WOL_FLAG_MP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct aqc111_wol_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 hw_addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 rsvd[283];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define WOL_CFG_SIZE sizeof(struct aqc111_wol_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct aqc111_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u16 rxctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 rx_checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 link_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 advertised_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 wol_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AQ_LS_MASK 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AQ_SPEED_MASK 0x7F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AQ_SPEED_SHIFT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AQ_INT_SPEED_5G 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AQ_INT_SPEED_2_5G 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AQ_INT_SPEED_1G 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AQ_INT_SPEED_100M 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* TX Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AQ_TX_DESC_LEN_MASK 0x1FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AQ_TX_DESC_DROP_PADD BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AQ_TX_DESC_VLAN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AQ_TX_DESC_MSS_MASK 0x7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AQ_TX_DESC_MSS_SHIFT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AQ_TX_DESC_VLAN_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AQ_TX_DESC_VLAN_SHIFT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AQ_RX_HW_PAD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* RX Packet Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AQ_RX_PD_L4_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AQ_RX_PD_L3_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AQ_RX_PD_L4_TYPE_MASK 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AQ_RX_PD_L4_UDP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AQ_RX_PD_L4_TCP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AQ_RX_PD_L3_TYPE_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AQ_RX_PD_L3_IP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AQ_RX_PD_L3_IP6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AQ_RX_PD_VLAN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AQ_RX_PD_RX_OK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AQ_RX_PD_DROP BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AQ_RX_PD_LEN_MASK 0x7FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AQ_RX_PD_LEN_SHIFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AQ_RX_PD_VLAN_SHIFT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* RX Descriptor header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AQ_RX_DH_PKT_CNT_MASK 0x1FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AQ_RX_DH_DESC_OFFSET_MASK 0xFFFFE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AQ_RX_DH_DESC_OFFSET_SHIFT 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned char ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned char timer_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned char timer_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned char size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned char ifg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } AQC111_BULKIN_SIZE[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* xHCI & EHCI & OHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {7, 0x00, 0x01, 0x1E, 0xFF},/* 10G, 5G, 2.5G, 1G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {7, 0xA0, 0x00, 0x14, 0x00},/* 100M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Jumbo packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {7, 0x00, 0x01, 0x18, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif /* __LINUX_USBNET_AQC111_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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