^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Xilinx GMII2RGMII Converter driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Kedareswara rao Appana <appanad@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This driver is developed for Xilinx GMII2RGMII Converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define XILINX_GMII2RGMII_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define XILINX_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct gmii2rgmii {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct phy_device *phy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct phy_driver *phy_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct phy_driver conv_phy_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mdio_device *mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int xgmiitorgmii_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct gmii2rgmii *priv = mdiodev_get_drvdata(&phydev->mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct mii_bus *bus = priv->mdio->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int addr = priv->mdio->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u16 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (priv->phy_drv->read_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) err = priv->phy_drv->read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) err = genphy_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) val = mdiobus_read(bus, addr, XILINX_GMII2RGMII_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) val &= ~XILINX_GMII2RGMII_SPEED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (phydev->speed == SPEED_1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) val |= BMCR_SPEED1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) else if (phydev->speed == SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) val |= BMCR_SPEED100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) val |= BMCR_SPEED10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mdiobus_write(bus, addr, XILINX_GMII2RGMII_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int xgmiitorgmii_probe(struct mdio_device *mdiodev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device *dev = &mdiodev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device_node *np = dev->of_node, *phy_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct gmii2rgmii *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) phy_node = of_parse_phandle(np, "phy-handle", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!phy_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(dev, "Couldn't parse phy-handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) priv->phy_dev = of_phy_find_device(phy_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) of_node_put(phy_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!priv->phy_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_info(dev, "Couldn't find phydev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!priv->phy_dev->drv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_info(dev, "Attached phy not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) priv->mdio = mdiodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) priv->phy_drv = priv->phy_dev->drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) memcpy(&priv->conv_phy_drv, priv->phy_dev->drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) sizeof(struct phy_driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) priv->conv_phy_drv.read_status = xgmiitorgmii_read_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mdiodev_set_drvdata(&priv->phy_dev->mdio, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) priv->phy_dev->drv = &priv->conv_phy_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct of_device_id xgmiitorgmii_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .compatible = "xlnx,gmii-to-rgmii-1.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_DEVICE_TABLE(of, xgmiitorgmii_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct mdio_driver xgmiitorgmii_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .probe = xgmiitorgmii_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .mdiodrv.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "xgmiitorgmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .of_match_table = xgmiitorgmii_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mdio_module_driver(xgmiitorgmii_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODULE_DESCRIPTION("Xilinx GMII2RGMII converter driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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