^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Vitesse PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Kriston Carson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Vitesse Extended Page Magic Register(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MII_VSC82X4_EXT_PAGE_16E 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MII_VSC82X4_EXT_PAGE_17E 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MII_VSC82X4_EXT_PAGE_18E 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Vitesse Extended Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MII_VSC8244_EXT_CON1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MII_VSC8244_EXTCON1_INIT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Vitesse Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MII_VSC8244_IMASK 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MII_VSC8244_IMASK_IEN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MII_VSC8244_IMASK_SPEED 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MII_VSC8244_IMASK_LINK 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MII_VSC8244_IMASK_DUPLEX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MII_VSC8244_IMASK_MASK 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MII_VSC8221_IMASK_MASK 0xa000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Vitesse Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MII_VSC8244_ISTAT 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MII_VSC8244_ISTAT_STATUS 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MII_VSC8244_ISTAT_SPEED 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MII_VSC8244_ISTAT_LINK 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MII_VSC8244_ISTAT_DUPLEX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Vitesse Auxiliary Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MII_VSC8244_AUX_CONSTAT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MII_VSC8244_AUXCONSTAT_INIT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MII_VSC8244_AUXCONSTAT_100 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Vitesse Extended Page Access Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Vitesse VSC8601 Extended PHY Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MII_VSC8601_EPHY_CTL 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PHY_ID_VSC8234 0x000fc620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PHY_ID_VSC8244 0x000fc6c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PHY_ID_VSC8572 0x000704d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_ID_VSC8601 0x00070420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PHY_ID_VSC7385 0x00070450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_ID_VSC7388 0x00070480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_ID_VSC7395 0x00070550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PHY_ID_VSC7398 0x00070580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_ID_VSC8662 0x00070660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PHY_ID_VSC8221 0x000fc550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PHY_ID_VSC8211 0x000fc4b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MODULE_DESCRIPTION("Vitesse PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_AUTHOR("Kriston Carson");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int vsc824x_add_skew(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int extcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (extcon < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return extcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MII_VSC8244_EXTCON1_RX_SKEW_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MII_VSC8244_EXTCON1_RX_SKEW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int vsc824x_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MII_VSC8244_AUXCONSTAT_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) err = vsc824x_add_skew(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VSC73XX_EXT_PAGE_ACCESS 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int vsc73xx_read_page(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return __phy_read(phydev, VSC73XX_EXT_PAGE_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int vsc73xx_write_page(struct phy_device *phydev, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return __phy_write(phydev, VSC73XX_EXT_PAGE_ACCESS, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void vsc73xx_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Receiver init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) phy_modify(phydev, 0x0c, 0x0300, 0x0200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) phy_write(phydev, 0x1f, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Config LEDs 0x61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int vsc738x_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u16 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* This magic sequence appear in the application note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * "VSC7385/7388 PHY Configuration".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Maybe one day we will get to know what it all means.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) phy_modify(phydev, 0x08, 0x0200, 0x0200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) phy_write(phydev, 0x1f, 0x52b5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) phy_write(phydev, 0x10, 0xb68a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) phy_modify(phydev, 0x12, 0xff07, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) phy_modify(phydev, 0x11, 0x00ff, 0x00a2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) phy_write(phydev, 0x10, 0x968a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) phy_modify(phydev, 0x08, 0x0200, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) phy_write(phydev, 0x1f, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Read revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rev = phy_read(phydev, MII_PHYSID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rev &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Special quirk for revision 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (rev == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) phy_modify(phydev, 0x08, 0x0200, 0x0200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) phy_write(phydev, 0x1f, 0x52b5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) phy_write(phydev, 0x12, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) phy_write(phydev, 0x11, 0x0689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) phy_write(phydev, 0x10, 0x8f92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) phy_write(phydev, 0x1f, 0x52b5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) phy_write(phydev, 0x12, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) phy_write(phydev, 0x11, 0x0e35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) phy_write(phydev, 0x10, 0x9786);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) phy_modify(phydev, 0x08, 0x0200, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) phy_write(phydev, 0x17, 0xff80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) phy_write(phydev, 0x17, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) phy_write(phydev, 0x1f, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) phy_write(phydev, 0x12, 0x0048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (rev == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) phy_write(phydev, 0x14, 0x6600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) phy_write(phydev, 0x1f, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) phy_write(phydev, 0x18, 0xa24e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) phy_modify(phydev, 0x16, 0x0fc0, 0x0240);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) phy_modify(phydev, 0x14, 0x6000, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* bits 14-15 in extended register 0x14 controls DACG amplitude
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * 6 = -8%, 2 is hardware default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) phy_write(phydev, 0x1f, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) phy_modify(phydev, 0x14, 0xe000, 0x6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) phy_write(phydev, 0x1f, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) vsc73xx_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int vsc739x_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* This magic sequence appears in the VSC7395 SparX-G5e application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * note "VSC7395/VSC7398 PHY Configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Maybe one day we will get to know what it all means.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) phy_modify(phydev, 0x08, 0x0200, 0x0200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) phy_write(phydev, 0x1f, 0x52b5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) phy_write(phydev, 0x10, 0xb68a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) phy_modify(phydev, 0x12, 0xff07, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) phy_modify(phydev, 0x11, 0x00ff, 0x00a2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) phy_write(phydev, 0x10, 0x968a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) phy_modify(phydev, 0x08, 0x0200, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) phy_write(phydev, 0x1f, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) phy_write(phydev, 0x1f, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) phy_write(phydev, 0x12, 0x0048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) phy_write(phydev, 0x1f, 0x2a30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) phy_modify(phydev, 0x16, 0x0fc0, 0x0240);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) phy_modify(phydev, 0x14, 0x6000, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) phy_write(phydev, 0x1f, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) phy_modify(phydev, 0x14, 0xe000, 0x6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) phy_write(phydev, 0x1f, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) vsc73xx_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int vsc73xx_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* The VSC73xx switches does not like to be instructed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * do autonegotiation in any way, it prefers that you just go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * with the power-on/reset defaults. Writing some registers will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * just make autonegotiation permanently fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* This adds a skew for both TX and RX clocks, so the skew should only be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * applied to "rgmii-id" interfaces. It may not work as expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int vsc8601_add_skew(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = phy_read(phydev, MII_VSC8601_EPHY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int vsc8601_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = vsc8601_add_skew(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int vsc824x_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Don't bother to ACK the interrupts if interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * are disabled. The 824x cannot clear the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * if they are disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) err = phy_read(phydev, MII_VSC8244_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return (err < 0) ? err : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int vsc82xx_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err = phy_write(phydev, MII_VSC8244_IMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) (phydev->drv->phy_id == PHY_ID_VSC8234 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) phydev->drv->phy_id == PHY_ID_VSC8244 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) phydev->drv->phy_id == PHY_ID_VSC8572 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) phydev->drv->phy_id == PHY_ID_VSC8601) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MII_VSC8244_IMASK_MASK :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MII_VSC8221_IMASK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* The Vitesse PHY cannot clear the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * once it has disabled them, so we clear them first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) err = phy_read(phydev, MII_VSC8244_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) err = phy_write(phydev, MII_VSC8244_IMASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int vsc8221_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MII_VSC8221_AUXCONSTAT_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Perhaps we should set EXT_CON1 based on the interface?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Options are 802.3Z SerDes or SGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * @phydev: target phy_device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * special values in the VSC8234/VSC8244 extended reserved registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int vsc82x4_config_autocross_enable(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* map extended registers set 0x10 - 0x1e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* map standard registers set 0x10 - 0x1e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* vsc82x4_config_aneg - restart auto-negotiation or write BMCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @phydev: target phy_device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Description: If auto-negotiation is enabled, we configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * advertising, and then restart auto-negotiation. If it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * enabled, then we write the BMCR and also start the auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * MDI/MDI-X feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int vsc82x4_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * writing special values in the VSC8234 extended reserved registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = genphy_setup_forced(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret < 0) /* error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return vsc82x4_config_autocross_enable(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Vitesse 82xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct phy_driver vsc82xx_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .phy_id = PHY_ID_VSC8234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "Vitesse VSC8234",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .config_init = &vsc824x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .config_aneg = &vsc82x4_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .ack_interrupt = &vsc824x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .config_intr = &vsc82xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .phy_id = PHY_ID_VSC8244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = "Vitesse VSC8244",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .phy_id_mask = 0x000fffc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .config_init = &vsc824x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .config_aneg = &vsc82x4_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .ack_interrupt = &vsc824x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .config_intr = &vsc82xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .phy_id = PHY_ID_VSC8572,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "Vitesse VSC8572",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .config_init = &vsc824x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .config_aneg = &vsc82x4_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .ack_interrupt = &vsc824x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .config_intr = &vsc82xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .phy_id = PHY_ID_VSC8601,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .name = "Vitesse VSC8601",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .config_init = &vsc8601_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .ack_interrupt = &vsc824x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .config_intr = &vsc82xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .phy_id = PHY_ID_VSC7385,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "Vitesse VSC7385",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .config_init = vsc738x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .config_aneg = vsc73xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .read_page = vsc73xx_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .write_page = vsc73xx_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .phy_id = PHY_ID_VSC7388,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .name = "Vitesse VSC7388",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .config_init = vsc738x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .config_aneg = vsc73xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .read_page = vsc73xx_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .write_page = vsc73xx_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .phy_id = PHY_ID_VSC7395,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .name = "Vitesse VSC7395",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .config_init = vsc739x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .config_aneg = vsc73xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .read_page = vsc73xx_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .write_page = vsc73xx_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .phy_id = PHY_ID_VSC7398,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .name = "Vitesse VSC7398",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .config_init = vsc739x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .config_aneg = vsc73xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .read_page = vsc73xx_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .write_page = vsc73xx_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .phy_id = PHY_ID_VSC8662,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .name = "Vitesse VSC8662",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .config_init = &vsc824x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .config_aneg = &vsc82x4_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .ack_interrupt = &vsc824x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .config_intr = &vsc82xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Vitesse 8221 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .phy_id = PHY_ID_VSC8221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .name = "Vitesse VSC8221",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .config_init = &vsc8221_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .ack_interrupt = &vsc824x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .config_intr = &vsc82xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Vitesse 8211 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .phy_id = PHY_ID_VSC8211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "Vitesse VSC8211",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .config_init = &vsc8221_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .ack_interrupt = &vsc824x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .config_intr = &vsc82xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) module_phy_driver(vsc82xx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { PHY_ID_VSC8234, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { PHY_ID_VSC8244, 0x000fffc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { PHY_ID_VSC8572, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { PHY_ID_VSC7385, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { PHY_ID_VSC7388, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { PHY_ID_VSC7395, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { PHY_ID_VSC7398, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { PHY_ID_VSC8662, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { PHY_ID_VSC8221, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { PHY_ID_VSC8211, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MODULE_DEVICE_TABLE(mdio, vitesse_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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