^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPI driver for Micrel/Kendin KS8995M and KSZ8864RMN ethernet switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Gabor Juhos <juhosg at openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file was based on: drivers/spi/at25.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_VERSION "0.1.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRV_DESC "Micrel KS8995 Ethernet switch SPI driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define KS8995_REG_ID0 0x00 /* Chip ID0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define KS8995_REG_ID1 0x01 /* Chip ID1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define KS8995_REG_GC0 0x02 /* Global Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define KS8995_REG_GC1 0x03 /* Global Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define KS8995_REG_GC2 0x04 /* Global Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define KS8995_REG_GC3 0x05 /* Global Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define KS8995_REG_GC4 0x06 /* Global Control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define KS8995_REG_GC5 0x07 /* Global Control 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define KS8995_REG_GC6 0x08 /* Global Control 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define KS8995_REG_GC7 0x09 /* Global Control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define KS8995_REG_GC8 0x0a /* Global Control 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define KS8995_REG_GC9 0x0b /* Global Control 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define KS8995_REG_PC(p, r) ((0x10 * p) + r) /* Port Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define KS8995_REG_PS(p, r) ((0x10 * p) + r + 0xe) /* Port Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define KS8995_REG_TPC0 0x60 /* TOS Priority Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define KS8995_REG_TPC1 0x61 /* TOS Priority Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define KS8995_REG_TPC2 0x62 /* TOS Priority Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define KS8995_REG_TPC3 0x63 /* TOS Priority Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define KS8995_REG_TPC4 0x64 /* TOS Priority Control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define KS8995_REG_TPC5 0x65 /* TOS Priority Control 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define KS8995_REG_TPC6 0x66 /* TOS Priority Control 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define KS8995_REG_TPC7 0x67 /* TOS Priority Control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define KS8995_REG_MAC0 0x68 /* MAC address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define KS8995_REG_MAC1 0x69 /* MAC address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define KS8995_REG_MAC2 0x6a /* MAC address 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define KS8995_REG_MAC3 0x6b /* MAC address 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define KS8995_REG_MAC4 0x6c /* MAC address 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define KS8995_REG_MAC5 0x6d /* MAC address 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define KS8995_REG_IAC0 0x6e /* Indirect Access Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define KS8995_REG_IAC1 0x6f /* Indirect Access Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define KS8995_REG_IAD7 0x70 /* Indirect Access Data 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define KS8995_REG_IAD6 0x71 /* Indirect Access Data 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define KS8995_REG_IAD5 0x72 /* Indirect Access Data 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define KS8995_REG_IAD4 0x73 /* Indirect Access Data 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define KS8995_REG_IAD3 0x74 /* Indirect Access Data 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define KS8995_REG_IAD2 0x75 /* Indirect Access Data 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define KS8995_REG_IAD1 0x76 /* Indirect Access Data 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define KS8995_REG_IAD0 0x77 /* Indirect Access Data 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define KSZ8864_REG_ID1 0xfe /* Chip ID in bit 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define KS8995_REGS_SIZE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define KSZ8864_REGS_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define KSZ8795_REGS_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ID1_CHIPID_M 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ID1_CHIPID_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ID1_REVISION_M 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ID1_REVISION_S 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ID1_START_SW 1 /* start the switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FAMILY_KS8995 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FAMILY_KSZ8795 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CHIPID_M 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define KS8995_CHIP_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define KSZ8864_CHIP_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define KSZ8795_CHIP_ID 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define KS8995_CMD_WRITE 0x02U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define KS8995_CMD_READ 0x03U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define KS8995_RESET_DELAY 10 /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum ks8995_chip_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ks8995,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ksz8864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ksz8795,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) max_variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ks8995_chip_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int family_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int addr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct ks8995_chip_params ks8995_chip[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [ks8995] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "KS8995MA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .family_id = FAMILY_KS8995,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .chip_id = KS8995_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .regs_size = KS8995_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .addr_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .addr_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [ksz8864] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "KSZ8864RMN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .family_id = FAMILY_KS8995,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .chip_id = KSZ8864_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .regs_size = KSZ8864_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .addr_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .addr_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [ksz8795] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "KSZ8795CLX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .family_id = FAMILY_KSZ8795,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .chip_id = KSZ8795_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .regs_size = KSZ8795_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .addr_width = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .addr_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ks8995_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum of_gpio_flags reset_gpio_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ks8995_switch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct ks8995_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct bin_attribute regs_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct ks8995_chip_params *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int revision_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct spi_device_id ks8995_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {"ks8995", ks8995},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {"ksz8864", ksz8864},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {"ksz8795", ksz8795},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MODULE_DEVICE_TABLE(spi, ks8995_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct of_device_id ks8895_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .compatible = "micrel,ks8995" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .compatible = "micrel,ksz8864" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { .compatible = "micrel,ksz8795" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MODULE_DEVICE_TABLE(of, ks8895_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline u8 get_chip_id(u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return (val >> ID1_CHIPID_S) & ID1_CHIPID_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline u8 get_chip_rev(u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return (val >> ID1_REVISION_S) & ID1_REVISION_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* create_spi_cmd - create a chip specific SPI command header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @ks: pointer to switch instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @cmd: SPI command for switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @address: register address for command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Different chip families use different bit pattern to address the switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * KS8995: 8bit command + 8bit address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * KSZ8795: 3bit command + 12bit address + 1bit TR (?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline __be16 create_spi_cmd(struct ks8995_switch *ks, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u16 result = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* make room for address (incl. address shift) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) result <<= ks->chip->addr_width + ks->chip->addr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* add address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) result |= address << ks->chip->addr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* SPI protocol needs big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return cpu_to_be16(result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int ks8995_read(struct ks8995_switch *ks, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned offset, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __be16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct spi_transfer t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cmd = create_spi_cmd(ks, KS8995_CMD_READ, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) memset(&t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) t[0].tx_buf = &cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) t[0].len = sizeof(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) t[1].rx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) t[1].len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mutex_lock(&ks->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) err = spi_sync(ks->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mutex_unlock(&ks->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return err ? err : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int ks8995_write(struct ks8995_switch *ks, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned offset, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __be16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct spi_transfer t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cmd = create_spi_cmd(ks, KS8995_CMD_WRITE, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) memset(&t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) t[0].tx_buf = &cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) t[0].len = sizeof(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) t[1].tx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) t[1].len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mutex_lock(&ks->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) err = spi_sync(ks->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mutex_unlock(&ks->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return err ? err : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static inline int ks8995_read_reg(struct ks8995_switch *ks, u8 addr, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ks8995_read(ks, buf, addr, 1) != 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline int ks8995_write_reg(struct ks8995_switch *ks, u8 addr, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) char buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ks8995_write(ks, &buf, addr, 1) != 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int ks8995_stop(struct ks8995_switch *ks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ks8995_write_reg(ks, KS8995_REG_ID1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int ks8995_start(struct ks8995_switch *ks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ks8995_write_reg(ks, KS8995_REG_ID1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int ks8995_reset(struct ks8995_switch *ks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err = ks8995_stop(ks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) udelay(KS8995_RESET_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ks8995_start(ks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static ssize_t ks8995_registers_read(struct file *filp, struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct ks8995_switch *ks8995;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ks8995 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ks8995_read(ks8995, buf, off, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static ssize_t ks8995_registers_write(struct file *filp, struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct ks8995_switch *ks8995;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ks8995 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ks8995_write(ks8995, buf, off, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* ks8995_get_revision - get chip revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @ks: pointer to switch instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Verify chip family and id and get chip revision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int ks8995_get_revision(struct ks8995_switch *ks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 id0, id1, ksz8864_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* read family id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) err = ks8995_read_reg(ks, KS8995_REG_ID0, &id0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* verify family id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (id0 != ks->chip->family_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(&ks->spi->dev, "chip family id mismatch: expected 0x%02x but 0x%02x read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ks->chip->family_id, id0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) switch (ks->chip->family_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case FAMILY_KS8995:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* try reading chip id at CHIP ID1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) err = ks8995_read_reg(ks, KS8995_REG_ID1, &id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* verify chip id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if ((get_chip_id(id1) == CHIPID_M) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (get_chip_id(id1) == ks->chip->chip_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* KS8995MA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ks->revision_id = get_chip_rev(id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } else if (get_chip_id(id1) != CHIPID_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* KSZ8864RMN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) err = ks8995_read_reg(ks, KS8995_REG_ID1, &ksz8864_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if ((ksz8864_id & 0x80) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (ks->chip->chip_id == KSZ8864_CHIP_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ks->revision_id = get_chip_rev(id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(&ks->spi->dev, "unsupported chip id for KS8995 family: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case FAMILY_KSZ8795:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* try reading chip id at CHIP ID1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) err = ks8995_read_reg(ks, KS8995_REG_ID1, &id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (get_chip_id(id1) == ks->chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ks->revision_id = get_chip_rev(id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(&ks->spi->dev, "unsupported chip id for KSZ8795 family: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(&ks->spi->dev, "unsupported family id: 0x%02x\n", id0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* ks8995_parse_dt - setup platform data from devicetree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @ks: pointer to switch instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Parses supported DT properties and sets up platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void ks8995_parse_dt(struct ks8995_switch *ks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct device_node *np = ks->spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct ks8995_pdata *pdata = ks->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pdata->reset_gpio = of_get_named_gpio_flags(np, "reset-gpios", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) &pdata->reset_gpio_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct bin_attribute ks8995_registers_attr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .attr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = "registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .mode = 0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .size = KS8995_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .read = ks8995_registers_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .write = ks8995_registers_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int ks8995_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct ks8995_switch *ks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int variant = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (variant >= max_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(&spi->dev, "bad chip variant %d\n", variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ks = devm_kzalloc(&spi->dev, sizeof(*ks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!ks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mutex_init(&ks->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ks->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ks->chip = &ks8995_chip[variant];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ks->spi->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ks->pdata = devm_kzalloc(&spi->dev, sizeof(*ks->pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!ks->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ks->pdata->reset_gpio = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ks8995_parse_dt(ks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!ks->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ks->pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* de-assert switch reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ks->pdata && gpio_is_valid(ks->pdata->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) flags = (ks->pdata->reset_gpio_flags == OF_GPIO_ACTIVE_LOW ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GPIOF_ACTIVE_LOW : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) err = devm_gpio_request_one(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ks->pdata->reset_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) flags, "switch-reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "failed to get reset-gpios: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) gpiod_set_value(gpio_to_desc(ks->pdata->reset_gpio), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spi_set_drvdata(spi, ks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) spi->mode = SPI_MODE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) err = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(&spi->dev, "spi_setup failed, err=%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err = ks8995_get_revision(ks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) memcpy(&ks->regs_attr, &ks8995_registers_attr, sizeof(ks->regs_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ks->regs_attr.size = ks->chip->regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) err = ks8995_reset(ks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) sysfs_attr_init(&ks->regs_attr.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err = sysfs_create_bin_file(&spi->dev.kobj, &ks->regs_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(&spi->dev, "unable to create sysfs file, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_info(&spi->dev, "%s device found, Chip ID:%x, Revision:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ks->chip->name, ks->chip->chip_id, ks->revision_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int ks8995_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct ks8995_switch *ks = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sysfs_remove_bin_file(&spi->dev.kobj, &ks->regs_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ks->pdata && gpio_is_valid(ks->pdata->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) gpiod_set_value(gpio_to_desc(ks->pdata->reset_gpio), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct spi_driver ks8995_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "spi-ks8995",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .of_match_table = of_match_ptr(ks8895_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .probe = ks8995_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .remove = ks8995_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .id_table = ks8995_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) module_spi_driver(ks8995_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_DESCRIPTION(DRV_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MODULE_AUTHOR("Gabor Juhos <juhosg at openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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