^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/net/phy/rockchip.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for ROCKCHIP Ethernet PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * David Wu <david.wu@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define INTERNAL_EPHY_ID 0x1234d400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MII_INTERNAL_CTRL_STATUS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SMI_ADDR_TSTCNTL 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SMI_ADDR_TSTREAD1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SMI_ADDR_TSTREAD2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SMI_ADDR_TSTWRITE 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MII_SPECIAL_CONTROL_STATUS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MII_AUTO_MDIX_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MII_MDIX_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MII_SPEED_10 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MII_SPEED_100 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TSTCNTL_RD (BIT(15) | BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TSTCNTL_WR (BIT(14) | BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TSTMODE_ENABLE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TSTMODE_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WR_ADDR_A7CFG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int rockchip_init_tstmode(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Enable access to Analog and DSP register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int rockchip_close_tstmode(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Back to basic register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int rockchip_integrated_phy_analog_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = rockchip_init_tstmode(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Adjust tx amplitude to make sginal better,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * the default value is 0x8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return rockchip_close_tstmode(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int rockchip_integrated_phy_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * The auto MIDX has linked problem on some board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * workround to disable auto MDIX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val &= ~MII_AUTO_MDIX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return rockchip_integrated_phy_analog_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void rockchip_link_change_notify(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * If mode switch happens from 10BT to 100BT, all DSP/AFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * registers are set to default values. So any AFE/DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * registers have to be re-initialized in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (phydev->state == PHY_RUNNING && phydev->speed == SPEED_100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret = rockchip_integrated_phy_analog_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int rockchip_set_polarity(struct phy_device *phydev, int polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int reg, err, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* get the current settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg &= ~MII_AUTO_MDIX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) switch (polarity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case ETH_TP_MDI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) val &= ~MII_MDIX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case ETH_TP_MDI_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val |= MII_MDIX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case ETH_TP_MDI_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case ETH_TP_MDI_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (val != reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Set the new polarity value in the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int rockchip_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) err = rockchip_set_polarity(phydev, phydev->mdix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int rockchip_phy_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) genphy_resume(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return rockchip_integrated_phy_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct phy_driver rockchip_phy_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .phy_id = INTERNAL_EPHY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "Rockchip integrated EPHY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .link_change_notify = rockchip_link_change_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .soft_reset = genphy_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .config_init = rockchip_integrated_phy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .config_aneg = rockchip_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .resume = rockchip_phy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) module_phy_driver(rockchip_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { INTERNAL_EPHY_ID, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_AUTHOR("David Wu <david.wu@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_DESCRIPTION("Rockchip Ethernet PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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