^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Driver for ROCKCHIP RK630 Ethernet PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2020, Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * David Wu <david.wu@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/wakelock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RK630_PHY_ID 0x00441400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* PAGE 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_MMD_ACCESS_CONTROL 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_MMD_ACCESS_DATA_ADDRESS 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_INTERRUPT_STATUS 0X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_INTERRUPT_MASK 0X11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_GLOBAL_CONFIGURATION 0X13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_MAC_ADDRESS0 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_MAC_ADDRESS1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_MAC_ADDRESS2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_PAGE_SEL 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* PAGE 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_PAGE1_APS_CTRL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_PAGE1_UAPS_CONFIGURE 0X13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_PAGE1_EEE_CONFIGURE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* PAGE 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_PAGE2_AFE_CTRL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* PAGE 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_PAGE6_ADC_ANONTROL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_PAGE6_GAIN_ANONTROL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_PAGE6_AFE_RX_CTRL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_PAGE6_AFE_TX_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_PAGE6_AFE_DRIVER2 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_PAGE6_CP_CURRENT 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_PAGE6_ADC_OP_BIAS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_PAGE6_RX_DECTOR 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_PAGE6_AFE_PDCW 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* PAGE 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_PAGE8_AFE_CTRL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_PAGE8_AUTO_CAL 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Fixed address:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Addr: 1 --- RK630@S40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 2 --- RV1106@T22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_ADDR_S40 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_ADDR_T22 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define T22_TX_LEVEL_100M 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define T22_TX_LEVEL_10M 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct rk630_phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct phy_device *phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bool ieee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int wol_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct wake_lock wol_wake_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int tx_level_100M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int tx_level_10M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void rk630_phy_t22_get_tx_level_from_efuse(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct rk630_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int tx_level_100M = T22_TX_LEVEL_100M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int tx_level_10M = T22_TX_LEVEL_10M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned char *efuse_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) cell = nvmem_cell_get(&phydev->mdio.dev, "txlevel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (IS_ERR(cell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) phydev_err(phydev, "failed to get txlevel cell: %ld, use default\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PTR_ERR(cell));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) efuse_buf = nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!IS_ERR(efuse_buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (len == 2 && efuse_buf[0] > 0 && efuse_buf[1] > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tx_level_100M = efuse_buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tx_level_10M = efuse_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) kfree(efuse_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) phydev_err(phydev, "failed to get efuse buf, use default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) priv->tx_level_100M = tx_level_100M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) priv->tx_level_10M = tx_level_10M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void rk630_phy_wol_enable(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct net_device *ndev = phydev->attached_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Switch to page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) phy_write(phydev, REG_PAGE_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) phy_write(phydev, REG_MAC_ADDRESS0, ((u16)ndev->dev_addr[0] << 8) + ndev->dev_addr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) phy_write(phydev, REG_MAC_ADDRESS1, ((u16)ndev->dev_addr[2] << 8) + ndev->dev_addr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) phy_write(phydev, REG_MAC_ADDRESS2, ((u16)ndev->dev_addr[4] << 8) + ndev->dev_addr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) value = phy_read(phydev, REG_GLOBAL_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) value |= BIT(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) value &= ~BIT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) value |= BIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) phy_write(phydev, REG_GLOBAL_CONFIGURATION, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) value = phy_read(phydev, REG_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) value |= BIT(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) phy_write(phydev, REG_INTERRUPT_MASK, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void rk630_phy_wol_disable(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Switch to page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) phy_write(phydev, REG_PAGE_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) value = phy_read(phydev, REG_GLOBAL_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) value &= ~BIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) phy_write(phydev, REG_GLOBAL_CONFIGURATION, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void rk630_phy_ieee_set(struct phy_device *phydev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Switch to page 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) phy_write(phydev, REG_PAGE_SEL, 0x0100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) value = phy_read(phydev, REG_PAGE1_EEE_CONFIGURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) value |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) value &= ~BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) phy_write(phydev, REG_PAGE1_EEE_CONFIGURE, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Switch to page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) phy_write(phydev, REG_PAGE_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void rk630_phy_set_uaps(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Switch to page 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) phy_write(phydev, REG_PAGE_SEL, 0x0100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) value = phy_read(phydev, REG_PAGE1_UAPS_CONFIGURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) value |= BIT(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) phy_write(phydev, REG_PAGE1_UAPS_CONFIGURE, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Switch to page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) phy_write(phydev, REG_PAGE_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void rk630_phy_s40_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) phy_write(phydev, 0, phy_read(phydev, 0) & ~BIT(13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Switch to page 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) phy_write(phydev, REG_PAGE_SEL, 0x0100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Disable APS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Switch to page 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) phy_write(phydev, REG_PAGE_SEL, 0x0200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* PHYAFE TRX optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) phy_write(phydev, REG_PAGE2_AFE_CTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Switch to page 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) phy_write(phydev, REG_PAGE_SEL, 0x0600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* PHYAFE TX optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, 0x708f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* PHYAFE RX optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) phy_write(phydev, REG_PAGE6_AFE_RX_CTRL, 0xf000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) phy_write(phydev, REG_PAGE6_AFE_DRIVER2, 0x1530);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Switch to page 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) phy_write(phydev, REG_PAGE_SEL, 0x0800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* PHYAFE TRX optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) phy_write(phydev, REG_PAGE8_AFE_CTRL, 0x00bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Switch to page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) phy_write(phydev, REG_PAGE_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void rk630_phy_t22_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct rk630_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Switch to page 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) phy_write(phydev, REG_PAGE_SEL, 0x0100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Disable APS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Switch to page 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) phy_write(phydev, REG_PAGE_SEL, 0x0200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* PHYAFE TRX optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) phy_write(phydev, REG_PAGE2_AFE_CTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Switch to page 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) phy_write(phydev, REG_PAGE_SEL, 0x0600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* PHYAFE ADC optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) phy_write(phydev, REG_PAGE6_ADC_ANONTROL, 0x5540);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* PHYAFE Gain optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) phy_write(phydev, REG_PAGE6_GAIN_ANONTROL, 0x0400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* PHYAFE EQ optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, 0x1088);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (priv->tx_level_100M <= 0 || priv->tx_level_10M <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rk630_phy_t22_get_tx_level_from_efuse(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* PHYAFE TX optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) phy_write(phydev, REG_PAGE6_AFE_DRIVER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) (priv->tx_level_100M << 8) | priv->tx_level_10M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* PHYAFE CP current optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) phy_write(phydev, REG_PAGE6_CP_CURRENT, 0x0575);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* ADC OP BIAS optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) phy_write(phydev, REG_PAGE6_ADC_OP_BIAS, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Rx signal detctor level optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) phy_write(phydev, REG_PAGE6_RX_DECTOR, 0x0408);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* PHYAFE PDCW optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) phy_write(phydev, REG_PAGE6_AFE_PDCW, 0x8880);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Switch to page 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) phy_write(phydev, REG_PAGE_SEL, 0x0800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Disable auto-cal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) phy_write(phydev, REG_PAGE8_AUTO_CAL, 0x0844);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Switch to page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) phy_write(phydev, REG_PAGE_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Disable eee mode advertised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) phy_write(phydev, REG_MMD_ACCESS_CONTROL, 0x0007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) phy_write(phydev, REG_MMD_ACCESS_DATA_ADDRESS, 0x003c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) phy_write(phydev, REG_MMD_ACCESS_CONTROL, 0x4007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) phy_write(phydev, REG_MMD_ACCESS_DATA_ADDRESS, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int rk630_phy_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (phydev->mdio.addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case PHY_ADDR_S40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) rk630_phy_s40_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Ultra Auto-Power Saving Mode (UAPS) is designed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * save power when cable is not plugged into PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) rk630_phy_set_uaps(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case PHY_ADDR_T22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rk630_phy_t22_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) phydev_err(phydev, "Unsupported address for current phy: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) phydev->mdio.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rk630_phy_ieee_set(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static irqreturn_t rk630_wol_irq_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct rk630_phy_priv *priv = (struct rk630_phy_priv *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) phy_write(priv->phydev, REG_INTERRUPT_STATUS, BIT(14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) wake_lock_timeout(&priv->wol_wake_lock, msecs_to_jiffies(8000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int rk630_phy_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct rk630_phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) phydev->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) priv->wol_irq = of_irq_get_byname(phydev->mdio.dev.of_node, "wol_irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (priv->wol_irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return priv->wol_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (priv->wol_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) wake_lock_init(&priv->wol_wake_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) WAKE_LOCK_SUSPEND, "wol_wake_lock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = devm_request_threaded_irq(&phydev->mdio.dev, priv->wol_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) NULL, rk630_wol_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) IRQF_TRIGGER_FALLING | IRQF_SHARED | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "wol_irq", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) wake_lock_destroy(&priv->wol_wake_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) phydev_err(phydev, "request wol_irq failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) disable_irq(priv->wol_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) enable_irq_wake(priv->wol_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) priv->phydev = phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void rk630_phy_remove(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct rk630_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (priv->wol_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) wake_lock_destroy(&priv->wol_wake_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int rk630_phy_suspend(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct rk630_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (priv->wol_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) rk630_phy_wol_enable(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) phy_write(phydev, REG_INTERRUPT_MASK, BIT(14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) enable_irq(priv->wol_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return genphy_suspend(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int rk630_phy_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct rk630_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (priv->wol_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) rk630_phy_wol_disable(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) phy_write(phydev, REG_INTERRUPT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) disable_irq(priv->wol_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return genphy_resume(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct phy_driver rk630_phy_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .phy_id = RK630_PHY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .phy_id_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = "RK630 PHY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .features = PHY_BASIC_FEATURES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .probe = rk630_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .remove = rk630_phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .soft_reset = genphy_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .config_init = rk630_phy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .config_aneg = genphy_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .read_status = genphy_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .suspend = rk630_phy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .resume = rk630_phy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct mdio_device_id __maybe_unused rk630_phy_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { RK630_PHY_ID, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) module_phy_driver(rk630_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_AUTHOR("David Wu <david.wu@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_DESCRIPTION("Rockchip RK630 Ethernet PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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