^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/net/phy/realtek.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Driver for Realtek PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Johnson Leung <r58129@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2004 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RTL821x_PHYSR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RTL821x_PHYSR_DUPLEX BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RTL821x_PHYSR_SPEED GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTL821x_INER 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTL8211B_INER_INIT 0x6400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTL8211E_INER_LINK_STATUS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTL8211F_INER_LINK_STATUS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTL821x_INSR 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTL821x_EXT_PAGE_SELECT 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTL821x_PAGE_SELECT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTL8211F_PHYCR1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTL8211F_INSR 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTL8211F_TX_DELAY BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTL8211F_RX_DELAY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTL8211F_ALDPS_PLL_OFF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTL8211F_ALDPS_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTL8211E_CTRL_DELAY BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTL8211E_TX_DELAY BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RTL8211E_RX_DELAY BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RTL8201F_ISR 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RTL8201F_IER 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RTL8366RB_POWER_SAVE 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RTL8366RB_POWER_SAVE_ON BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RTL_SUPPORTS_5000FULL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RTL_SUPPORTS_2500FULL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RTL_SUPPORTS_10000FULL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RTL_ADV_2500FULL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RTL_LPADV_10000FULL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RTL_LPADV_5000FULL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RTL_LPADV_2500FULL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RTLGEN_SPEED_MASK 0x0630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RTL_GENERIC_PHYID 0x001cc800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_DESCRIPTION("Realtek PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_AUTHOR("Johnson Leung");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int rtl821x_read_page(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return __phy_read(phydev, RTL821x_PAGE_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int rtl821x_write_page(struct phy_device *phydev, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int rtl8201_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) err = phy_read(phydev, RTL8201F_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return (err < 0) ? err : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int rtl821x_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) err = phy_read(phydev, RTL821x_INSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return (err < 0) ? err : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int rtl8211f_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return (err < 0) ? err : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int rtl8201_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val = BIT(13) | BIT(12) | BIT(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int rtl8211b_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) err = phy_write(phydev, RTL821x_INER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) RTL8211B_INER_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) err = phy_write(phydev, RTL821x_INER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int rtl8211e_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) err = phy_write(phydev, RTL821x_INER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) RTL8211E_INER_LINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) err = phy_write(phydev, RTL821x_INER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int rtl8211f_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val = RTL8211F_INER_LINK_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int rtl8211_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Quirk was copied from vendor driver. Unfortunately it includes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * description of the magic numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) phy_write(phydev, 0x17, 0x2138);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) phy_write(phydev, 0x0e, 0x0260);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) phy_write(phydev, 0x17, 0x2108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) phy_write(phydev, 0x0e, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int rtl8211c_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* RTL8211C has an issue when operating in Gigabit slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return phy_set_bits(phydev, MII_CTRL1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int rtl8211f_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u16 val_txdly, val_rxdly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val = RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_XTAL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) switch (phydev->interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case PHY_INTERFACE_MODE_RGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val_txdly = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val_rxdly = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case PHY_INTERFACE_MODE_RGMII_RXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val_txdly = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val_rxdly = RTL8211F_RX_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case PHY_INTERFACE_MODE_RGMII_TXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val_txdly = RTL8211F_TX_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) val_rxdly = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case PHY_INTERFACE_MODE_RGMII_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val_txdly = RTL8211F_TX_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val_rxdly = RTL8211F_RX_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) default: /* the rest of the modes imply leaving delay as is. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val_txdly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, "Failed to update the TX delay register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val_txdly ? "Enabling" : "Disabling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val_txdly ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val_rxdly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_err(dev, "Failed to update the RX delay register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val_rxdly ? "Enabling" : "Disabling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val_rxdly ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int rtl821x_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = genphy_resume(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int rtl8211e_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int ret = 0, oldpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) switch (phydev->interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case PHY_INTERFACE_MODE_RGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val = RTL8211E_CTRL_DELAY | 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case PHY_INTERFACE_MODE_RGMII_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case PHY_INTERFACE_MODE_RGMII_RXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case PHY_INTERFACE_MODE_RGMII_TXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) default: /* the rest of the modes imply leaving delays as is. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* According to a sample driver there is a 0x1c config register on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * 0xa4 extension page (0x7) layout. It can be used to disable/enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * The configuration register definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * 14 = reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * 13 = Force Tx RX Delay controlled by bit12 bit11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * 12 = RX Delay, 11 = TX Delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * 10:0 = Test && debug settings reserved by realtek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) oldpage = phy_select_page(phydev, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (oldpage < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) goto err_restore_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto err_restore_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) err_restore_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return phy_restore_page(phydev, oldpage, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int rtl8211b_suspend(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) phy_write(phydev, MII_MMD_DATA, BIT(9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return genphy_suspend(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int rtl8211b_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) phy_write(phydev, MII_MMD_DATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return genphy_resume(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int rtl8366rb_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RTL8366RB_POWER_SAVE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(&phydev->mdio.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "error enabling power management\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* get actual speed to cover the downshift case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int rtlgen_get_speed(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!phydev->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) val = phy_read_paged(phydev, 0xa43, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) switch (val & RTLGEN_SPEED_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case 0x0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) phydev->speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case 0x0010:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) phydev->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 0x0020:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) phydev->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case 0x0200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) phydev->speed = SPEED_10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case 0x0210:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) phydev->speed = SPEED_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case 0x0220:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) phydev->speed = SPEED_5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int rtlgen_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = genphy_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return rtlgen_get_speed(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rtl821x_write_page(phydev, 0xa5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = __phy_read(phydev, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) rtl821x_write_page(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rtl821x_write_page(phydev, 0xa5d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = __phy_read(phydev, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) rtl821x_write_page(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) rtl821x_write_page(phydev, 0xa5d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = __phy_read(phydev, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) rtl821x_write_page(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) rtl821x_write_page(phydev, 0xa5d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = __phy_write(phydev, 0x10, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rtl821x_write_page(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int ret = rtlgen_read_mmd(phydev, devnum, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret != -EOPNOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) rtl821x_write_page(phydev, 0xa6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = __phy_read(phydev, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) rtl821x_write_page(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) rtl821x_write_page(phydev, 0xa6d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = __phy_read(phydev, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) rtl821x_write_page(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rtl821x_write_page(phydev, 0xa6d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = __phy_read(phydev, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) rtl821x_write_page(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret != -EOPNOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rtl821x_write_page(phydev, 0xa6d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = __phy_write(phydev, 0x12, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rtl821x_write_page(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int rtl822x_get_features(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) val = phy_read_paged(phydev, 0xa61, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) phydev->supported, val & RTL_SUPPORTS_2500FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) phydev->supported, val & RTL_SUPPORTS_5000FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) phydev->supported, val & RTL_SUPPORTS_10000FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return genphy_read_abilities(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int rtl822x_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (phydev->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u16 adv2500 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) phydev->advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) adv2500 = RTL_ADV_2500FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) RTL_ADV_2500FULL, adv2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return __genphy_config_aneg(phydev, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int rtl822x_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (phydev->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (lpadv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return lpadv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = genphy_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return rtlgen_get_speed(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) val = phy_read(phydev, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) phy_write(phydev, RTL821x_PAGE_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return val >= 0 && val & RTL_SUPPORTS_2500FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int rtlgen_match_phy_device(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return phydev->phy_id == RTL_GENERIC_PHYID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) !rtlgen_supports_2_5gbps(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int rtl8226_match_phy_device(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return phydev->phy_id == RTL_GENERIC_PHYID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) rtlgen_supports_2_5gbps(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int rtlgen_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int ret = genphy_resume(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Internal PHY's from RTL8168h up may not be instantly ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static struct phy_driver realtek_drvs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PHY_ID_MATCH_EXACT(0x00008201),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .name = "RTL8201CP Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PHY_ID_MATCH_EXACT(0x001cc816),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .name = "RTL8201F Fast Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .ack_interrupt = &rtl8201_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .config_intr = &rtl8201_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PHY_ID_MATCH_MODEL(0x001cc880),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .name = "RTL8208 Fast Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .read_mmd = genphy_read_mmd_unsupported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .write_mmd = genphy_write_mmd_unsupported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PHY_ID_MATCH_EXACT(0x001cc910),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .name = "RTL8211 Gigabit Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .config_aneg = rtl8211_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .read_mmd = &genphy_read_mmd_unsupported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .write_mmd = &genphy_write_mmd_unsupported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PHY_ID_MATCH_EXACT(0x001cc912),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .name = "RTL8211B Gigabit Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .ack_interrupt = &rtl821x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .config_intr = &rtl8211b_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .read_mmd = &genphy_read_mmd_unsupported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .write_mmd = &genphy_write_mmd_unsupported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .suspend = rtl8211b_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .resume = rtl8211b_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PHY_ID_MATCH_EXACT(0x001cc913),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "RTL8211C Gigabit Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .config_init = rtl8211c_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .read_mmd = &genphy_read_mmd_unsupported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .write_mmd = &genphy_write_mmd_unsupported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PHY_ID_MATCH_EXACT(0x001cc914),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .name = "RTL8211DN Gigabit Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .ack_interrupt = rtl821x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .config_intr = rtl8211e_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PHY_ID_MATCH_EXACT(0x001cc915),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .name = "RTL8211E Gigabit Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .config_init = &rtl8211e_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .ack_interrupt = &rtl821x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .config_intr = &rtl8211e_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PHY_ID_MATCH_EXACT(0x001cc916),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .name = "RTL8211F Gigabit Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .config_init = &rtl8211f_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .ack_interrupt = &rtl8211f_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .config_intr = &rtl8211f_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .resume = rtl821x_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .name = "Generic FE-GE Realtek PHY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .match_phy_device = rtlgen_match_phy_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .read_status = rtlgen_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .resume = rtlgen_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .read_mmd = rtlgen_read_mmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .write_mmd = rtlgen_write_mmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .name = "RTL8226 2.5Gbps PHY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .match_phy_device = rtl8226_match_phy_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .get_features = rtl822x_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .config_aneg = rtl822x_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .read_status = rtl822x_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .resume = rtlgen_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .read_mmd = rtl822x_read_mmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .write_mmd = rtl822x_write_mmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PHY_ID_MATCH_EXACT(0x001cc840),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .get_features = rtl822x_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .config_aneg = rtl822x_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .read_status = rtl822x_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .resume = rtlgen_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .read_page = rtl821x_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .write_page = rtl821x_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .read_mmd = rtl822x_read_mmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .write_mmd = rtl822x_write_mmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PHY_ID_MATCH_EXACT(0x001cc961),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .name = "RTL8366RB Gigabit Ethernet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .config_init = &rtl8366rb_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* These interrupts are handled by the irq controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * embedded inside the RTL8366RB, they get unmasked when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * irq is requested and ACKed by reading the status register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * which is done by the irqchip code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .ack_interrupt = genphy_no_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .config_intr = genphy_no_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) module_phy_driver(realtek_drvs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { PHY_ID_MATCH_VENDOR(0x001cc800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MODULE_DEVICE_TABLE(mdio, realtek_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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