^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/net/phy/qsemi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for Quality Semiconductor PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Andy Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2004 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MII_QS6612_MCR 17 /* Mode Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MII_QS6612_FTR 27 /* Factory Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MII_QS6612_MCO 28 /* Misc. Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MII_QS6612_ISR 29 /* Interrupt Source Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MII_QS6612_IMR_INIT 0x003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QS6612_PCR_AN_COMPLETE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QS6612_PCR_RLBEN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QS6612_PCR_DCREN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QS6612_PCR_4B5BEN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QS6612_PCR_TX_ISOLATE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QS6612_PCR_MLT3_DIS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QS6612_PCR_SCRM_DESCRM 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MODULE_DESCRIPTION("Quality Semiconductor PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_AUTHOR("Andy Fleming");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Returns 0, unless there's a write error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int qs6612_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* The PHY powers up isolated on the RPX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * so send a command to allow operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * XXX - My docs indicate this should be 0x0940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * ...or something. The current value sets three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * reserved bits, bit 11, which specifies it should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * set to one, bit 10, which specifies it should be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * to 0, and bit 7, which doesn't specify. However, my
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * docs are preliminary, and I will leave it like this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * until someone more knowledgable corrects me or it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * -- Andy Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return phy_write(phydev, MII_QS6612_PCR, 0x0dc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int qs6612_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) err = phy_read(phydev, MII_QS6612_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) err = phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) err = phy_read(phydev, MII_EXPANSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int qs6612_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) err = phy_write(phydev, MII_QS6612_IMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MII_QS6612_IMR_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err = phy_write(phydev, MII_QS6612_IMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct phy_driver qs6612_driver[] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .phy_id = 0x00181440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "QS6612",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .config_init = qs6612_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .ack_interrupt = qs6612_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .config_intr = qs6612_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) module_phy_driver(qs6612_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct mdio_device_id __maybe_unused qs6612_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x00181440, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODULE_DEVICE_TABLE(mdio, qs6612_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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