^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* NXP TJA1100 BroadRReach PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2018 Marek Vasut <marex@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/ethtool_netlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PHY_ID_MASK 0xfffffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PHY_ID_TJA1100 0x0180dc40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PHY_ID_TJA1101 0x0180dd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHY_ID_TJA1102 0x0180dc80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MII_ECTRL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MII_ECTRL_LINK_CONTROL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MII_ECTRL_CABLE_TEST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MII_ECTRL_CONFIG_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MII_ECTRL_WAKE_REQUEST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MII_CFG1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MII_CFG1_MASTER_SLAVE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MII_CFG1_AUTO_OP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MII_CFG1_SLEEP_CONFIRM BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MII_CFG1_LED_MODE_LINKUP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MII_CFG1_LED_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MII_CFG2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MII_INTSRC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MII_INTSRC_TEMP_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MII_INTSRC_UV_ERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MII_INTEN 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MII_INTEN_LINK_FAIL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MII_INTEN_LINK_UP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MII_COMMSTAT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MII_COMMSTAT_LINK_UP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MII_COMMSTAT_SQI_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MII_GENSTAT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MII_GENSTAT_PLL_LOCKED BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MII_EXTSTAT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MII_EXTSTAT_SHORT_DETECT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MII_EXTSTAT_OPEN_DETECT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MII_EXTSTAT_POLARITY_DETECT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MII_COMMCFG 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MII_COMMCFG_AUTO_OP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct tja11xx_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) char *hwmon_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct phy_device *phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct work_struct phy_register_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct tja11xx_phy_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const char *string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { "phy_polarity_detect", 25, 6, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { "phy_open_detect", 25, 7, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { "phy_short_detect", 25, 8, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 150, 30000, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int phy_modify_check(struct phy_device *phydev, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 mask, u16 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = phy_modify(phydev, reg, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return tja11xx_check(phydev, reg, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int tja11xx_enable_reg_write(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int tja11xx_enable_link_control(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int tja11xx_disable_link_control(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int tja11xx_wakeup(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = phy_read(phydev, MII_ECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) switch (ret & MII_ECTRL_POWER_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case MII_ECTRL_POWER_MODE_NO_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case MII_ECTRL_POWER_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case MII_ECTRL_POWER_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = phy_modify_check(phydev, MII_ECTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MII_ECTRL_POWER_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MII_ECTRL_POWER_MODE_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MII_ECTRL_POWER_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = phy_modify_check(phydev, MII_GENSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MII_GENSTAT_PLL_LOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MII_GENSTAT_PLL_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return tja11xx_enable_link_control(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int tja11xx_soft_reset(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = tja11xx_enable_reg_write(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return genphy_soft_reset(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bool finished = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (phydev->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!phydev->drv->cable_test_start ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) !phydev->drv->cable_test_get_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = phydev->drv->cable_test_start(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* According to the documentation this test takes 100 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = phydev->drv->cable_test_get_status(phydev, &finished);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (finished)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ethnl_cable_test_finished(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int tja11xx_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret, changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u16 ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) switch (phydev->master_slave_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case MASTER_SLAVE_CFG_MASTER_FORCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ctl |= MII_CFG1_MASTER_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case MASTER_SLAVE_CFG_SLAVE_FORCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case MASTER_SLAVE_CFG_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case MASTER_SLAVE_CFG_UNSUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto do_test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) phydev_warn(phydev, "Unsupported Master/Slave mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (changed < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) do_test:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = tja11xx_config_aneg_cable_test(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return __genphy_config_aneg(phydev, changed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int tja11xx_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = tja11xx_enable_reg_write(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) phydev->autoneg = AUTONEG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) phydev->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (phydev->phy_id & PHY_ID_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case PHY_ID_TJA1100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = phy_modify(phydev, MII_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MII_CFG1_LED_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MII_CFG1_LED_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case PHY_ID_TJA1101:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case PHY_ID_TJA1102:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MII_CFG2_SLEEP_REQUEST_TO_16MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = tja11xx_wakeup(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* ACK interrupts by reading the status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = phy_read(phydev, MII_INTSRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int tja11xx_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = genphy_update_link(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = phy_read(phydev, MII_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret & MII_CFG1_MASTER_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (phydev->link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = phy_read(phydev, MII_COMMSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!(ret & MII_COMMSTAT_LINK_UP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) phydev->link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int tja11xx_get_sqi(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = phy_read(phydev, MII_COMMSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int tja11xx_get_sqi_max(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return MII_COMMSTAT_SQI_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int tja11xx_get_sset_count(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ARRAY_SIZE(tja11xx_hw_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) strncpy(data + i * ETH_GSTRING_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void tja11xx_get_stats(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) data[i] = U64_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) data[i] = ret & tja11xx_hw_stats[i].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) data[i] >>= tja11xx_hw_stats[i].off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int tja11xx_hwmon_read(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 attr, int channel, long *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = phy_read(phydev, MII_INTSRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *value = !!(ret & MII_INTSRC_TEMP_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = phy_read(phydev, MII_INTSRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *value = !!(ret & MII_INTSRC_UV_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static umode_t tja11xx_hwmon_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .is_visible = tja11xx_hwmon_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .read = tja11xx_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .ops = &tja11xx_hwmon_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .info = tja11xx_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int tja11xx_hwmon_register(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct tja11xx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!priv->hwmon_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) for (i = 0; priv->hwmon_name[i]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (hwmon_is_bad_char(priv->hwmon_name[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) priv->hwmon_name[i] = '_';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) priv->hwmon_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &tja11xx_hwmon_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return PTR_ERR_OR_ZERO(priv->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int tja11xx_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct tja11xx_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) priv->phydev = phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return tja11xx_hwmon_register(phydev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void tja1102_p1_register(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) phy_register_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct phy_device *phydev_phy0 = priv->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct mii_bus *bus = phydev_phy0->mdio.bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct device *dev = &phydev_phy0->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct phy_device *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) addr = of_mdio_parse_addr(dev, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (addr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(dev, "Can't parse addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) } else if (addr != phydev_phy0->mdio.addr + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Currently we care only about double PHY chip TJA1102.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * If some day NXP will decide to bring chips with more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * PHYs, this logic should be reworked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(dev, "Unexpected address. Should be: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) phydev_phy0->mdio.addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (mdiobus_is_registered_device(bus, addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(dev, "device is already registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Real PHY ID of Port 1 is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(dev, "Can't create PHY device for Port 1: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Overwrite parent device. phy_device_create() set parent to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * the mii_bus->dev, which is not correct in case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) phy->mdio.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* All resources needed for Port 1 should be already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * available for Port 0. Both ports use the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * interrupt line, so -EPROBE_DEFER would make no sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) phy_device_free(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int tja1102_p0_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct tja11xx_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) priv->phydev = phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = tja11xx_hwmon_register(phydev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) schedule_work(&priv->phy_register_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = phy_read(phydev, MII_PHYSID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* TJA1102 Port 1 has phyid 0 and doesn't support temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * and undervoltage alarms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (port0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return ret ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return !ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int tja1102_p0_match_phy_device(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return tja1102_match_phy_device(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int tja1102_p1_match_phy_device(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return tja1102_match_phy_device(phydev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int tja11xx_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = phy_read(phydev, MII_INTSRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return (ret < 0) ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int tja11xx_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return phy_write(phydev, MII_INTEN, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int tja11xx_cable_test_start(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = tja11xx_wakeup(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = tja11xx_disable_link_control(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * | BI_DA+ | BI_DA- | Result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * | open | open | open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * | + short to - | - short to + | short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * | short to Vdd | open | open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * | open | shot to Vdd | open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * | short to Vdd | short to Vdd | short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * | shot to GND | open | open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * | open | shot to GND | open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * | short to GND | shot to GND | short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * | connected to active link partner (master) | shot and open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int tja11xx_cable_test_report_trans(u32 result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if ((result & mask) == mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* connected to active link partner (master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else if ((result & mask) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return ETHTOOL_A_CABLE_RESULT_CODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } else if (result & MII_EXTSTAT_SHORT_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } else if (result & MII_EXTSTAT_OPEN_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int tja11xx_cable_test_report(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = phy_read(phydev, MII_EXTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) tja11xx_cable_test_report_trans(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int tja11xx_cable_test_get_status(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) bool *finished)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *finished = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = phy_read(phydev, MII_ECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!(ret & MII_ECTRL_CABLE_TEST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *finished = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return tja11xx_cable_test_report(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static struct phy_driver tja11xx_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .name = "NXP TJA1100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .features = PHY_BASIC_T1_FEATURES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .probe = tja11xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .soft_reset = tja11xx_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .config_aneg = tja11xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .config_init = tja11xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .read_status = tja11xx_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .get_sqi = tja11xx_get_sqi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .get_sqi_max = tja11xx_get_sqi_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .set_loopback = genphy_loopback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .get_sset_count = tja11xx_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .get_strings = tja11xx_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .get_stats = tja11xx_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .name = "NXP TJA1101",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .features = PHY_BASIC_T1_FEATURES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .probe = tja11xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .soft_reset = tja11xx_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .config_aneg = tja11xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .config_init = tja11xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .read_status = tja11xx_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .get_sqi = tja11xx_get_sqi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .get_sqi_max = tja11xx_get_sqi_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .set_loopback = genphy_loopback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .get_sset_count = tja11xx_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .get_strings = tja11xx_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .get_stats = tja11xx_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .name = "NXP TJA1102 Port 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .features = PHY_BASIC_T1_FEATURES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .flags = PHY_POLL_CABLE_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .probe = tja1102_p0_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .soft_reset = tja11xx_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .config_aneg = tja11xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .config_init = tja11xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .read_status = tja11xx_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .get_sqi = tja11xx_get_sqi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .get_sqi_max = tja11xx_get_sqi_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .match_phy_device = tja1102_p0_match_phy_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .set_loopback = genphy_loopback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .get_sset_count = tja11xx_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .get_strings = tja11xx_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .get_stats = tja11xx_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .ack_interrupt = tja11xx_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .config_intr = tja11xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .cable_test_start = tja11xx_cable_test_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .cable_test_get_status = tja11xx_cable_test_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .name = "NXP TJA1102 Port 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .features = PHY_BASIC_T1_FEATURES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .flags = PHY_POLL_CABLE_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* currently no probe for Port 1 is need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .soft_reset = tja11xx_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .config_aneg = tja11xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .config_init = tja11xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .read_status = tja11xx_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .get_sqi = tja11xx_get_sqi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .get_sqi_max = tja11xx_get_sqi_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .match_phy_device = tja1102_p1_match_phy_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .set_loopback = genphy_loopback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .get_sset_count = tja11xx_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .get_strings = tja11xx_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .get_stats = tja11xx_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .ack_interrupt = tja11xx_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .config_intr = tja11xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .cable_test_start = tja11xx_cable_test_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .cable_test_get_status = tja11xx_cable_test_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) module_phy_driver(tja11xx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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