^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Microsemi VSC85xx PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MSCC_PHY_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MSCC_PHY_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #if IS_ENABLED(CONFIG_MACSEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mscc_macsec.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum rgmii_clock_delay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) RGMII_CLK_DELAY_0_2_NS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) RGMII_CLK_DELAY_0_8_NS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) RGMII_CLK_DELAY_1_1_NS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) RGMII_CLK_DELAY_1_7_NS = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) RGMII_CLK_DELAY_2_0_NS = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) RGMII_CLK_DELAY_2_3_NS = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) RGMII_CLK_DELAY_2_6_NS = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) RGMII_CLK_DELAY_3_4_NS = 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Microsemi VSC85xx PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* IEEE 802. Std Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MSCC_PHY_BYPASS_CONTROL 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DISABLE_HP_AUTO_MDIX_MASK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DISABLE_POLARITY_CORR_MASK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PARALLEL_DET_IGNORE_ADVERTISED 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MSCC_PHY_EXT_CNTL_STATUS 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SMI_BROADCAST_WR_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MSCC_PHY_ERR_RX_CNT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MSCC_PHY_ERR_FALSE_CARRIER_CNT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MSCC_PHY_ERR_LINK_DISCONNECT_CNT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ERR_CNT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MSCC_PHY_EXT_PHY_CNTL_1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAC_IF_SELECTION_MASK 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAC_IF_SELECTION_GMII 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAC_IF_SELECTION_RMII 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAC_IF_SELECTION_RGMII 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAC_IF_SELECTION_POS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VSC8584_MAC_IF_SELECTION_MASK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VSC8584_MAC_IF_SELECTION_SGMII 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VSC8584_MAC_IF_SELECTION_1000BASEX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VSC8584_MAC_IF_SELECTION_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FAR_END_LOOPBACK_MODE_MASK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MEDIA_OP_MODE_MASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MEDIA_OP_MODE_COPPER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MEDIA_OP_MODE_SERDES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MEDIA_OP_MODE_1000BASEX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MEDIA_OP_MODE_100BASEFX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MEDIA_OP_MODE_AMS_COPPER_SERDES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MEDIA_OP_MODE_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MSCC_PHY_EXT_PHY_CNTL_2 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MII_VSC85XX_INT_MASK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MII_VSC85XX_INT_MASK_MDINT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MII_VSC85XX_INT_MASK_WOL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MII_VSC85XX_INT_MASK_EXT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MII_VSC85XX_INT_STATUS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MII_VSC85XX_INT_MASK_MASK (MII_VSC85XX_INT_MASK_MDINT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MII_VSC85XX_INT_MASK_LINK_CHG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MII_VSC85XX_INT_MASK_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MSCC_PHY_WOL_MAC_CONTROL 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EDGE_RATE_CNTL_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EDGE_RATE_CNTL_MASK 0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSCC_PHY_DEV_AUX_CNTL 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MSCC_PHY_LED_MODE_SEL 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LED_MODE_SEL_POS(x) ((x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MSCC_EXT_PAGE_CSR_CNTL_17 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MSCC_EXT_PAGE_CSR_CNTL_18 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MSCC_EXT_PAGE_CSR_CNTL_19 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MSCC_PHY_CSR_CNTL_19_REG_ADDR(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MSCC_PHY_CSR_CNTL_19_TARGET(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MSCC_PHY_CSR_CNTL_19_READ BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MSCC_PHY_CSR_CNTL_19_CMD BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MSCC_EXT_PAGE_CSR_CNTL_20 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MSCC_PHY_CSR_CNTL_20_TARGET(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PHY_MCB_TARGET 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PHY_MCB_S6G_WRITE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PHY_MCB_S6G_READ BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PHY_S6G_PLL5G_CFG0 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PHY_S6G_PLL5G_CFG2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PHY_S6G_LCPLL_CFG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PHY_S6G_PLL_CFG 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PHY_S6G_COMMON_CFG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PHY_S6G_GPC_CFG 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PHY_S6G_MISC_CFG 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PHY_MCB_S6G_CFG 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PHY_S6G_DFT_CFG2 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PHY_S6G_PLL_STATUS 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PHY_S6G_IB_STATUS0 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PHY_S6G_SYS_RST_POS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PHY_S6G_ENA_LANE_POS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PHY_S6G_ENA_LOOP_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PHY_S6G_QRATE_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PHY_S6G_IF_MODE_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PHY_S6G_PLL_ENA_OFFS_POS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PHY_S6G_PLL_FSM_ENA_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PHY_S6G_CFG2_FSM_DIS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PHY_S6G_CFG2_FSM_CLK_BP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MSCC_EXT_PAGE_ACCESS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MSCC_PHY_PAGE_CSR_CNTL MSCC_PHY_PAGE_EXTENDED_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MSCC_PHY_PAGE_MACSEC MSCC_PHY_PAGE_EXTENDED_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * in the same package.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MSCC_PHY_PAGE_1588 0x1588 /* PTP (1588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Extended Page 1 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MSCC_PHY_EXT_MODE_CNTL 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FORCE_MDI_CROSSOVER_MASK 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define FORCE_MDI_CROSSOVER_MDIX 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FORCE_MDI_CROSSOVER_MDI 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MSCC_PHY_ACTIPHY_CNTL 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PHY_ADDR_REVERSED 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DOWNSHIFT_CNTL_MASK 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DOWNSHIFT_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DOWNSHIFT_CNTL_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MSCC_PHY_EXT_PHY_CNTL_4 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PHY_CNTL_4_ADDR_POS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MSCC_PHY_VERIPHY_CNTL_2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MSCC_PHY_VERIPHY_CNTL_3 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Extended Page 2 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MSCC_PHY_CU_PMD_TX_CNTL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* RGMII setting controls at address 18E2, for VSC8572 and similar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VSC8572_RGMII_CNTL 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VSC8572_RGMII_RX_DELAY_MASK 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VSC8572_RGMII_TX_DELAY_MASK 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* RGMII controls at address 20E2, for VSC8502 and similar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VSC8502_RGMII_CNTL 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VSC8502_RGMII_RX_DELAY_MASK 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VSC8502_RGMII_TX_DELAY_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MSCC_PHY_WOL_MID_MAC_ADDR 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MSCC_PHY_WOL_LOWER_PASSWD 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MSCC_PHY_WOL_MID_PASSWD 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MSCC_PHY_WOL_UPPER_PASSWD 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MSCC_PHY_WOL_MAC_CONTROL 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SECURE_ON_ENABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SECURE_ON_PASSWD_LEN_4 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MSCC_PHY_EXTENDED_INT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MSCC_PHY_EXTENDED_INT_MS_EGR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Extended Page 3 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MSCC_PHY_SERDES_TX_VALID_CNT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MSCC_PHY_SERDES_RX_VALID_CNT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MSCC_PHY_SERDES_RX_CRC_ERR_CNT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Extended page GPIO Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MSCC_DW8051_CNTL_STATUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MICRO_NSOFT_RESET 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RUN_FROM_INT_ROM 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AUTOINC_ADDR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PATCH_RAM_CLK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MICRO_PATCH_EN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DW8051_CLK_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MICRO_CLK_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MICRO_CLK_DIVIDE(x) ((x) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MSCC_DW8051_VLD_MASK 0xf1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* x Address in range 1-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MSCC_INT_MEM_ADDR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MSCC_INT_MEM_CNTL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define READ_SFR 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define READ_PRAM 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define READ_ROM 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define READ_RAM 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define INT_MEM_WRITE_EN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define INT_MEM_DATA_M 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MSCC_PHY_PROC_CMD 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PROC_CMD_NCOMPLETED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PROC_CMD_FAILED 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PROC_CMD_SGMII_PORT(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PROC_CMD_QSGMII_PORT 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PROC_CMD_RST_CONF_PORT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PROC_CMD_RECONF_PORT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PROC_CMD_READ_MOD_WRITE_PORT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PROC_CMD_WRITE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PROC_CMD_READ 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PROC_CMD_FIBER_DISABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PROC_CMD_FIBER_100BASE_FX 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PROC_CMD_FIBER_1000BASE_X 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PROC_CMD_SGMII_MAC 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PROC_CMD_QSGMII_MAC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PROC_CMD_NO_MAC_CONF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PROC_CMD_1588_DEFAULT_INIT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PROC_CMD_NOP 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PROC_CMD_PHY_INIT 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PROC_CMD_CRC16 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PROC_CMD_FIBER_MEDIA_CONF 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MSCC_PHY_MAC_CFG_FASTLINK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MAC_CFG_MASK 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MAC_CFG_SGMII 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MAC_CFG_QSGMII 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MAC_CFG_RGMII 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Test page Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MSCC_PHY_TEST_PAGE_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MSCC_PHY_TEST_PAGE_8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TR_CLK_DISABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MSCC_PHY_TEST_PAGE_9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MSCC_PHY_TEST_PAGE_20 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MSCC_PHY_TEST_PAGE_24 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Token ring page Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MSCC_PHY_TR_CNTL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TR_WRITE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TR_ADDR(x) (0x7fff & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MSCC_PHY_TR_LSB 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MSCC_PHY_TR_MSB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Microsemi PHY ID's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Code assumes lowest nibble is 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PHY_ID_VSC8502 0x00070630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PHY_ID_VSC8504 0x000704c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PHY_ID_VSC8514 0x00070670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PHY_ID_VSC8530 0x00070560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PHY_ID_VSC8531 0x00070570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PHY_ID_VSC8540 0x00070760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PHY_ID_VSC8541 0x00070770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PHY_ID_VSC8552 0x000704e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PHY_ID_VSC856X 0x000707e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PHY_ID_VSC8572 0x000704d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PHY_ID_VSC8574 0x000704a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PHY_ID_VSC8575 0x000707d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PHY_ID_VSC8582 0x000707b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PHY_ID_VSC8584 0x000707c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MSCC_VDDMAC_1500 1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MSCC_VDDMAC_1800 1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MSCC_VDDMAC_2500 2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MSCC_VDDMAC_3300 3300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DOWNSHIFT_COUNT_MAX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MAX_LEDS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) BIT(VSC8531_LINK_1000_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) BIT(VSC8531_LINK_100_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) BIT(VSC8531_LINK_10_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) BIT(VSC8531_LINK_10_100_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) BIT(VSC8531_DUPLEX_COLLISION) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) BIT(VSC8531_COLLISION) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) BIT(VSC8531_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) BIT(VSC8584_100FX_1000X_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) BIT(VSC8531_AUTONEG_FAULT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) BIT(VSC8531_SERIAL_MODE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) BIT(VSC8531_FORCE_LED_OFF) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) BIT(VSC8531_FORCE_LED_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) BIT(VSC8531_LINK_1000_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) BIT(VSC8531_LINK_100_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) BIT(VSC8531_LINK_10_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) BIT(VSC8531_LINK_10_100_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) BIT(VSC8531_DUPLEX_COLLISION) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) BIT(VSC8531_COLLISION) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) BIT(VSC8531_ACTIVITY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) BIT(VSC8531_AUTONEG_FAULT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) BIT(VSC8531_SERIAL_MODE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) BIT(VSC8531_FORCE_LED_OFF) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) BIT(VSC8531_FORCE_LED_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MSCC_VSC8584_REVB_INT8051_FW "microchip/mscc_vsc8584_revb_int8051_fb48.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MSCC_VSC8574_REVB_INT8051_FW "microchip/mscc_vsc8574_revb_int8051_29e8.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define VSC8584_REVB 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MSCC_DEV_REV_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct reg_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct vsc85xx_hw_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) const char *string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u16 page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u16 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct vsc8531_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int rate_magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u16 supp_led_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 leds_mode[MAX_LEDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 nleds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const struct vsc85xx_hw_stat *hw_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u64 *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int nstats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* PHY address within the package. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* For multiple port PHYs; the MDIO address of the base PHY in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * package.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #if IS_ENABLED(CONFIG_MACSEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* MACsec fields:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * - One SecY per device (enforced at the s/w implementation level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * - macsec_flows: list of h/w flows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * - ingr_flows: bitmap of ingress flows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * - egr_flows: bitmap of egress flows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct macsec_secy *secy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct list_head macsec_flows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long ingr_flows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned long egr_flows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct mii_timestamper mii_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) bool input_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct vsc85xx_ptp *ptp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* LOAD/SAVE GPIO pin, used for retrieving or setting time to the PHC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct gpio_desc *load_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* For multiple port PHYs; the MDIO address of the base PHY in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * pair of two PHYs that share a 1588 engine. PHY0 and PHY2 are coupled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * PHY1 and PHY3 as well. PHY0 and PHY1 are base PHYs for their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * respective pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int ts_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 ts_base_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* ts_lock: used for per-PHY timestamping operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * phc_lock: used for per-PHY PHC opertations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct mutex ts_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct mutex phc_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Shared structure between the PHYs of the same package.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * is shared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct vsc85xx_shared_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct mutex gpio_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #if IS_ENABLED(CONFIG_OF_MDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct vsc8531_edge_rate_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 vddmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 slowdown[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #endif /* CONFIG_OF_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) enum csr_target {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MACRO_CTRL = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #if IS_ENABLED(CONFIG_MACSEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int vsc8584_macsec_init(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void vsc8584_handle_macsec_interrupt(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) void vsc8584_config_macsec_intr(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static inline int vsc8584_macsec_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static inline void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static inline void vsc8584_config_macsec_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #if IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) void vsc85xx_link_change_notify(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) void vsc8584_config_ts_intr(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int vsc8584_ptp_init(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int vsc8584_ptp_probe_once(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int vsc8584_ptp_probe(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static inline void vsc85xx_link_change_notify(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static inline void vsc8584_config_ts_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static inline int vsc8584_ptp_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static inline int vsc8584_ptp_probe_once(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static inline int vsc8584_ptp_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static inline irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #endif /* _MSCC_PHY_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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