Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015 Microchip Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/microchipphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <dt-bindings/net/microchip-lan78xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DRIVER_AUTHOR	"WOOJUNG HUH <woojung.huh@microchip.com>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DRIVER_DESC	"Microchip LAN88XX PHY driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct lan88xx_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	int	chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	int	chip_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	__u32	wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static int lan88xx_read_page(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static int lan88xx_write_page(struct phy_device *phydev, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int lan88xx_phy_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		/* unmask all source and clear them before enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		rc = phy_read(phydev, LAN88XX_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		rc = phy_write(phydev, LAN88XX_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			       LAN88XX_INT_MASK_MDINTPIN_EN_ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			       LAN88XX_INT_MASK_LINK_CHANGE_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return rc < 0 ? rc : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int lan88xx_phy_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int rc = phy_read(phydev, LAN88XX_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return rc < 0 ? rc : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int lan88xx_suspend(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct lan88xx_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* do not power down PHY when WOL is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (!priv->wolopts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		genphy_suspend(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			      u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int val, save_page, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u16 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* Save current page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	save_page = phy_save_page(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (save_page < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		phydev_warn(phydev, "Failed to get current page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* Switch to TR page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			  (data & 0xFFFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		phydev_warn(phydev, "Failed to write TR low data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			  (data & 0x00FF0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		phydev_warn(phydev, "Failed to write TR high data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Config control bits [15:13] of register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	buf |= 0x8000; /* Set [15] to Packet transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		phydev_warn(phydev, "Failed to write data in reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	usleep_range(1000, 2000);/* Wait for Data to be written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (!(val & 0x8000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			    regaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return phy_restore_page(phydev, save_page, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void lan88xx_config_TR_regs(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* Get access to Channel 0x1, Node 0xF , Register 0x01.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * MrvlTrFix1000Kp, MasterEnableTR bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* Get access to Channel b'10, Node b'1101, Register 0x06.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * SSTrKp1000Mas bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* Get access to Channel b'10, Node b'1111, Register 0x11.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 * bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* Get access to Channel b'10, Node b'1101, Register 0x10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * Write 24-bit value 0xEEFFDD to register. Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Get access to Channel b'10, Node b'1101, Register 0x13.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 * Write 24-bit value 0x071448 to register. Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* Get access to Channel b'10, Node b'1101, Register 0x12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * Write 24-bit value 0x13132F to register. Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* Get access to Channel b'10, Node b'1101, Register 0x14.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 * eee_TrKf_freeze_delay bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Get access to Channel b'01, Node b'1111, Register 0x34.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * Write 24-bit value 0x91B06C to register. Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 * FastMseSearchUpdGain1000 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Get access to Channel b'01, Node b'1111, Register 0x3E.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 * Write 24-bit value 0xC0A028 to register. Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* Get access to Channel b'01, Node b'1111, Register 0x35.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 * Write 24-bit value 0x041600 to register. Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 * FastMsePhChangeDelay1000 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* Get access to Channel b'10, Node b'1101, Register 0x03.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int lan88xx_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct lan88xx_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u32 led_modes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	priv->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	len = of_property_read_variable_u32_array(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 						  "microchip,led-modes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 						  led_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 						  0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 						  ARRAY_SIZE(led_modes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (len >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			if (led_modes[i] > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			reg |= led_modes[i] << (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		for (; i < ARRAY_SIZE(led_modes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		(void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	} else if (len == -EOVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* these values can be used to identify internal PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	phydev->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void lan88xx_remove(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct lan88xx_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		devm_kfree(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int lan88xx_set_wol(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			   struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct lan88xx_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	priv->wolopts = wol->wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void lan88xx_set_mdix(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	switch (phydev->mdix_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	case ETH_TP_MDI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		val = LAN88XX_EXT_MODE_CTRL_MDI_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	case ETH_TP_MDI_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	case ETH_TP_MDI_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	buf |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int lan88xx_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/*Zerodetect delay enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	val = phy_read_mmd(phydev, MDIO_MMD_PCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			   PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		      val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	/* Config DSP registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	lan88xx_config_TR_regs(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int lan88xx_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	lan88xx_set_mdix(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct phy_driver microchip_phy_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.phy_id		= 0x0007c130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.phy_id_mask	= 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.name		= "Microchip LAN88xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	/* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.probe		= lan88xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.remove		= lan88xx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.config_init	= lan88xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.config_aneg	= lan88xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.ack_interrupt	= lan88xx_phy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.config_intr	= lan88xx_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.suspend	= lan88xx_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.set_wol	= lan88xx_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.read_page	= lan88xx_read_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.write_page	= lan88xx_write_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) module_phy_driver(microchip_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct mdio_device_id __maybe_unused microchip_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	{ 0x0007c130, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_DEVICE_TABLE(mdio, microchip_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_LICENSE("GPL");