^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 10G 88x3310 PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based upon the ID registers, this PHY appears to be a mixture of IPs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * from two different companies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * There appears to be several different data paths through the PHY which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are automatically managed by the PHY. The following has been determined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * via observation and experimentation for a setup using single-lane Serdes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * With XAUI, observation shows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * XAUI PHYXS -- <appropriate PCS as above>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * and no switching of the host interface mode occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * If both the fiber and copper ports are connected, the first to gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * link takes priority and the other port is completely locked out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/marvell_phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/sfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MV_PMA_FW_VER0 = 0xc011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MV_PMA_FW_VER1 = 0xc012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MV_PMA_BOOT = 0xc050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MV_PMA_BOOT_FATAL = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MV_PCS_BASE_T = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MV_PCS_BASE_R = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MV_PCS_1000BASEX = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MV_PCS_CSCR1 = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MV_PCS_CSCR1_ED_MASK = 0x0300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MV_PCS_CSCR1_ED_OFF = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MV_PCS_CSCR1_ED_RX = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MV_PCS_CSCR1_ED_NLP = 0x0300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MV_PCS_CSCR1_MDIX_MASK = 0x0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MV_PCS_CSCR1_MDIX_MDI = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MV_PCS_CSSR1 = 0x8008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MV_PCS_CSSR1_SPD1_MASK = 0xc000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MV_PCS_CSSR1_SPD1_1000 = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MV_PCS_CSSR1_SPD1_100 = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MV_PCS_CSSR1_SPD1_10 = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MV_PCS_CSSR1_RESOLVED = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MV_PCS_CSSR1_MDIX = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MV_PCS_CSSR1_SPD2_MASK = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MV_PCS_CSSR1_SPD2_5000 = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MV_PCS_CSSR1_SPD2_2500 = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MV_PCS_CSSR1_SPD2_10000 = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Temperature read register (88E2110 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MV_PCS_TEMP = 0x8042,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * registers appear to set themselves to the 0x800X when AN is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * restarted, but status registers appear readable from either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Vendor2 MMD registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MV_V2_PORT_CTRL = 0xf001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MV_V2_PORT_CTRL_SWRST = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MV_V2_PORT_MAC_TYPE_MASK = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Temperature control/read registers (88X3310 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MV_V2_TEMP_CTRL = 0xf08a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MV_V2_TEMP_CTRL_MASK = 0xc000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MV_V2_TEMP_CTRL_DISABLE = 0xc000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MV_V2_TEMP = 0xf08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct mv3310_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 firmware_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bool rate_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) char *hwmon_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_HWMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static umode_t mv3310_hwmon_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (type == hwmon_chip && attr == hwmon_chip_update_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (type == hwmon_temp && attr == hwmon_temp_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int mv10g_hwmon_read_temp_reg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return mv3310_hwmon_read_temp_reg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else /* MARVELL_PHY_ID_88E2110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return mv2110_hwmon_read_temp_reg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 attr, int channel, long *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *value = MSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (type == hwmon_temp && attr == hwmon_temp_input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) temp = mv10g_hwmon_read_temp_reg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (temp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *value = ((temp & 0xff) - 75) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct hwmon_ops mv3310_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .is_visible = mv3310_hwmon_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .read = mv3310_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static u32 mv3310_hwmon_chip_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct hwmon_channel_info mv3310_hwmon_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .type = hwmon_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .config = mv3310_hwmon_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static u32 mv3310_hwmon_temp_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) HWMON_T_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct hwmon_channel_info mv3310_hwmon_temp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .type = hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .config = mv3310_hwmon_temp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &mv3310_hwmon_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &mv3310_hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .ops = &mv3310_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .info = mv3310_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MV_V2_TEMP_UNKNOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MV_V2_TEMP_CTRL_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int mv3310_hwmon_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int i, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!priv->hwmon_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (i = j = 0; priv->hwmon_name[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (isalnum(priv->hwmon_name[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (i != j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) priv->hwmon_name[j] = priv->hwmon_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) priv->hwmon_name[j] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = mv3310_hwmon_config(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) priv->hwmon_name, phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) &mv3310_hwmon_chip_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return PTR_ERR_OR_ZERO(priv->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int mv3310_hwmon_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int mv3310_power_down(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MV_V2_PORT_CTRL_PWRDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int mv3310_power_up(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MV_V2_PORT_CTRL_PWRDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) priv->firmware_ver < 0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MV_V2_PORT_CTRL_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int mv3310_reset(struct phy_device *phydev, u32 unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int val, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unit + MDIO_CTRL1, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) !(val & MDIO_CTRL1_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 5000, 100000, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (val & MV_PCS_CSCR1_ED_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case MV_PCS_CSCR1_ED_NLP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *edpd = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case MV_PCS_CSCR1_ED_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *edpd = ETHTOOL_PHY_EDPD_NO_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *edpd = ETHTOOL_PHY_EDPD_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) switch (edpd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case 1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val = MV_PCS_CSCR1_ED_NLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case ETHTOOL_PHY_EDPD_NO_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val = MV_PCS_CSCR1_ED_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case ETHTOOL_PHY_EDPD_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val = MV_PCS_CSCR1_ED_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MV_PCS_CSCR1_ED_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (err > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) err = mv3310_reset(phydev, MV_PCS_BASE_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct phy_device *phydev = upstream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) phy_interface_t iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sfp_parse_support(phydev->sfp_bus, id, support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) iface = sfp_select_interface(phydev->sfp_bus, support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (iface != PHY_INTERFACE_MODE_10GBASER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct sfp_upstream_ops mv3310_sfp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .attach = phy_sfp_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .detach = phy_sfp_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .module_insert = mv3310_sfp_insert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int mv3310_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct mv3310_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!phydev->is_c45 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret & MV_PMA_BOOT_FATAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_warn(&phydev->mdio.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "PHY failed to boot firmware, status=%04x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_set_drvdata(&phydev->mdio.dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) priv->firmware_ver = ret << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) priv->firmware_ver |= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Powering down the port when not in use saves about 600mW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = mv3310_power_down(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = mv3310_hwmon_probe(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return phy_sfp_probe(phydev, &mv3310_sfp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void mv3310_remove(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mv3310_hwmon_config(phydev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int mv3310_suspend(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return mv3310_power_down(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int mv3310_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = mv3310_power_up(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return mv3310_hwmon_config(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * don't set bit 14 in PMA Extended Abilities (1.11), although they do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * support 2.5GBASET and 5GBASET. For these models, we can still read their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * 2.5G/5G extended abilities register (1.21). We detect these models based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * the PMA device identifier, with a mask matching models known to have this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Only some revisions of the 88X3310 family PMA seem to be impacted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int mv3310_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Check that the PHY interface type is compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) phydev->interface != PHY_INTERFACE_MODE_XAUI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) phydev->interface != PHY_INTERFACE_MODE_10GBASER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Power up so reset works */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) err = mv3310_power_up(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MV_V2_PORT_MAC_TYPE_RATE_MATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Enable EDPD mode - saving 600mW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int mv3310_get_features(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = genphy_c45_pma_read_abilities(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (mv3310_has_pma_ngbaset_quirk(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MDIO_PMA_NG_EXTABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) phydev->supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) val & MDIO_PMA_NG_EXTABLE_2_5GBT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) phydev->supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) val & MDIO_PMA_NG_EXTABLE_5GBT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int mv3310_config_mdix(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) switch (phydev->mdix_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case ETH_TP_MDI_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val = MV_PCS_CSCR1_MDIX_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case ETH_TP_MDI_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) val = MV_PCS_CSCR1_MDIX_MDIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case ETH_TP_MDI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) val = MV_PCS_CSCR1_MDIX_MDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MV_PCS_CSCR1_MDIX_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (err > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) err = mv3310_reset(phydev, MV_PCS_BASE_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int mv3310_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) bool changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = mv3310_config_mdix(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (phydev->autoneg == AUTONEG_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return genphy_c45_pma_setup_forced(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = genphy_c45_an_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Clause 45 has no standardized support for 1000BaseT, therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * use vendor registers for this mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return genphy_c45_check_and_restart_aneg(phydev, changed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int mv3310_aneg_done(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (val & MDIO_STAT1_LSTATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return genphy_c45_aneg_done(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void mv3310_update_interface(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* In "XFI with Rate Matching" mode the PHY interface is fixed at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * 10Gb. The PHY adapts the rate to actual wire speed with help of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * internal 16KB buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (priv->rate_match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) phydev->interface = PHY_INTERFACE_MODE_10GBASER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) phydev->link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* The PHY automatically switches its serdes interface (and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * active PHYXS instance) between Cisco SGMII, 10GBase-R and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * 2500BaseX modes according to the speed. Florian suggests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * setting phydev->interface to communicate this to the MAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * Only do this if we are already in one of the above modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) switch (phydev->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case SPEED_10000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) phydev->interface = PHY_INTERFACE_MODE_10GBASER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case SPEED_2500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) phydev->interface = PHY_INTERFACE_MODE_SGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int mv3310_read_status_10gbaser(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) phydev->link = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) phydev->speed = SPEED_10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) phydev->port = PORT_FIBRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int mv3310_read_status_copper(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int cssr1, speed, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) val = genphy_c45_read_link(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (cssr1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* If the link settings are not resolved, mark the link down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) phydev->link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Read the copper link settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (speed == MV_PCS_CSSR1_SPD1_SPD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) phydev->speed = SPEED_10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) phydev->speed = SPEED_5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) phydev->speed = SPEED_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case MV_PCS_CSSR1_SPD1_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) phydev->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case MV_PCS_CSSR1_SPD1_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) phydev->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case MV_PCS_CSSR1_SPD1_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) phydev->speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) phydev->port = PORT_TP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ETH_TP_MDI_X : ETH_TP_MDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (val & MDIO_AN_STAT1_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) val = genphy_c45_read_lpa(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Read the link partner's 1G advertisement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Update the pause status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) phy_resolve_aneg_pause(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int mv3310_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int err, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) phydev->speed = SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) phydev->duplex = DUPLEX_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) linkmode_zero(phydev->lp_advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) phydev->link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) phydev->pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) phydev->asym_pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) phydev->mdix = ETH_TP_MDI_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (val & MDIO_STAT1_LSTATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) err = mv3310_read_status_10gbaser(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) err = mv3310_read_status_copper(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (phydev->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mv3310_update_interface(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int mv3310_get_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct ethtool_tunable *tuna, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case ETHTOOL_PHY_EDPD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return mv3310_get_edpd(phydev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int mv3310_set_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct ethtool_tunable *tuna, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case ETHTOOL_PHY_EDPD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return mv3310_set_edpd(phydev, *(u16 *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static struct phy_driver mv3310_drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .phy_id = MARVELL_PHY_ID_88X3310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .phy_id_mask = MARVELL_PHY_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .name = "mv88x3310",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .get_features = mv3310_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .config_init = mv3310_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .probe = mv3310_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .suspend = mv3310_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .resume = mv3310_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .config_aneg = mv3310_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .aneg_done = mv3310_aneg_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .read_status = mv3310_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .get_tunable = mv3310_get_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .set_tunable = mv3310_set_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .remove = mv3310_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .phy_id = MARVELL_PHY_ID_88E2110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .phy_id_mask = MARVELL_PHY_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .name = "mv88x2110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .probe = mv3310_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .suspend = mv3310_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .resume = mv3310_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .config_init = mv3310_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .config_aneg = mv3310_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .aneg_done = mv3310_aneg_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .read_status = mv3310_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .get_tunable = mv3310_get_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .set_tunable = mv3310_set_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .remove = mv3310_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) module_phy_driver(mv3310_drivers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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